Lines Matching defs:NewReg
342 // be replaced by NewReg. Return true if any of their parent instructions may
347 // the two-address instruction also defines NewReg, as may happen with
351 // both NewReg and AntiDepReg covers it.
355 unsigned NewReg)
361 // operands, in case they may be assigned to NewReg. In this case antidep
366 // Handle cases in which this instructions defines NewReg.
371 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
375 CheckOper.getReg() != NewReg)
378 // Don't allow the instruction to define NewReg and AntiDepReg.
384 // NewReg
388 // Don't allow inline asm to define NewReg at all. Who know what it's
406 unsigned NewReg = Order[i];
408 if (NewReg == AntiDepReg) continue;
412 if (NewReg == LastNewReg) continue;
413 // If any instructions that define AntiDepReg also define the NewReg, it's
416 if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
417 // If NewReg is dead and NewReg's most recent def is not before
418 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
421 assert(((KillIndices[NewRegNewReg] == ~0u))
422 && "Kill and Def maps aren't consistent for NewReg!");
423 if (KillIndices[NewReg] != ~0u ||
424 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
425 KillIndices[AntiDepReg] > DefIndices[NewReg])
427 return NewReg;
629 if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
636 << " using " << TRI->getName(NewReg) << "!\n");
642 Q->second->setReg(NewReg);
651 UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
657 Classes[NewReg] = Classes[AntiDepReg];
658 DefIndices[NewReg] = DefIndices[AntiDepReg];
659 KillIndices[NewReg] = KillIndices[AntiDepReg];
660 assert(((KillIndices[NewReg] == ~0u) !=
661 (DefIndices[NewReg] == ~0u)) &&
662 "Kill and Def maps aren't consistent for NewReg!");
672 LastNewReg[AntiDepReg] = NewReg;
