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    Searched defs:DefIdx (Results 1 - 9 of 9) sorted by null

  /external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.h 140 unsigned DefIdx;
158 return DefIdx-1;
ScheduleDAGSDNodes.cpp 515 DefIdx = 0;
521 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
529 for (;DefIdx < NodeNumDefs; ++DefIdx) {
530 if (!Node->hasAnyUseOfValue(DefIdx))
532 ValueType = Node->getValueType(DefIdx);
533 ++DefIdx;
595 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
599 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
  /external/llvm/lib/CodeGen/
LiveIntervalAnalysis.cpp 399 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
400 if (DefIdx != -1) {
401 if (mi->isRegTiedToUseOperand(DefIdx)) {
403 end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
531 SlotIndex defIdx = getMBBStartIdx(MBB);
532 assert(getInstructionFromIndex(defIdx) == 0 &&
534 VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
    [all...]
ScheduleDAGInstrs.cpp 765 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
766 if (DefIdx != -1) {
767 const MachineOperand &MO = DefMI->getOperand(DefIdx);
769 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
778 DefIdx = Op2;
792 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
801 Latency = InstrItins->getOperandCycle(DefClass, DefIdx);
    [all...]
RegAllocFast.cpp 725 unsigned DefIdx = 0;
726 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
728 << DefIdx << ".\n");
    [all...]
InlineSpiller.cpp 890 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
    [all...]
MachineInstr.cpp     [all...]
MachineVerifier.cpp 765 unsigned defIdx;
766 if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
768 unsigned DefReg = MI->getOperand(defIdx).getReg();
844 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getRegSlot();
847 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
849 if (VNI->def != DefIdx && !MO->isEarlyClobber()) {
852 << DefIdx << " in " << LI << '\n';
856 *OS << DefIdx << " is not live in " << LI << '\n';
    [all...]
RegisterCoalescer.cpp 628 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
629 assert(DefIdx != -1);
631 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
738 SlotIndex DefIdx = UseIdx.getRegSlot();
739 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
742 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
743 assert(DVNI->def == DefIdx);
    [all...]

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