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Searched
defs:DefMI
(Results
1 - 13
of
13
) sorted by null
/external/llvm/lib/Target/ARM/
ARMHazardRecognizer.cpp
19
static bool hasRAWHazard(MachineInstr *
DefMI
, MachineInstr *MI,
30
return MI->readsRegister(
DefMI
->getOperand(0).getReg(), &TRI);
45
MachineInstr *
DefMI
= LastMI;
55
DefMI
= &*I;
59
if (TII.isFpMLxInstruction(
DefMI
->getOpcode()) &&
61
hasRAWHazard(
DefMI
, MI, TRI))) {
MLxExpansionPass.cpp
92
MachineInstr *
DefMI
= MRI->getVRegDef(Reg);
94
if (
DefMI
->getParent() != MBB)
96
if (
DefMI
->isCopyLike()) {
97
Reg =
DefMI
->getOperand(1).getReg();
99
DefMI
= MRI->getVRegDef(Reg);
102
} else if (
DefMI
->isInsertSubreg()) {
103
Reg =
DefMI
->getOperand(2).getReg();
105
DefMI
= MRI->getVRegDef(Reg);
111
return
DefMI
;
160
MachineInstr *
DefMI
= getAccDefMI(MI)
[
all
...]
/external/llvm/lib/CodeGen/
LiveIntervalAnalysis.cpp
166
MachineInstr *
DefMI
= getInstructionFromIndex(OldLR->valno->def);
167
if (
DefMI
!= 0) {
168
return
DefMI
->findRegisterDefOperandIdx(interval.reg) != -1;
[
all
...]
LiveRangeEdit.cpp
46
const MachineInstr *
DefMI
,
48
assert(
DefMI
&& "Missing instruction");
50
if (!TII.isTriviallyReMaterializable(
DefMI
, aa))
62
MachineInstr *
DefMI
= LIS.getInstructionFromIndex(VNI->def);
63
if (!
DefMI
)
65
checkRematerializable(VNI,
DefMI
, aa);
151
MachineInstr *
DefMI
= 0, *UseMI = 0;
159
if (
DefMI
&&
DefMI
!= MI)
163
DefMI
= MI
[
all
...]
PHIElimination.cpp
138
MachineInstr *
DefMI
= *I;
139
unsigned DefReg =
DefMI
->getOperand(0).getReg();
141
DefMI
->eraseFromParent();
180
const MachineInstr *
DefMI
= MRI->getVRegDef(SrcReg);
181
if (!
DefMI
|| !
DefMI
->isImplicitDef())
300
MachineInstr *
DefMI
= MRI->getVRegDef(SrcReg);
301
if (
DefMI
->isImplicitDef()) {
302
ImpDefs.insert(
DefMI
);
PeepholeOptimizer.cpp
295
MachineInstr *
DefMI
= MRI->getVRegDef(Src);
296
if (!
DefMI
|| !
DefMI
->isBitcast())
300
NumDefs =
DefMI
->getDesc().getNumDefs();
301
NumSrcs =
DefMI
->getDesc().getNumOperands() - NumDefs;
305
const MachineOperand &MO =
DefMI
->getOperand(i);
MachineCSE.cpp
132
MachineInstr *
DefMI
= MRI->getVRegDef(Reg);
133
if (
DefMI
->getParent() != MBB)
135
if (!
DefMI
->isCopy())
137
unsigned SrcReg =
DefMI
->getOperand(1).getReg();
140
if (
DefMI
->getOperand(0).getSubReg() ||
DefMI
->getOperand(1).getSubReg())
144
DEBUG(dbgs() << "Coalescing: " << *
DefMI
);
148
DefMI
->eraseFromParent();
ScheduleDAGInstrs.cpp
764
MachineInstr *
DefMI
= Def->getInstr();
765
int DefIdx =
DefMI
->findRegisterDefOperandIdx(Reg);
767
const MachineOperand &MO =
DefMI
->getOperand(DefIdx);
769
DefIdx >= (int)
DefMI
->getDesc().getNumOperands()) {
776
unsigned Op2 =
DefMI
->findRegisterDefOperandIdx(Reg, false, true, TRI);
777
if (
DefMI
->getOperand(Op2).isReg())
792
int UseCycle = TII->getOperandLatency(InstrItins,
DefMI
, DefIdx,
800
unsigned DefClass =
DefMI
->getDesc().getSchedClass();
[
all
...]
StrongPHIElimination.cpp
253
MachineInstr *
DefMI
= MRI->getVRegDef(SrcReg);
254
if (
DefMI
)
255
PHISrcDefs[
DefMI
->getParent()].push_back(
DefMI
);
TailDuplication.cpp
227
MachineInstr *
DefMI
= MRI->getVRegDef(VReg);
229
if (
DefMI
) {
230
DefBB =
DefMI
->getParent();
[
all
...]
InlineSpiller.cpp
109
MachineInstr *
DefMI
;
120
SpillReg(Reg), SpillVNI(VNI), SpillMBB(0),
DefMI
(0) {}
123
bool hasDef() const { return DefByOrigPHI ||
DefMI
; }
331
if (SVI.
DefMI
)
332
OS << " def: " << *SVI.
DefMI
;
395
DepSV.
DefMI
= SV.
DefMI
;
484
return SVI->second.
DefMI
;
602
SVI->second.
DefMI
= MI;
623
return SVI->second.
DefMI
;
[
all
...]
TwoAddressInstructionPass.cpp
96
MachineInstr *MI, MachineInstr *
DefMI
,
324
MachineInstr *MI, MachineInstr *
DefMI
,
350
return MBB ==
DefMI
->getParent();
445
MachineInstr *
DefMI
= &MI;
447
if (!
DefMI
->killsRegister(Reg))
456
DefMI
= &*Begin;
461
if (!isCopyToReg(*
DefMI
, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
[
all
...]
/external/llvm/lib/Target/X86/
X86InstrInfo.cpp
[
all
...]
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