1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef MipsISELLOWERING_H 16 #define MipsISELLOWERING_H 17 18 #include "Mips.h" 19 #include "MipsSubtarget.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/Target/TargetLowering.h" 22 23 namespace llvm { 24 namespace MipsISD { 25 enum NodeType { 26 // Start the numbering from where ISD NodeType finishes. 27 FIRST_NUMBER = ISD::BUILTIN_OP_END, 28 29 // Jump and link (call) 30 JmpLink, 31 32 // Get the Higher 16 bits from a 32-bit immediate 33 // No relation with Mips Hi register 34 Hi, 35 36 // Get the Lower 16 bits from a 32-bit immediate 37 // No relation with Mips Lo register 38 Lo, 39 40 // Handle gp_rel (small data/bss sections) relocation. 41 GPRel, 42 43 // Thread Pointer 44 ThreadPointer, 45 46 // Floating Point Branch Conditional 47 FPBrcond, 48 49 // Floating Point Compare 50 FPCmp, 51 52 // Floating Point Conditional Moves 53 CMovFP_T, 54 CMovFP_F, 55 56 // Floating Point Rounding 57 FPRound, 58 59 // Return 60 Ret, 61 62 // MAdd/Sub nodes 63 MAdd, 64 MAddu, 65 MSub, 66 MSubu, 67 68 // DivRem(u) 69 DivRem, 70 DivRemU, 71 72 BuildPairF64, 73 ExtractElementF64, 74 75 Wrapper, 76 77 DynAlloc, 78 79 Sync, 80 81 Ext, 82 Ins 83 }; 84 } 85 86 //===--------------------------------------------------------------------===// 87 // TargetLowering Implementation 88 //===--------------------------------------------------------------------===// 89 90 class MipsTargetLowering : public TargetLowering { 91 public: 92 explicit MipsTargetLowering(MipsTargetMachine &TM); 93 94 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 95 96 virtual bool allowsUnalignedMemoryAccesses (EVT VT) const; 97 98 /// LowerOperation - Provide custom lowering hooks for some operations. 99 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 100 101 /// getTargetNodeName - This method returns the name of a target specific 102 // DAG node. 103 virtual const char *getTargetNodeName(unsigned Opcode) const; 104 105 /// getSetCCResultType - get the ISD::SETCC result ValueType 106 EVT getSetCCResultType(EVT VT) const; 107 108 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 109 private: 110 // Subtarget Info 111 const MipsSubtarget *Subtarget; 112 113 bool HasMips64, IsN64, IsO32; 114 115 // Lower Operand helpers 116 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 117 CallingConv::ID CallConv, bool isVarArg, 118 const SmallVectorImpl<ISD::InputArg> &Ins, 119 DebugLoc dl, SelectionDAG &DAG, 120 SmallVectorImpl<SDValue> &InVals) const; 121 122 // Lower Operand specifics 123 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 124 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 125 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 126 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 127 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 128 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 129 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 130 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 131 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 132 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 133 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 134 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; 135 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 136 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; 137 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 138 139 virtual SDValue 140 LowerFormalArguments(SDValue Chain, 141 CallingConv::ID CallConv, bool isVarArg, 142 const SmallVectorImpl<ISD::InputArg> &Ins, 143 DebugLoc dl, SelectionDAG &DAG, 144 SmallVectorImpl<SDValue> &InVals) const; 145 146 virtual SDValue 147 LowerCall(SDValue Chain, SDValue Callee, 148 CallingConv::ID CallConv, bool isVarArg, 149 bool doesNotRet, bool &isTailCall, 150 const SmallVectorImpl<ISD::OutputArg> &Outs, 151 const SmallVectorImpl<SDValue> &OutVals, 152 const SmallVectorImpl<ISD::InputArg> &Ins, 153 DebugLoc dl, SelectionDAG &DAG, 154 SmallVectorImpl<SDValue> &InVals) const; 155 156 virtual SDValue 157 LowerReturn(SDValue Chain, 158 CallingConv::ID CallConv, bool isVarArg, 159 const SmallVectorImpl<ISD::OutputArg> &Outs, 160 const SmallVectorImpl<SDValue> &OutVals, 161 DebugLoc dl, SelectionDAG &DAG) const; 162 163 virtual MachineBasicBlock * 164 EmitInstrWithCustomInserter(MachineInstr *MI, 165 MachineBasicBlock *MBB) const; 166 167 // Inline asm support 168 ConstraintType getConstraintType(const std::string &Constraint) const; 169 170 /// Examine constraint string and operand type and determine a weight value. 171 /// The operand object must already have been set up with the operand type. 172 ConstraintWeight getSingleConstraintMatchWeight( 173 AsmOperandInfo &info, const char *constraint) const; 174 175 std::pair<unsigned, const TargetRegisterClass*> 176 getRegForInlineAsmConstraint(const std::string &Constraint, 177 EVT VT) const; 178 179 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 180 181 /// isFPImmLegal - Returns true if the target can instruction select the 182 /// specified FP immediate natively. If false, the legalizer will 183 /// materialize the FP immediate as a load from a constant pool. 184 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 185 186 virtual unsigned getJumpTableEncoding() const; 187 188 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 189 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 190 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI, 191 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 192 bool Nand = false) const; 193 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 194 MachineBasicBlock *BB, unsigned Size) const; 195 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI, 196 MachineBasicBlock *BB, unsigned Size) const; 197 }; 198 } 199 200 #endif // MipsISELLOWERING_H 201
