1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SelectionDAGISel class, which is used as the common 11 // base class for SelectionDAG-based instruction selectors. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H 16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H 17 18 #include "llvm/BasicBlock.h" 19 #include "llvm/Pass.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/CodeGen/MachineFunctionPass.h" 22 23 namespace llvm { 24 class FastISel; 25 class SelectionDAGBuilder; 26 class SDValue; 27 class MachineRegisterInfo; 28 class MachineBasicBlock; 29 class MachineFunction; 30 class MachineInstr; 31 class TargetLowering; 32 class TargetLibraryInfo; 33 class TargetInstrInfo; 34 class FunctionLoweringInfo; 35 class ScheduleHazardRecognizer; 36 class GCFunctionInfo; 37 class ScheduleDAGSDNodes; 38 class LoadInst; 39 40 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based 41 /// pattern-matching instruction selectors. 42 class SelectionDAGISel : public MachineFunctionPass { 43 public: 44 const TargetMachine &TM; 45 const TargetLowering &TLI; 46 const TargetLibraryInfo *LibInfo; 47 FunctionLoweringInfo *FuncInfo; 48 MachineFunction *MF; 49 MachineRegisterInfo *RegInfo; 50 SelectionDAG *CurDAG; 51 SelectionDAGBuilder *SDB; 52 AliasAnalysis *AA; 53 GCFunctionInfo *GFI; 54 CodeGenOpt::Level OptLevel; 55 static char ID; 56 57 explicit SelectionDAGISel(const TargetMachine &tm, 58 CodeGenOpt::Level OL = CodeGenOpt::Default); 59 virtual ~SelectionDAGISel(); 60 61 const TargetLowering &getTargetLowering() { return TLI; } 62 63 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 64 65 virtual bool runOnMachineFunction(MachineFunction &MF); 66 67 virtual void EmitFunctionEntryCode() {} 68 69 /// PreprocessISelDAG - This hook allows targets to hack on the graph before 70 /// instruction selection starts. 71 virtual void PreprocessISelDAG() {} 72 73 /// PostprocessISelDAG() - This hook allows the target to hack on the graph 74 /// right after selection. 75 virtual void PostprocessISelDAG() {} 76 77 /// Select - Main hook targets implement to select a node. 78 virtual SDNode *Select(SDNode *N) = 0; 79 80 /// SelectInlineAsmMemoryOperand - Select the specified address as a target 81 /// addressing mode, according to the specified constraint code. If this does 82 /// not match or is not implemented, return true. The resultant operands 83 /// (which will appear in the machine instruction) should be added to the 84 /// OutOps vector. 85 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 86 char ConstraintCode, 87 std::vector<SDValue> &OutOps) { 88 return true; 89 } 90 91 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 92 /// operand node N of U during instruction selection that starts at Root. 93 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 94 95 /// IsLegalToFold - Returns true if the specific operand node N of 96 /// U can be folded during instruction selection that starts at Root. 97 /// FIXME: This is a static member function because the MSP430/X86 98 /// targets, which uses it during isel. This could become a proper member. 99 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 100 CodeGenOpt::Level OptLevel, 101 bool IgnoreChains = false); 102 103 // Opcodes used by the DAG state machine: 104 enum BuiltinOpcodes { 105 OPC_Scope, 106 OPC_RecordNode, 107 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3, 108 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7, 109 OPC_RecordMemRef, 110 OPC_CaptureGlueInput, 111 OPC_MoveChild, 112 OPC_MoveParent, 113 OPC_CheckSame, 114 OPC_CheckPatternPredicate, 115 OPC_CheckPredicate, 116 OPC_CheckOpcode, 117 OPC_SwitchOpcode, 118 OPC_CheckType, 119 OPC_SwitchType, 120 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type, 121 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type, 122 OPC_CheckChild6Type, OPC_CheckChild7Type, 123 OPC_CheckInteger, 124 OPC_CheckCondCode, 125 OPC_CheckValueType, 126 OPC_CheckComplexPat, 127 OPC_CheckAndImm, OPC_CheckOrImm, 128 OPC_CheckFoldableChainNode, 129 130 OPC_EmitInteger, 131 OPC_EmitRegister, 132 OPC_EmitRegister2, 133 OPC_EmitConvertToTarget, 134 OPC_EmitMergeInputChains, 135 OPC_EmitMergeInputChains1_0, 136 OPC_EmitMergeInputChains1_1, 137 OPC_EmitCopyToReg, 138 OPC_EmitNodeXForm, 139 OPC_EmitNode, 140 OPC_MorphNodeTo, 141 OPC_MarkGlueResults, 142 OPC_CompleteMatch 143 }; 144 145 enum { 146 OPFL_None = 0, // Node has no chain or glue input and isn't variadic. 147 OPFL_Chain = 1, // Node has a chain input. 148 OPFL_GlueInput = 2, // Node has a glue input. 149 OPFL_GlueOutput = 4, // Node has a glue output. 150 OPFL_MemRefs = 8, // Node gets accumulated MemRefs. 151 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs. 152 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs. 153 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs. 154 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs. 155 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs. 156 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs. 157 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs. 158 159 OPFL_VariadicInfo = OPFL_Variadic6 160 }; 161 162 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the 163 /// number of fixed arity values that should be skipped when copying from the 164 /// root. 165 static inline int getNumFixedFromVariadicInfo(unsigned Flags) { 166 return ((Flags&OPFL_VariadicInfo) >> 4)-1; 167 } 168 169 170 protected: 171 /// DAGSize - Size of DAG being instruction selected. 172 /// 173 unsigned DAGSize; 174 175 /// ISelPosition - Node iterator marking the current position of 176 /// instruction selection as it procedes through the topologically-sorted 177 /// node list. 178 SelectionDAG::allnodes_iterator ISelPosition; 179 180 181 /// ISelUpdater - helper class to handle updates of the 182 /// instruction selection graph. 183 class ISelUpdater : public SelectionDAG::DAGUpdateListener { 184 virtual void anchor(); 185 SelectionDAG::allnodes_iterator &ISelPosition; 186 public: 187 explicit ISelUpdater(SelectionDAG::allnodes_iterator &isp) 188 : ISelPosition(isp) {} 189 190 /// NodeDeleted - Handle nodes deleted from the graph. If the 191 /// node being deleted is the current ISelPosition node, update 192 /// ISelPosition. 193 /// 194 virtual void NodeDeleted(SDNode *N, SDNode *E) { 195 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 196 ++ISelPosition; 197 } 198 199 /// NodeUpdated - Ignore updates for now. 200 virtual void NodeUpdated(SDNode *N) {} 201 }; 202 203 /// ReplaceUses - replace all uses of the old node F with the use 204 /// of the new node T. 205 void ReplaceUses(SDValue F, SDValue T) { 206 ISelUpdater ISU(ISelPosition); 207 CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISU); 208 } 209 210 /// ReplaceUses - replace all uses of the old nodes F with the use 211 /// of the new nodes T. 212 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { 213 ISelUpdater ISU(ISelPosition); 214 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISU); 215 } 216 217 /// ReplaceUses - replace all uses of the old node F with the use 218 /// of the new node T. 219 void ReplaceUses(SDNode *F, SDNode *T) { 220 ISelUpdater ISU(ISelPosition); 221 CurDAG->ReplaceAllUsesWith(F, T, &ISU); 222 } 223 224 225 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 226 /// by tblgen. Others should not call it. 227 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops); 228 229 230 public: 231 // Calls to these predicates are generated by tblgen. 232 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 233 int64_t DesiredMaskS) const; 234 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 235 int64_t DesiredMaskS) const; 236 237 238 /// CheckPatternPredicate - This function is generated by tblgen in the 239 /// target. It runs the specified pattern predicate and returns true if it 240 /// succeeds or false if it fails. The number is a private implementation 241 /// detail to the code tblgen produces. 242 virtual bool CheckPatternPredicate(unsigned PredNo) const { 243 llvm_unreachable("Tblgen should generate the implementation of this!"); 244 } 245 246 /// CheckNodePredicate - This function is generated by tblgen in the target. 247 /// It runs node predicate number PredNo and returns true if it succeeds or 248 /// false if it fails. The number is a private implementation 249 /// detail to the code tblgen produces. 250 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const { 251 llvm_unreachable("Tblgen should generate the implementation of this!"); 252 } 253 254 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, 255 unsigned PatternNo, 256 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { 257 llvm_unreachable("Tblgen should generate the implementation of this!"); 258 } 259 260 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) { 261 llvm_unreachable("Tblgen should generate this!"); 262 } 263 264 SDNode *SelectCodeCommon(SDNode *NodeToMatch, 265 const unsigned char *MatcherTable, 266 unsigned TableSize); 267 268 private: 269 270 // Calls to these functions are generated by tblgen. 271 SDNode *Select_INLINEASM(SDNode *N); 272 SDNode *Select_UNDEF(SDNode *N); 273 void CannotYetSelect(SDNode *N); 274 275 private: 276 void DoInstructionSelection(); 277 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs, 278 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo); 279 280 void PrepareEHLandingPad(); 281 void SelectAllBasicBlocks(const Function &Fn); 282 bool TryToFoldFastISelLoad(const LoadInst *LI, const Instruction *FoldInst, 283 FastISel *FastIS); 284 void FinishBasicBlock(); 285 286 void SelectBasicBlock(BasicBlock::const_iterator Begin, 287 BasicBlock::const_iterator End, 288 bool &HadTailCall); 289 void CodeGenAndEmitDAG(); 290 void LowerArguments(const BasicBlock *BB); 291 292 void ComputeLiveOutVRegInfo(); 293 294 /// Create the scheduler. If a specific scheduler was specified 295 /// via the SchedulerRegistry, use it, otherwise select the 296 /// one preferred by the target. 297 /// 298 ScheduleDAGSDNodes *CreateScheduler(); 299 300 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel 301 /// state machines that start with a OPC_SwitchOpcode node. 302 std::vector<unsigned> OpcodeOffset; 303 304 void UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 305 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 306 SDValue InputGlue, const SmallVectorImpl<SDNode*> &F, 307 bool isMorphNodeTo); 308 309 }; 310 311 } 312 313 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */ 314
