1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SelectionDAG::Legalize method. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Analysis/DebugInfo.h" 15 #include "llvm/CodeGen/Analysis.h" 16 #include "llvm/CodeGen/MachineFunction.h" 17 #include "llvm/CodeGen/MachineJumpTableInfo.h" 18 #include "llvm/CodeGen/SelectionDAG.h" 19 #include "llvm/Target/TargetFrameLowering.h" 20 #include "llvm/Target/TargetLowering.h" 21 #include "llvm/Target/TargetData.h" 22 #include "llvm/Target/TargetMachine.h" 23 #include "llvm/CallingConv.h" 24 #include "llvm/Constants.h" 25 #include "llvm/DerivedTypes.h" 26 #include "llvm/LLVMContext.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/MathExtras.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/ADT/DenseMap.h" 32 #include "llvm/ADT/SmallVector.h" 33 #include "llvm/ADT/SmallPtrSet.h" 34 using namespace llvm; 35 36 //===----------------------------------------------------------------------===// 37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 38 /// hacks on it until the target machine can handle it. This involves 39 /// eliminating value sizes the machine cannot handle (promoting small sizes to 40 /// large sizes or splitting up large values into small values) as well as 41 /// eliminating operations the machine cannot handle. 42 /// 43 /// This code also does a small amount of optimization and recognition of idioms 44 /// as part of its processing. For example, if a target does not support a 45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 46 /// will attempt merge setcc and brc instructions into brcc's. 47 /// 48 namespace { 49 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener { 50 const TargetMachine &TM; 51 const TargetLowering &TLI; 52 SelectionDAG &DAG; 53 54 /// LegalizePosition - The iterator for walking through the node list. 55 SelectionDAG::allnodes_iterator LegalizePosition; 56 57 /// LegalizedNodes - The set of nodes which have already been legalized. 58 SmallPtrSet<SDNode *, 16> LegalizedNodes; 59 60 // Libcall insertion helpers. 61 62 public: 63 explicit SelectionDAGLegalize(SelectionDAG &DAG); 64 65 void LegalizeDAG(); 66 67 private: 68 /// LegalizeOp - Legalizes the given operation. 69 void LegalizeOp(SDNode *Node); 70 71 SDValue OptimizeFloatStore(StoreSDNode *ST); 72 73 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 74 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 75 /// is necessary to spill the vector being inserted into to memory, perform 76 /// the insert there, and then read the result back. 77 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 78 SDValue Idx, DebugLoc dl); 79 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 80 SDValue Idx, DebugLoc dl); 81 82 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 83 /// performs the same shuffe in terms of order or result bytes, but on a type 84 /// whose vector element type is narrower than the original shuffle type. 85 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 86 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 87 SDValue N1, SDValue N2, 88 ArrayRef<int> Mask) const; 89 90 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 91 DebugLoc dl); 92 93 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 94 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, 95 unsigned NumOps, bool isSigned, DebugLoc dl); 96 97 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC, 98 SDNode *Node, bool isSigned); 99 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 100 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 101 RTLIB::Libcall Call_PPCF128); 102 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 103 RTLIB::Libcall Call_I8, 104 RTLIB::Libcall Call_I16, 105 RTLIB::Libcall Call_I32, 106 RTLIB::Libcall Call_I64, 107 RTLIB::Libcall Call_I128); 108 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results); 109 110 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 111 SDValue ExpandBUILD_VECTOR(SDNode *Node); 112 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 113 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 114 SmallVectorImpl<SDValue> &Results); 115 SDValue ExpandFCOPYSIGN(SDNode *Node); 116 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 117 DebugLoc dl); 118 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 119 DebugLoc dl); 120 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 121 DebugLoc dl); 122 123 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 124 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 125 126 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 127 SDValue ExpandInsertToVectorThroughStack(SDValue Op); 128 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 129 130 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP); 131 132 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node); 133 134 void ExpandNode(SDNode *Node); 135 void PromoteNode(SDNode *Node); 136 137 void ForgetNode(SDNode *N) { 138 LegalizedNodes.erase(N); 139 if (LegalizePosition == SelectionDAG::allnodes_iterator(N)) 140 ++LegalizePosition; 141 } 142 143 public: 144 // DAGUpdateListener implementation. 145 virtual void NodeDeleted(SDNode *N, SDNode *E) { 146 ForgetNode(N); 147 } 148 virtual void NodeUpdated(SDNode *N) {} 149 150 // Node replacement helpers 151 void ReplacedNode(SDNode *N) { 152 if (N->use_empty()) { 153 DAG.RemoveDeadNode(N, this); 154 } else { 155 ForgetNode(N); 156 } 157 } 158 void ReplaceNode(SDNode *Old, SDNode *New) { 159 DAG.ReplaceAllUsesWith(Old, New, this); 160 ReplacedNode(Old); 161 } 162 void ReplaceNode(SDValue Old, SDValue New) { 163 DAG.ReplaceAllUsesWith(Old, New, this); 164 ReplacedNode(Old.getNode()); 165 } 166 void ReplaceNode(SDNode *Old, const SDValue *New) { 167 DAG.ReplaceAllUsesWith(Old, New, this); 168 ReplacedNode(Old); 169 } 170 }; 171 } 172 173 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 174 /// performs the same shuffe in terms of order or result bytes, but on a type 175 /// whose vector element type is narrower than the original shuffle type. 176 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 177 SDValue 178 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 179 SDValue N1, SDValue N2, 180 ArrayRef<int> Mask) const { 181 unsigned NumMaskElts = VT.getVectorNumElements(); 182 unsigned NumDestElts = NVT.getVectorNumElements(); 183 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 184 185 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 186 187 if (NumEltsGrowth == 1) 188 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 189 190 SmallVector<int, 8> NewMask; 191 for (unsigned i = 0; i != NumMaskElts; ++i) { 192 int Idx = Mask[i]; 193 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 194 if (Idx < 0) 195 NewMask.push_back(-1); 196 else 197 NewMask.push_back(Idx * NumEltsGrowth + j); 198 } 199 } 200 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 201 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 202 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 203 } 204 205 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 206 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 207 DAG(dag) { 208 } 209 210 void SelectionDAGLegalize::LegalizeDAG() { 211 DAG.AssignTopologicalOrder(); 212 213 // Visit all the nodes. We start in topological order, so that we see 214 // nodes with their original operands intact. Legalization can produce 215 // new nodes which may themselves need to be legalized. Iterate until all 216 // nodes have been legalized. 217 for (;;) { 218 bool AnyLegalized = false; 219 for (LegalizePosition = DAG.allnodes_end(); 220 LegalizePosition != DAG.allnodes_begin(); ) { 221 --LegalizePosition; 222 223 SDNode *N = LegalizePosition; 224 if (LegalizedNodes.insert(N)) { 225 AnyLegalized = true; 226 LegalizeOp(N); 227 } 228 } 229 if (!AnyLegalized) 230 break; 231 232 } 233 234 // Remove dead nodes now. 235 DAG.RemoveDeadNodes(); 236 } 237 238 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 239 /// a load from the constant pool. 240 SDValue 241 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) { 242 bool Extend = false; 243 DebugLoc dl = CFP->getDebugLoc(); 244 245 // If a FP immediate is precise when represented as a float and if the 246 // target can do an extending load from float to double, we put it into 247 // the constant pool as a float, even if it's is statically typed as a 248 // double. This shrinks FP constants and canonicalizes them for targets where 249 // an FP extending load is the same cost as a normal load (such as on the x87 250 // fp stack or PPC FP unit). 251 EVT VT = CFP->getValueType(0); 252 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 253 if (!UseCP) { 254 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 255 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 256 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 257 } 258 259 EVT OrigVT = VT; 260 EVT SVT = VT; 261 while (SVT != MVT::f32) { 262 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 263 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) && 264 // Only do this if the target has a native EXTLOAD instruction from 265 // smaller type. 266 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 267 TLI.ShouldShrinkFPConstant(OrigVT)) { 268 Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 269 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 270 VT = SVT; 271 Extend = true; 272 } 273 } 274 275 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 276 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 277 if (Extend) { 278 SDValue Result = 279 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, 280 DAG.getEntryNode(), 281 CPIdx, MachinePointerInfo::getConstantPool(), 282 VT, false, false, Alignment); 283 return Result; 284 } 285 SDValue Result = 286 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 287 MachinePointerInfo::getConstantPool(), false, false, false, 288 Alignment); 289 return Result; 290 } 291 292 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 293 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 294 const TargetLowering &TLI, 295 SelectionDAGLegalize *DAGLegalize) { 296 assert(ST->getAddressingMode() == ISD::UNINDEXED && 297 "unaligned indexed stores not implemented!"); 298 SDValue Chain = ST->getChain(); 299 SDValue Ptr = ST->getBasePtr(); 300 SDValue Val = ST->getValue(); 301 EVT VT = Val.getValueType(); 302 int Alignment = ST->getAlignment(); 303 DebugLoc dl = ST->getDebugLoc(); 304 if (ST->getMemoryVT().isFloatingPoint() || 305 ST->getMemoryVT().isVector()) { 306 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 307 if (TLI.isTypeLegal(intVT)) { 308 // Expand to a bitconvert of the value to the integer type of the 309 // same size, then a (misaligned) int store. 310 // FIXME: Does not handle truncating floating point stores! 311 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); 312 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), 313 ST->isVolatile(), ST->isNonTemporal(), Alignment); 314 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result); 315 return; 316 } 317 // Do a (aligned) store to a stack slot, then copy from the stack slot 318 // to the final destination using (unaligned) integer loads and stores. 319 EVT StoredVT = ST->getMemoryVT(); 320 EVT RegVT = 321 TLI.getRegisterType(*DAG.getContext(), 322 EVT::getIntegerVT(*DAG.getContext(), 323 StoredVT.getSizeInBits())); 324 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 325 unsigned RegBytes = RegVT.getSizeInBits() / 8; 326 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 327 328 // Make sure the stack slot is also aligned for the register type. 329 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 330 331 // Perform the original store, only redirected to the stack slot. 332 SDValue Store = DAG.getTruncStore(Chain, dl, 333 Val, StackPtr, MachinePointerInfo(), 334 StoredVT, false, false, 0); 335 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 336 SmallVector<SDValue, 8> Stores; 337 unsigned Offset = 0; 338 339 // Do all but one copies using the full register width. 340 for (unsigned i = 1; i < NumRegs; i++) { 341 // Load one integer register's worth from the stack slot. 342 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, 343 MachinePointerInfo(), 344 false, false, false, 0); 345 // Store it to the final location. Remember the store. 346 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 347 ST->getPointerInfo().getWithOffset(Offset), 348 ST->isVolatile(), ST->isNonTemporal(), 349 MinAlign(ST->getAlignment(), Offset))); 350 // Increment the pointers. 351 Offset += RegBytes; 352 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 353 Increment); 354 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 355 } 356 357 // The last store may be partial. Do a truncating store. On big-endian 358 // machines this requires an extending load from the stack slot to ensure 359 // that the bits are in the right place. 360 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 361 8 * (StoredBytes - Offset)); 362 363 // Load from the stack slot. 364 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 365 MachinePointerInfo(), 366 MemVT, false, false, 0); 367 368 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 369 ST->getPointerInfo() 370 .getWithOffset(Offset), 371 MemVT, ST->isVolatile(), 372 ST->isNonTemporal(), 373 MinAlign(ST->getAlignment(), Offset))); 374 // The order of the stores doesn't matter - say it with a TokenFactor. 375 SDValue Result = 376 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 377 Stores.size()); 378 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result); 379 return; 380 } 381 assert(ST->getMemoryVT().isInteger() && 382 !ST->getMemoryVT().isVector() && 383 "Unaligned store of unknown type."); 384 // Get the half-size VT 385 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 386 int NumBits = NewStoredVT.getSizeInBits(); 387 int IncrementSize = NumBits / 8; 388 389 // Divide the stored value in two parts. 390 SDValue ShiftAmount = DAG.getConstant(NumBits, 391 TLI.getShiftAmountTy(Val.getValueType())); 392 SDValue Lo = Val; 393 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 394 395 // Store the two parts 396 SDValue Store1, Store2; 397 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 398 ST->getPointerInfo(), NewStoredVT, 399 ST->isVolatile(), ST->isNonTemporal(), Alignment); 400 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 401 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 402 Alignment = MinAlign(Alignment, IncrementSize); 403 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 404 ST->getPointerInfo().getWithOffset(IncrementSize), 405 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 406 Alignment); 407 408 SDValue Result = 409 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 410 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result); 411 } 412 413 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 414 static void 415 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 416 const TargetLowering &TLI, 417 SDValue &ValResult, SDValue &ChainResult) { 418 assert(LD->getAddressingMode() == ISD::UNINDEXED && 419 "unaligned indexed loads not implemented!"); 420 SDValue Chain = LD->getChain(); 421 SDValue Ptr = LD->getBasePtr(); 422 EVT VT = LD->getValueType(0); 423 EVT LoadedVT = LD->getMemoryVT(); 424 DebugLoc dl = LD->getDebugLoc(); 425 if (VT.isFloatingPoint() || VT.isVector()) { 426 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 427 if (TLI.isTypeLegal(intVT)) { 428 // Expand to a (misaligned) integer load of the same size, 429 // then bitconvert to floating point or vector. 430 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(), 431 LD->isVolatile(), 432 LD->isNonTemporal(), 433 LD->isInvariant(), LD->getAlignment()); 434 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); 435 if (VT.isFloatingPoint() && LoadedVT != VT) 436 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 437 438 ValResult = Result; 439 ChainResult = Chain; 440 return; 441 } 442 443 // Copy the value to a (aligned) stack slot using (unaligned) integer 444 // loads and stores, then do a (aligned) load from the stack slot. 445 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 446 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 447 unsigned RegBytes = RegVT.getSizeInBits() / 8; 448 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 449 450 // Make sure the stack slot is also aligned for the register type. 451 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 452 453 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 454 SmallVector<SDValue, 8> Stores; 455 SDValue StackPtr = StackBase; 456 unsigned Offset = 0; 457 458 // Do all but one copies using the full register width. 459 for (unsigned i = 1; i < NumRegs; i++) { 460 // Load one integer register's worth from the original location. 461 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, 462 LD->getPointerInfo().getWithOffset(Offset), 463 LD->isVolatile(), LD->isNonTemporal(), 464 LD->isInvariant(), 465 MinAlign(LD->getAlignment(), Offset)); 466 // Follow the load with a store to the stack slot. Remember the store. 467 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 468 MachinePointerInfo(), false, false, 0)); 469 // Increment the pointers. 470 Offset += RegBytes; 471 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 472 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 473 Increment); 474 } 475 476 // The last copy may be partial. Do an extending load. 477 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 478 8 * (LoadedBytes - Offset)); 479 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 480 LD->getPointerInfo().getWithOffset(Offset), 481 MemVT, LD->isVolatile(), 482 LD->isNonTemporal(), 483 MinAlign(LD->getAlignment(), Offset)); 484 // Follow the load with a store to the stack slot. Remember the store. 485 // On big-endian machines this requires a truncating store to ensure 486 // that the bits end up in the right place. 487 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 488 MachinePointerInfo(), MemVT, 489 false, false, 0)); 490 491 // The order of the stores doesn't matter - say it with a TokenFactor. 492 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 493 Stores.size()); 494 495 // Finally, perform the original load only redirected to the stack slot. 496 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 497 MachinePointerInfo(), LoadedVT, false, false, 0); 498 499 // Callers expect a MERGE_VALUES node. 500 ValResult = Load; 501 ChainResult = TF; 502 return; 503 } 504 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 505 "Unaligned load of unsupported type."); 506 507 // Compute the new VT that is half the size of the old one. This is an 508 // integer MVT. 509 unsigned NumBits = LoadedVT.getSizeInBits(); 510 EVT NewLoadedVT; 511 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 512 NumBits >>= 1; 513 514 unsigned Alignment = LD->getAlignment(); 515 unsigned IncrementSize = NumBits / 8; 516 ISD::LoadExtType HiExtType = LD->getExtensionType(); 517 518 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 519 if (HiExtType == ISD::NON_EXTLOAD) 520 HiExtType = ISD::ZEXTLOAD; 521 522 // Load the value in two parts 523 SDValue Lo, Hi; 524 if (TLI.isLittleEndian()) { 525 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), 526 NewLoadedVT, LD->isVolatile(), 527 LD->isNonTemporal(), Alignment); 528 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 529 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 530 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, 531 LD->getPointerInfo().getWithOffset(IncrementSize), 532 NewLoadedVT, LD->isVolatile(), 533 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 534 } else { 535 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(), 536 NewLoadedVT, LD->isVolatile(), 537 LD->isNonTemporal(), Alignment); 538 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 539 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 540 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, 541 LD->getPointerInfo().getWithOffset(IncrementSize), 542 NewLoadedVT, LD->isVolatile(), 543 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 544 } 545 546 // aggregate the two parts 547 SDValue ShiftAmount = DAG.getConstant(NumBits, 548 TLI.getShiftAmountTy(Hi.getValueType())); 549 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 550 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 551 552 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 553 Hi.getValue(1)); 554 555 ValResult = Result; 556 ChainResult = TF; 557 } 558 559 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 560 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 561 /// is necessary to spill the vector being inserted into to memory, perform 562 /// the insert there, and then read the result back. 563 SDValue SelectionDAGLegalize:: 564 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 565 DebugLoc dl) { 566 SDValue Tmp1 = Vec; 567 SDValue Tmp2 = Val; 568 SDValue Tmp3 = Idx; 569 570 // If the target doesn't support this, we have to spill the input vector 571 // to a temporary stack slot, update the element, then reload it. This is 572 // badness. We could also load the value into a vector register (either 573 // with a "move to register" or "extload into register" instruction, then 574 // permute it into place, if the idx is a constant and if the idx is 575 // supported by the target. 576 EVT VT = Tmp1.getValueType(); 577 EVT EltVT = VT.getVectorElementType(); 578 EVT IdxVT = Tmp3.getValueType(); 579 EVT PtrVT = TLI.getPointerTy(); 580 SDValue StackPtr = DAG.CreateStackTemporary(VT); 581 582 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 583 584 // Store the vector. 585 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 586 MachinePointerInfo::getFixedStack(SPFI), 587 false, false, 0); 588 589 // Truncate or zero extend offset to target pointer type. 590 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 591 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 592 // Add the offset to the index. 593 unsigned EltSize = EltVT.getSizeInBits()/8; 594 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 595 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 596 // Store the scalar value. 597 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT, 598 false, false, 0); 599 // Load the updated vector. 600 return DAG.getLoad(VT, dl, Ch, StackPtr, 601 MachinePointerInfo::getFixedStack(SPFI), false, false, 602 false, 0); 603 } 604 605 606 SDValue SelectionDAGLegalize:: 607 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 608 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 609 // SCALAR_TO_VECTOR requires that the type of the value being inserted 610 // match the element type of the vector being created, except for 611 // integers in which case the inserted value can be over width. 612 EVT EltVT = Vec.getValueType().getVectorElementType(); 613 if (Val.getValueType() == EltVT || 614 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 615 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 616 Vec.getValueType(), Val); 617 618 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 619 // We generate a shuffle of InVec and ScVec, so the shuffle mask 620 // should be 0,1,2,3,4,5... with the appropriate element replaced with 621 // elt 0 of the RHS. 622 SmallVector<int, 8> ShufOps; 623 for (unsigned i = 0; i != NumElts; ++i) 624 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 625 626 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 627 &ShufOps[0]); 628 } 629 } 630 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 631 } 632 633 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 634 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 635 // FIXME: We shouldn't do this for TargetConstantFP's. 636 // FIXME: move this to the DAG Combiner! Note that we can't regress due 637 // to phase ordering between legalized code and the dag combiner. This 638 // probably means that we need to integrate dag combiner and legalizer 639 // together. 640 // We generally can't do this one for long doubles. 641 SDValue Tmp1 = ST->getChain(); 642 SDValue Tmp2 = ST->getBasePtr(); 643 SDValue Tmp3; 644 unsigned Alignment = ST->getAlignment(); 645 bool isVolatile = ST->isVolatile(); 646 bool isNonTemporal = ST->isNonTemporal(); 647 DebugLoc dl = ST->getDebugLoc(); 648 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 649 if (CFP->getValueType(0) == MVT::f32 && 650 TLI.isTypeLegal(MVT::i32)) { 651 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 652 bitcastToAPInt().zextOrTrunc(32), 653 MVT::i32); 654 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 655 isVolatile, isNonTemporal, Alignment); 656 } 657 658 if (CFP->getValueType(0) == MVT::f64) { 659 // If this target supports 64-bit registers, do a single 64-bit store. 660 if (TLI.isTypeLegal(MVT::i64)) { 661 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 662 zextOrTrunc(64), MVT::i64); 663 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 664 isVolatile, isNonTemporal, Alignment); 665 } 666 667 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) { 668 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 669 // stores. If the target supports neither 32- nor 64-bits, this 670 // xform is certainly not worth it. 671 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 672 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32); 673 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 674 if (TLI.isBigEndian()) std::swap(Lo, Hi); 675 676 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile, 677 isNonTemporal, Alignment); 678 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 679 DAG.getIntPtrConstant(4)); 680 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, 681 ST->getPointerInfo().getWithOffset(4), 682 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 683 684 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 685 } 686 } 687 } 688 return SDValue(0, 0); 689 } 690 691 /// LegalizeOp - Return a legal replacement for the given operation, with 692 /// all legal operands. 693 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { 694 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 695 return; 696 697 DebugLoc dl = Node->getDebugLoc(); 698 699 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 700 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) == 701 TargetLowering::TypeLegal && 702 "Unexpected illegal type!"); 703 704 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 705 assert((TLI.getTypeAction(*DAG.getContext(), 706 Node->getOperand(i).getValueType()) == 707 TargetLowering::TypeLegal || 708 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 709 "Unexpected illegal type!"); 710 711 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 712 bool isCustom = false; 713 714 // Figure out the correct action; the way to query this varies by opcode 715 TargetLowering::LegalizeAction Action = TargetLowering::Legal; 716 bool SimpleFinishLegalizing = true; 717 switch (Node->getOpcode()) { 718 case ISD::INTRINSIC_W_CHAIN: 719 case ISD::INTRINSIC_WO_CHAIN: 720 case ISD::INTRINSIC_VOID: 721 case ISD::STACKSAVE: 722 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 723 break; 724 case ISD::VAARG: 725 Action = TLI.getOperationAction(Node->getOpcode(), 726 Node->getValueType(0)); 727 if (Action != TargetLowering::Promote) 728 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 729 break; 730 case ISD::SINT_TO_FP: 731 case ISD::UINT_TO_FP: 732 case ISD::EXTRACT_VECTOR_ELT: 733 Action = TLI.getOperationAction(Node->getOpcode(), 734 Node->getOperand(0).getValueType()); 735 break; 736 case ISD::FP_ROUND_INREG: 737 case ISD::SIGN_EXTEND_INREG: { 738 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 739 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 740 break; 741 } 742 case ISD::ATOMIC_STORE: { 743 Action = TLI.getOperationAction(Node->getOpcode(), 744 Node->getOperand(2).getValueType()); 745 break; 746 } 747 case ISD::SELECT_CC: 748 case ISD::SETCC: 749 case ISD::BR_CC: { 750 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 751 Node->getOpcode() == ISD::SETCC ? 2 : 1; 752 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 753 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 754 ISD::CondCode CCCode = 755 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 756 Action = TLI.getCondCodeAction(CCCode, OpVT); 757 if (Action == TargetLowering::Legal) { 758 if (Node->getOpcode() == ISD::SELECT_CC) 759 Action = TLI.getOperationAction(Node->getOpcode(), 760 Node->getValueType(0)); 761 else 762 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 763 } 764 break; 765 } 766 case ISD::LOAD: 767 case ISD::STORE: 768 // FIXME: Model these properly. LOAD and STORE are complicated, and 769 // STORE expects the unlegalized operand in some cases. 770 SimpleFinishLegalizing = false; 771 break; 772 case ISD::CALLSEQ_START: 773 case ISD::CALLSEQ_END: 774 // FIXME: This shouldn't be necessary. These nodes have special properties 775 // dealing with the recursive nature of legalization. Removing this 776 // special case should be done as part of making LegalizeDAG non-recursive. 777 SimpleFinishLegalizing = false; 778 break; 779 case ISD::EXTRACT_ELEMENT: 780 case ISD::FLT_ROUNDS_: 781 case ISD::SADDO: 782 case ISD::SSUBO: 783 case ISD::UADDO: 784 case ISD::USUBO: 785 case ISD::SMULO: 786 case ISD::UMULO: 787 case ISD::FPOWI: 788 case ISD::MERGE_VALUES: 789 case ISD::EH_RETURN: 790 case ISD::FRAME_TO_ARGS_OFFSET: 791 case ISD::EH_SJLJ_SETJMP: 792 case ISD::EH_SJLJ_LONGJMP: 793 // These operations lie about being legal: when they claim to be legal, 794 // they should actually be expanded. 795 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 796 if (Action == TargetLowering::Legal) 797 Action = TargetLowering::Expand; 798 break; 799 case ISD::INIT_TRAMPOLINE: 800 case ISD::ADJUST_TRAMPOLINE: 801 case ISD::FRAMEADDR: 802 case ISD::RETURNADDR: 803 // These operations lie about being legal: when they claim to be legal, 804 // they should actually be custom-lowered. 805 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 806 if (Action == TargetLowering::Legal) 807 Action = TargetLowering::Custom; 808 break; 809 default: 810 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 811 Action = TargetLowering::Legal; 812 } else { 813 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 814 } 815 break; 816 } 817 818 if (SimpleFinishLegalizing) { 819 SmallVector<SDValue, 8> Ops; 820 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 821 Ops.push_back(Node->getOperand(i)); 822 switch (Node->getOpcode()) { 823 default: break; 824 case ISD::SHL: 825 case ISD::SRL: 826 case ISD::SRA: 827 case ISD::ROTL: 828 case ISD::ROTR: 829 // Legalizing shifts/rotates requires adjusting the shift amount 830 // to the appropriate width. 831 if (!Ops[1].getValueType().isVector()) { 832 SDValue SAO = DAG.getShiftAmountOperand(Ops[0].getValueType(), Ops[1]); 833 HandleSDNode Handle(SAO); 834 LegalizeOp(SAO.getNode()); 835 Ops[1] = Handle.getValue(); 836 } 837 break; 838 case ISD::SRL_PARTS: 839 case ISD::SRA_PARTS: 840 case ISD::SHL_PARTS: 841 // Legalizing shifts/rotates requires adjusting the shift amount 842 // to the appropriate width. 843 if (!Ops[2].getValueType().isVector()) { 844 SDValue SAO = DAG.getShiftAmountOperand(Ops[0].getValueType(), Ops[2]); 845 HandleSDNode Handle(SAO); 846 LegalizeOp(SAO.getNode()); 847 Ops[2] = Handle.getValue(); 848 } 849 break; 850 } 851 852 SDNode *NewNode = DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size()); 853 if (NewNode != Node) { 854 DAG.ReplaceAllUsesWith(Node, NewNode, this); 855 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 856 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i)); 857 ReplacedNode(Node); 858 Node = NewNode; 859 } 860 switch (Action) { 861 case TargetLowering::Legal: 862 return; 863 case TargetLowering::Custom: 864 // FIXME: The handling for custom lowering with multiple results is 865 // a complete mess. 866 Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG); 867 if (Tmp1.getNode()) { 868 SmallVector<SDValue, 8> ResultVals; 869 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 870 if (e == 1) 871 ResultVals.push_back(Tmp1); 872 else 873 ResultVals.push_back(Tmp1.getValue(i)); 874 } 875 if (Tmp1.getNode() != Node || Tmp1.getResNo() != 0) { 876 DAG.ReplaceAllUsesWith(Node, ResultVals.data(), this); 877 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 878 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]); 879 ReplacedNode(Node); 880 } 881 return; 882 } 883 884 // FALL THROUGH 885 case TargetLowering::Expand: 886 ExpandNode(Node); 887 return; 888 case TargetLowering::Promote: 889 PromoteNode(Node); 890 return; 891 } 892 } 893 894 switch (Node->getOpcode()) { 895 default: 896 #ifndef NDEBUG 897 dbgs() << "NODE: "; 898 Node->dump( &DAG); 899 dbgs() << "\n"; 900 #endif 901 llvm_unreachable("Do not know how to legalize this operator!"); 902 903 case ISD::CALLSEQ_START: 904 case ISD::CALLSEQ_END: 905 break; 906 case ISD::LOAD: { 907 LoadSDNode *LD = cast<LoadSDNode>(Node); 908 Tmp1 = LD->getChain(); // Legalize the chain. 909 Tmp2 = LD->getBasePtr(); // Legalize the base pointer. 910 911 ISD::LoadExtType ExtType = LD->getExtensionType(); 912 if (ExtType == ISD::NON_EXTLOAD) { 913 EVT VT = Node->getValueType(0); 914 Tmp3 = SDValue(Node, 0); 915 Tmp4 = SDValue(Node, 1); 916 917 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 918 default: llvm_unreachable("This action is not supported yet!"); 919 case TargetLowering::Legal: 920 // If this is an unaligned load and the target doesn't support it, 921 // expand it. 922 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 923 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 924 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 925 if (LD->getAlignment() < ABIAlignment){ 926 ExpandUnalignedLoad(cast<LoadSDNode>(Node), 927 DAG, TLI, Tmp3, Tmp4); 928 } 929 } 930 break; 931 case TargetLowering::Custom: 932 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 933 if (Tmp1.getNode()) { 934 Tmp3 = Tmp1; 935 Tmp4 = Tmp1.getValue(1); 936 } 937 break; 938 case TargetLowering::Promote: { 939 // Only promote a load of vector type to another. 940 assert(VT.isVector() && "Cannot promote this load!"); 941 // Change base type to a different vector type. 942 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 943 944 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(), 945 LD->isVolatile(), LD->isNonTemporal(), 946 LD->isInvariant(), LD->getAlignment()); 947 Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1); 948 Tmp4 = Tmp1.getValue(1); 949 break; 950 } 951 } 952 if (Tmp4.getNode() != Node) { 953 assert(Tmp3.getNode() != Node && "Load must be completely replaced"); 954 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp3); 955 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp4); 956 ReplacedNode(Node); 957 } 958 return; 959 } 960 961 EVT SrcVT = LD->getMemoryVT(); 962 unsigned SrcWidth = SrcVT.getSizeInBits(); 963 unsigned Alignment = LD->getAlignment(); 964 bool isVolatile = LD->isVolatile(); 965 bool isNonTemporal = LD->isNonTemporal(); 966 967 if (SrcWidth != SrcVT.getStoreSizeInBits() && 968 // Some targets pretend to have an i1 loading operation, and actually 969 // load an i8. This trick is correct for ZEXTLOAD because the top 7 970 // bits are guaranteed to be zero; it helps the optimizers understand 971 // that these bits are zero. It is also useful for EXTLOAD, since it 972 // tells the optimizers that those bits are undefined. It would be 973 // nice to have an effective generic way of getting these benefits... 974 // Until such a way is found, don't insist on promoting i1 here. 975 (SrcVT != MVT::i1 || 976 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 977 // Promote to a byte-sized load if not loading an integral number of 978 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 979 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 980 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 981 SDValue Ch; 982 983 // The extra bits are guaranteed to be zero, since we stored them that 984 // way. A zext load from NVT thus automatically gives zext from SrcVT. 985 986 ISD::LoadExtType NewExtType = 987 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 988 989 SDValue Result = 990 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 991 Tmp1, Tmp2, LD->getPointerInfo(), 992 NVT, isVolatile, isNonTemporal, Alignment); 993 994 Ch = Result.getValue(1); // The chain. 995 996 if (ExtType == ISD::SEXTLOAD) 997 // Having the top bits zero doesn't help when sign extending. 998 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 999 Result.getValueType(), 1000 Result, DAG.getValueType(SrcVT)); 1001 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1002 // All the top bits are guaranteed to be zero - inform the optimizers. 1003 Result = DAG.getNode(ISD::AssertZext, dl, 1004 Result.getValueType(), Result, 1005 DAG.getValueType(SrcVT)); 1006 1007 Tmp1 = Result; 1008 Tmp2 = Ch; 1009 } else if (SrcWidth & (SrcWidth - 1)) { 1010 // If not loading a power-of-2 number of bits, expand as two loads. 1011 assert(!SrcVT.isVector() && "Unsupported extload!"); 1012 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1013 assert(RoundWidth < SrcWidth); 1014 unsigned ExtraWidth = SrcWidth - RoundWidth; 1015 assert(ExtraWidth < RoundWidth); 1016 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1017 "Load size not an integral number of bytes!"); 1018 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1019 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1020 SDValue Lo, Hi, Ch; 1021 unsigned IncrementSize; 1022 1023 if (TLI.isLittleEndian()) { 1024 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1025 // Load the bottom RoundWidth bits. 1026 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), 1027 Tmp1, Tmp2, 1028 LD->getPointerInfo(), RoundVT, isVolatile, 1029 isNonTemporal, Alignment); 1030 1031 // Load the remaining ExtraWidth bits. 1032 IncrementSize = RoundWidth / 8; 1033 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1034 DAG.getIntPtrConstant(IncrementSize)); 1035 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1036 LD->getPointerInfo().getWithOffset(IncrementSize), 1037 ExtraVT, isVolatile, isNonTemporal, 1038 MinAlign(Alignment, IncrementSize)); 1039 1040 // Build a factor node to remember that this load is independent of 1041 // the other one. 1042 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1043 Hi.getValue(1)); 1044 1045 // Move the top bits to the right place. 1046 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1047 DAG.getConstant(RoundWidth, 1048 TLI.getShiftAmountTy(Hi.getValueType()))); 1049 1050 // Join the hi and lo parts. 1051 Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1052 } else { 1053 // Big endian - avoid unaligned loads. 1054 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1055 // Load the top RoundWidth bits. 1056 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1057 LD->getPointerInfo(), RoundVT, isVolatile, 1058 isNonTemporal, Alignment); 1059 1060 // Load the remaining ExtraWidth bits. 1061 IncrementSize = RoundWidth / 8; 1062 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1063 DAG.getIntPtrConstant(IncrementSize)); 1064 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, 1065 dl, Node->getValueType(0), Tmp1, Tmp2, 1066 LD->getPointerInfo().getWithOffset(IncrementSize), 1067 ExtraVT, isVolatile, isNonTemporal, 1068 MinAlign(Alignment, IncrementSize)); 1069 1070 // Build a factor node to remember that this load is independent of 1071 // the other one. 1072 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1073 Hi.getValue(1)); 1074 1075 // Move the top bits to the right place. 1076 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1077 DAG.getConstant(ExtraWidth, 1078 TLI.getShiftAmountTy(Hi.getValueType()))); 1079 1080 // Join the hi and lo parts. 1081 Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1082 } 1083 1084 Tmp2 = Ch; 1085 } else { 1086 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1087 default: llvm_unreachable("This action is not supported yet!"); 1088 case TargetLowering::Custom: 1089 isCustom = true; 1090 // FALLTHROUGH 1091 case TargetLowering::Legal: 1092 Tmp1 = SDValue(Node, 0); 1093 Tmp2 = SDValue(Node, 1); 1094 1095 if (isCustom) { 1096 Tmp3 = TLI.LowerOperation(SDValue(Node, 0), DAG); 1097 if (Tmp3.getNode()) { 1098 Tmp1 = Tmp3; 1099 Tmp2 = Tmp3.getValue(1); 1100 } 1101 } else { 1102 // If this is an unaligned load and the target doesn't support it, 1103 // expand it. 1104 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1105 Type *Ty = 1106 LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1107 unsigned ABIAlignment = 1108 TLI.getTargetData()->getABITypeAlignment(Ty); 1109 if (LD->getAlignment() < ABIAlignment){ 1110 ExpandUnalignedLoad(cast<LoadSDNode>(Node), 1111 DAG, TLI, Tmp1, Tmp2); 1112 } 1113 } 1114 } 1115 break; 1116 case TargetLowering::Expand: 1117 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) { 1118 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, 1119 LD->getPointerInfo(), 1120 LD->isVolatile(), LD->isNonTemporal(), 1121 LD->isInvariant(), LD->getAlignment()); 1122 unsigned ExtendOp; 1123 switch (ExtType) { 1124 case ISD::EXTLOAD: 1125 ExtendOp = (SrcVT.isFloatingPoint() ? 1126 ISD::FP_EXTEND : ISD::ANY_EXTEND); 1127 break; 1128 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break; 1129 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; 1130 default: llvm_unreachable("Unexpected extend load type!"); 1131 } 1132 Tmp1 = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load); 1133 Tmp2 = Load.getValue(1); 1134 break; 1135 } 1136 1137 assert(!SrcVT.isVector() && 1138 "Vector Loads are handled in LegalizeVectorOps"); 1139 1140 // FIXME: This does not work for vectors on most targets. Sign- and 1141 // zero-extend operations are currently folded into extending loads, 1142 // whether they are legal or not, and then we end up here without any 1143 // support for legalizing them. 1144 assert(ExtType != ISD::EXTLOAD && 1145 "EXTLOAD should always be supported!"); 1146 // Turn the unsupported load into an EXTLOAD followed by an explicit 1147 // zero/sign extend inreg. 1148 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1149 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT, 1150 LD->isVolatile(), LD->isNonTemporal(), 1151 LD->getAlignment()); 1152 SDValue ValRes; 1153 if (ExtType == ISD::SEXTLOAD) 1154 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1155 Result.getValueType(), 1156 Result, DAG.getValueType(SrcVT)); 1157 else 1158 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType()); 1159 Tmp1 = ValRes; 1160 Tmp2 = Result.getValue(1); 1161 break; 1162 } 1163 } 1164 1165 // Since loads produce two values, make sure to remember that we legalized 1166 // both of them. 1167 if (Tmp2.getNode() != Node) { 1168 assert(Tmp1.getNode() != Node && "Load must be completely replaced"); 1169 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp1); 1170 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp2); 1171 ReplacedNode(Node); 1172 } 1173 break; 1174 } 1175 case ISD::STORE: { 1176 StoreSDNode *ST = cast<StoreSDNode>(Node); 1177 Tmp1 = ST->getChain(); 1178 Tmp2 = ST->getBasePtr(); 1179 unsigned Alignment = ST->getAlignment(); 1180 bool isVolatile = ST->isVolatile(); 1181 bool isNonTemporal = ST->isNonTemporal(); 1182 1183 if (!ST->isTruncatingStore()) { 1184 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1185 ReplaceNode(ST, OptStore); 1186 break; 1187 } 1188 1189 { 1190 Tmp3 = ST->getValue(); 1191 EVT VT = Tmp3.getValueType(); 1192 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1193 default: llvm_unreachable("This action is not supported yet!"); 1194 case TargetLowering::Legal: 1195 // If this is an unaligned store and the target doesn't support it, 1196 // expand it. 1197 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1198 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1199 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1200 if (ST->getAlignment() < ABIAlignment) 1201 ExpandUnalignedStore(cast<StoreSDNode>(Node), 1202 DAG, TLI, this); 1203 } 1204 break; 1205 case TargetLowering::Custom: 1206 Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG); 1207 if (Tmp1.getNode()) 1208 ReplaceNode(SDValue(Node, 0), Tmp1); 1209 break; 1210 case TargetLowering::Promote: { 1211 assert(VT.isVector() && "Unknown legal promote case!"); 1212 Tmp3 = DAG.getNode(ISD::BITCAST, dl, 1213 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1214 SDValue Result = 1215 DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1216 ST->getPointerInfo(), isVolatile, 1217 isNonTemporal, Alignment); 1218 ReplaceNode(SDValue(Node, 0), Result); 1219 break; 1220 } 1221 } 1222 break; 1223 } 1224 } else { 1225 Tmp3 = ST->getValue(); 1226 1227 EVT StVT = ST->getMemoryVT(); 1228 unsigned StWidth = StVT.getSizeInBits(); 1229 1230 if (StWidth != StVT.getStoreSizeInBits()) { 1231 // Promote to a byte-sized store with upper bits zero if not 1232 // storing an integral number of bytes. For example, promote 1233 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1234 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), 1235 StVT.getStoreSizeInBits()); 1236 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1237 SDValue Result = 1238 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 1239 NVT, isVolatile, isNonTemporal, Alignment); 1240 ReplaceNode(SDValue(Node, 0), Result); 1241 } else if (StWidth & (StWidth - 1)) { 1242 // If not storing a power-of-2 number of bits, expand as two stores. 1243 assert(!StVT.isVector() && "Unsupported truncstore!"); 1244 unsigned RoundWidth = 1 << Log2_32(StWidth); 1245 assert(RoundWidth < StWidth); 1246 unsigned ExtraWidth = StWidth - RoundWidth; 1247 assert(ExtraWidth < RoundWidth); 1248 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1249 "Store size not an integral number of bytes!"); 1250 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1251 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1252 SDValue Lo, Hi; 1253 unsigned IncrementSize; 1254 1255 if (TLI.isLittleEndian()) { 1256 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1257 // Store the bottom RoundWidth bits. 1258 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 1259 RoundVT, 1260 isVolatile, isNonTemporal, Alignment); 1261 1262 // Store the remaining ExtraWidth bits. 1263 IncrementSize = RoundWidth / 8; 1264 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1265 DAG.getIntPtrConstant(IncrementSize)); 1266 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1267 DAG.getConstant(RoundWidth, 1268 TLI.getShiftAmountTy(Tmp3.getValueType()))); 1269 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, 1270 ST->getPointerInfo().getWithOffset(IncrementSize), 1271 ExtraVT, isVolatile, isNonTemporal, 1272 MinAlign(Alignment, IncrementSize)); 1273 } else { 1274 // Big endian - avoid unaligned stores. 1275 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1276 // Store the top RoundWidth bits. 1277 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1278 DAG.getConstant(ExtraWidth, 1279 TLI.getShiftAmountTy(Tmp3.getValueType()))); 1280 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(), 1281 RoundVT, isVolatile, isNonTemporal, Alignment); 1282 1283 // Store the remaining ExtraWidth bits. 1284 IncrementSize = RoundWidth / 8; 1285 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1286 DAG.getIntPtrConstant(IncrementSize)); 1287 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, 1288 ST->getPointerInfo().getWithOffset(IncrementSize), 1289 ExtraVT, isVolatile, isNonTemporal, 1290 MinAlign(Alignment, IncrementSize)); 1291 } 1292 1293 // The order of the stores doesn't matter. 1294 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1295 ReplaceNode(SDValue(Node, 0), Result); 1296 } else { 1297 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1298 default: llvm_unreachable("This action is not supported yet!"); 1299 case TargetLowering::Legal: 1300 // If this is an unaligned store and the target doesn't support it, 1301 // expand it. 1302 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1303 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1304 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1305 if (ST->getAlignment() < ABIAlignment) 1306 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this); 1307 } 1308 break; 1309 case TargetLowering::Custom: 1310 ReplaceNode(SDValue(Node, 0), 1311 TLI.LowerOperation(SDValue(Node, 0), DAG)); 1312 break; 1313 case TargetLowering::Expand: 1314 assert(!StVT.isVector() && 1315 "Vector Stores are handled in LegalizeVectorOps"); 1316 1317 // TRUNCSTORE:i16 i32 -> STORE i16 1318 assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!"); 1319 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1320 SDValue Result = 1321 DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 1322 isVolatile, isNonTemporal, Alignment); 1323 ReplaceNode(SDValue(Node, 0), Result); 1324 break; 1325 } 1326 } 1327 } 1328 break; 1329 } 1330 } 1331 } 1332 1333 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1334 SDValue Vec = Op.getOperand(0); 1335 SDValue Idx = Op.getOperand(1); 1336 DebugLoc dl = Op.getDebugLoc(); 1337 // Store the value to a temporary stack slot, then LOAD the returned part. 1338 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1339 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1340 MachinePointerInfo(), false, false, 0); 1341 1342 // Add the offset to the index. 1343 unsigned EltSize = 1344 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1345 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1346 DAG.getConstant(EltSize, Idx.getValueType())); 1347 1348 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1349 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1350 else 1351 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1352 1353 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1354 1355 if (Op.getValueType().isVector()) 1356 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(), 1357 false, false, false, 0); 1358 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1359 MachinePointerInfo(), 1360 Vec.getValueType().getVectorElementType(), 1361 false, false, 0); 1362 } 1363 1364 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) { 1365 assert(Op.getValueType().isVector() && "Non-vector insert subvector!"); 1366 1367 SDValue Vec = Op.getOperand(0); 1368 SDValue Part = Op.getOperand(1); 1369 SDValue Idx = Op.getOperand(2); 1370 DebugLoc dl = Op.getDebugLoc(); 1371 1372 // Store the value to a temporary stack slot, then LOAD the returned part. 1373 1374 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1375 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 1376 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1377 1378 // First store the whole vector. 1379 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo, 1380 false, false, 0); 1381 1382 // Then store the inserted part. 1383 1384 // Add the offset to the index. 1385 unsigned EltSize = 1386 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1387 1388 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1389 DAG.getConstant(EltSize, Idx.getValueType())); 1390 1391 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1392 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1393 else 1394 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1395 1396 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, 1397 StackPtr); 1398 1399 // Store the subvector. 1400 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr, 1401 MachinePointerInfo(), false, false, 0); 1402 1403 // Finally, load the updated vector. 1404 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo, 1405 false, false, false, 0); 1406 } 1407 1408 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1409 // We can't handle this case efficiently. Allocate a sufficiently 1410 // aligned object on the stack, store each element into it, then load 1411 // the result as a vector. 1412 // Create the stack frame object. 1413 EVT VT = Node->getValueType(0); 1414 EVT EltVT = VT.getVectorElementType(); 1415 DebugLoc dl = Node->getDebugLoc(); 1416 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1417 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1418 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1419 1420 // Emit a store of each element to the stack slot. 1421 SmallVector<SDValue, 8> Stores; 1422 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1423 // Store (in the right endianness) the elements to memory. 1424 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1425 // Ignore undef elements. 1426 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1427 1428 unsigned Offset = TypeByteSize*i; 1429 1430 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1431 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1432 1433 // If the destination vector element type is narrower than the source 1434 // element type, only store the bits necessary. 1435 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1436 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1437 Node->getOperand(i), Idx, 1438 PtrInfo.getWithOffset(Offset), 1439 EltVT, false, false, 0)); 1440 } else 1441 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1442 Node->getOperand(i), Idx, 1443 PtrInfo.getWithOffset(Offset), 1444 false, false, 0)); 1445 } 1446 1447 SDValue StoreChain; 1448 if (!Stores.empty()) // Not all undef elements? 1449 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1450 &Stores[0], Stores.size()); 1451 else 1452 StoreChain = DAG.getEntryNode(); 1453 1454 // Result is a load from the stack slot. 1455 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, 1456 false, false, false, 0); 1457 } 1458 1459 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1460 DebugLoc dl = Node->getDebugLoc(); 1461 SDValue Tmp1 = Node->getOperand(0); 1462 SDValue Tmp2 = Node->getOperand(1); 1463 1464 // Get the sign bit of the RHS. First obtain a value that has the same 1465 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1466 SDValue SignBit; 1467 EVT FloatVT = Tmp2.getValueType(); 1468 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1469 if (TLI.isTypeLegal(IVT)) { 1470 // Convert to an integer with the same sign bit. 1471 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2); 1472 } else { 1473 // Store the float to memory, then load the sign part out as an integer. 1474 MVT LoadTy = TLI.getPointerTy(); 1475 // First create a temporary that is aligned for both the load and store. 1476 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1477 // Then store the float to it. 1478 SDValue Ch = 1479 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(), 1480 false, false, 0); 1481 if (TLI.isBigEndian()) { 1482 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1483 // Load out a legal integer with the same sign bit as the float. 1484 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(), 1485 false, false, false, 0); 1486 } else { // Little endian 1487 SDValue LoadPtr = StackPtr; 1488 // The float may be wider than the integer we are going to load. Advance 1489 // the pointer so that the loaded integer will contain the sign bit. 1490 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1491 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1492 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1493 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1494 // Load a legal integer containing the sign bit. 1495 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(), 1496 false, false, false, 0); 1497 // Move the sign bit to the top bit of the loaded integer. 1498 unsigned BitShift = LoadTy.getSizeInBits() - 1499 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1500 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1501 if (BitShift) 1502 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1503 DAG.getConstant(BitShift, 1504 TLI.getShiftAmountTy(SignBit.getValueType()))); 1505 } 1506 } 1507 // Now get the sign bit proper, by seeing whether the value is negative. 1508 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1509 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1510 ISD::SETLT); 1511 // Get the absolute value of the result. 1512 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1513 // Select between the nabs and abs value based on the sign bit of 1514 // the input. 1515 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1516 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1517 AbsVal); 1518 } 1519 1520 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1521 SmallVectorImpl<SDValue> &Results) { 1522 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1523 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1524 " not tell us which reg is the stack pointer!"); 1525 DebugLoc dl = Node->getDebugLoc(); 1526 EVT VT = Node->getValueType(0); 1527 SDValue Tmp1 = SDValue(Node, 0); 1528 SDValue Tmp2 = SDValue(Node, 1); 1529 SDValue Tmp3 = Node->getOperand(2); 1530 SDValue Chain = Tmp1.getOperand(0); 1531 1532 // Chain the dynamic stack allocation so that it doesn't modify the stack 1533 // pointer when other instructions are using the stack. 1534 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1535 1536 SDValue Size = Tmp2.getOperand(1); 1537 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1538 Chain = SP.getValue(1); 1539 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1540 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 1541 if (Align > StackAlign) 1542 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1543 DAG.getConstant(-(uint64_t)Align, VT)); 1544 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1545 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1546 1547 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1548 DAG.getIntPtrConstant(0, true), SDValue()); 1549 1550 Results.push_back(Tmp1); 1551 Results.push_back(Tmp2); 1552 } 1553 1554 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1555 /// condition code CC on the current target. This routine expands SETCC with 1556 /// illegal condition code into AND / OR of multiple SETCC values. 1557 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1558 SDValue &LHS, SDValue &RHS, 1559 SDValue &CC, 1560 DebugLoc dl) { 1561 EVT OpVT = LHS.getValueType(); 1562 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1563 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1564 default: llvm_unreachable("Unknown condition code action!"); 1565 case TargetLowering::Legal: 1566 // Nothing to do. 1567 break; 1568 case TargetLowering::Expand: { 1569 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1570 unsigned Opc = 0; 1571 switch (CCCode) { 1572 default: llvm_unreachable("Don't know how to expand this condition!"); 1573 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1574 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1575 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1576 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1577 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1578 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1579 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1580 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1581 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1582 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1583 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1584 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1585 // FIXME: Implement more expansions. 1586 } 1587 1588 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1589 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1590 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1591 RHS = SDValue(); 1592 CC = SDValue(); 1593 break; 1594 } 1595 } 1596 } 1597 1598 /// EmitStackConvert - Emit a store/load combination to the stack. This stores 1599 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1600 /// a load from the stack slot to DestVT, extending it if needed. 1601 /// The resultant code need not be legal. 1602 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1603 EVT SlotVT, 1604 EVT DestVT, 1605 DebugLoc dl) { 1606 // Create the stack frame object. 1607 unsigned SrcAlign = 1608 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1609 getTypeForEVT(*DAG.getContext())); 1610 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1611 1612 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1613 int SPFI = StackPtrFI->getIndex(); 1614 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI); 1615 1616 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1617 unsigned SlotSize = SlotVT.getSizeInBits(); 1618 unsigned DestSize = DestVT.getSizeInBits(); 1619 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); 1620 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType); 1621 1622 // Emit a store to the stack slot. Use a truncstore if the input value is 1623 // later than DestVT. 1624 SDValue Store; 1625 1626 if (SrcSize > SlotSize) 1627 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1628 PtrInfo, SlotVT, false, false, SrcAlign); 1629 else { 1630 assert(SrcSize == SlotSize && "Invalid store"); 1631 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1632 PtrInfo, false, false, SrcAlign); 1633 } 1634 1635 // Result is a load from the stack slot. 1636 if (SlotSize == DestSize) 1637 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, 1638 false, false, false, DestAlign); 1639 1640 assert(SlotSize < DestSize && "Unknown extension!"); 1641 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, 1642 PtrInfo, SlotVT, false, false, DestAlign); 1643 } 1644 1645 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1646 DebugLoc dl = Node->getDebugLoc(); 1647 // Create a vector sized/aligned stack slot, store the value to element #0, 1648 // then load the whole vector back out. 1649 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1650 1651 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1652 int SPFI = StackPtrFI->getIndex(); 1653 1654 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1655 StackPtr, 1656 MachinePointerInfo::getFixedStack(SPFI), 1657 Node->getValueType(0).getVectorElementType(), 1658 false, false, 0); 1659 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1660 MachinePointerInfo::getFixedStack(SPFI), 1661 false, false, false, 0); 1662 } 1663 1664 1665 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1666 /// support the operation, but do support the resultant vector type. 1667 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1668 unsigned NumElems = Node->getNumOperands(); 1669 SDValue Value1, Value2; 1670 DebugLoc dl = Node->getDebugLoc(); 1671 EVT VT = Node->getValueType(0); 1672 EVT OpVT = Node->getOperand(0).getValueType(); 1673 EVT EltVT = VT.getVectorElementType(); 1674 1675 // If the only non-undef value is the low element, turn this into a 1676 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1677 bool isOnlyLowElement = true; 1678 bool MoreThanTwoValues = false; 1679 bool isConstant = true; 1680 for (unsigned i = 0; i < NumElems; ++i) { 1681 SDValue V = Node->getOperand(i); 1682 if (V.getOpcode() == ISD::UNDEF) 1683 continue; 1684 if (i > 0) 1685 isOnlyLowElement = false; 1686 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1687 isConstant = false; 1688 1689 if (!Value1.getNode()) { 1690 Value1 = V; 1691 } else if (!Value2.getNode()) { 1692 if (V != Value1) 1693 Value2 = V; 1694 } else if (V != Value1 && V != Value2) { 1695 MoreThanTwoValues = true; 1696 } 1697 } 1698 1699 if (!Value1.getNode()) 1700 return DAG.getUNDEF(VT); 1701 1702 if (isOnlyLowElement) 1703 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1704 1705 // If all elements are constants, create a load from the constant pool. 1706 if (isConstant) { 1707 SmallVector<Constant*, 16> CV; 1708 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1709 if (ConstantFPSDNode *V = 1710 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1711 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1712 } else if (ConstantSDNode *V = 1713 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1714 if (OpVT==EltVT) 1715 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1716 else { 1717 // If OpVT and EltVT don't match, EltVT is not legal and the 1718 // element values have been promoted/truncated earlier. Undo this; 1719 // we don't want a v16i8 to become a v16i32 for example. 1720 const ConstantInt *CI = V->getConstantIntValue(); 1721 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1722 CI->getZExtValue())); 1723 } 1724 } else { 1725 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1726 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1727 CV.push_back(UndefValue::get(OpNTy)); 1728 } 1729 } 1730 Constant *CP = ConstantVector::get(CV); 1731 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1732 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1733 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1734 MachinePointerInfo::getConstantPool(), 1735 false, false, false, Alignment); 1736 } 1737 1738 if (!MoreThanTwoValues) { 1739 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1740 for (unsigned i = 0; i < NumElems; ++i) { 1741 SDValue V = Node->getOperand(i); 1742 if (V.getOpcode() == ISD::UNDEF) 1743 continue; 1744 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1745 } 1746 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1747 // Get the splatted value into the low element of a vector register. 1748 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1749 SDValue Vec2; 1750 if (Value2.getNode()) 1751 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1752 else 1753 Vec2 = DAG.getUNDEF(VT); 1754 1755 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1756 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1757 } 1758 } 1759 1760 // Otherwise, we can't handle this case efficiently. 1761 return ExpandVectorBuildThroughStack(Node); 1762 } 1763 1764 // ExpandLibCall - Expand a node into a call to a libcall. If the result value 1765 // does not fit into a register, return the lo part and set the hi part to the 1766 // by-reg argument. If it does fit into a single register, return the result 1767 // and leave the Hi part unset. 1768 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1769 bool isSigned) { 1770 TargetLowering::ArgListTy Args; 1771 TargetLowering::ArgListEntry Entry; 1772 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1773 EVT ArgVT = Node->getOperand(i).getValueType(); 1774 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1775 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1776 Entry.isSExt = isSigned; 1777 Entry.isZExt = !isSigned; 1778 Args.push_back(Entry); 1779 } 1780 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1781 TLI.getPointerTy()); 1782 1783 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1784 1785 // By default, the input chain to this libcall is the entry node of the 1786 // function. If the libcall is going to be emitted as a tail call then 1787 // TLI.isUsedByReturnOnly will change it to the right chain if the return 1788 // node which is being folded has a non-entry input chain. 1789 SDValue InChain = DAG.getEntryNode(); 1790 1791 // isTailCall may be true since the callee does not reference caller stack 1792 // frame. Check if it's in the right position. 1793 SDValue TCChain = InChain; 1794 bool isTailCall = isInTailCallPosition(DAG, Node, TCChain, TLI); 1795 if (isTailCall) 1796 InChain = TCChain; 1797 1798 std::pair<SDValue, SDValue> CallInfo = 1799 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1800 0, TLI.getLibcallCallingConv(LC), isTailCall, 1801 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 1802 Callee, Args, DAG, Node->getDebugLoc()); 1803 1804 if (!CallInfo.second.getNode()) 1805 // It's a tailcall, return the chain (which is the DAG root). 1806 return DAG.getRoot(); 1807 1808 return CallInfo.first; 1809 } 1810 1811 /// ExpandLibCall - Generate a libcall taking the given operands as arguments 1812 /// and returning a result of type RetVT. 1813 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, 1814 const SDValue *Ops, unsigned NumOps, 1815 bool isSigned, DebugLoc dl) { 1816 TargetLowering::ArgListTy Args; 1817 Args.reserve(NumOps); 1818 1819 TargetLowering::ArgListEntry Entry; 1820 for (unsigned i = 0; i != NumOps; ++i) { 1821 Entry.Node = Ops[i]; 1822 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); 1823 Entry.isSExt = isSigned; 1824 Entry.isZExt = !isSigned; 1825 Args.push_back(Entry); 1826 } 1827 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1828 TLI.getPointerTy()); 1829 1830 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 1831 std::pair<SDValue,SDValue> CallInfo = 1832 TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, 1833 false, 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 1834 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 1835 Callee, Args, DAG, dl); 1836 1837 return CallInfo.first; 1838 } 1839 1840 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to 1841 // ExpandLibCall except that the first operand is the in-chain. 1842 std::pair<SDValue, SDValue> 1843 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC, 1844 SDNode *Node, 1845 bool isSigned) { 1846 SDValue InChain = Node->getOperand(0); 1847 1848 TargetLowering::ArgListTy Args; 1849 TargetLowering::ArgListEntry Entry; 1850 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) { 1851 EVT ArgVT = Node->getOperand(i).getValueType(); 1852 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1853 Entry.Node = Node->getOperand(i); 1854 Entry.Ty = ArgTy; 1855 Entry.isSExt = isSigned; 1856 Entry.isZExt = !isSigned; 1857 Args.push_back(Entry); 1858 } 1859 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1860 TLI.getPointerTy()); 1861 1862 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1863 std::pair<SDValue, SDValue> CallInfo = 1864 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1865 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 1866 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 1867 Callee, Args, DAG, Node->getDebugLoc()); 1868 1869 return CallInfo; 1870 } 1871 1872 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1873 RTLIB::Libcall Call_F32, 1874 RTLIB::Libcall Call_F64, 1875 RTLIB::Libcall Call_F80, 1876 RTLIB::Libcall Call_PPCF128) { 1877 RTLIB::Libcall LC; 1878 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1879 default: llvm_unreachable("Unexpected request for libcall!"); 1880 case MVT::f32: LC = Call_F32; break; 1881 case MVT::f64: LC = Call_F64; break; 1882 case MVT::f80: LC = Call_F80; break; 1883 case MVT::ppcf128: LC = Call_PPCF128; break; 1884 } 1885 return ExpandLibCall(LC, Node, false); 1886 } 1887 1888 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 1889 RTLIB::Libcall Call_I8, 1890 RTLIB::Libcall Call_I16, 1891 RTLIB::Libcall Call_I32, 1892 RTLIB::Libcall Call_I64, 1893 RTLIB::Libcall Call_I128) { 1894 RTLIB::Libcall LC; 1895 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1896 default: llvm_unreachable("Unexpected request for libcall!"); 1897 case MVT::i8: LC = Call_I8; break; 1898 case MVT::i16: LC = Call_I16; break; 1899 case MVT::i32: LC = Call_I32; break; 1900 case MVT::i64: LC = Call_I64; break; 1901 case MVT::i128: LC = Call_I128; break; 1902 } 1903 return ExpandLibCall(LC, Node, isSigned); 1904 } 1905 1906 /// isDivRemLibcallAvailable - Return true if divmod libcall is available. 1907 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned, 1908 const TargetLowering &TLI) { 1909 RTLIB::Libcall LC; 1910 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1911 default: llvm_unreachable("Unexpected request for libcall!"); 1912 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; 1913 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; 1914 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; 1915 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 1916 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break; 1917 } 1918 1919 return TLI.getLibcallName(LC) != 0; 1920 } 1921 1922 /// UseDivRem - Only issue divrem libcall if both quotient and remainder are 1923 /// needed. 1924 static bool UseDivRem(SDNode *Node, bool isSigned, bool isDIV) { 1925 unsigned OtherOpcode = 0; 1926 if (isSigned) 1927 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV; 1928 else 1929 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV; 1930 1931 SDValue Op0 = Node->getOperand(0); 1932 SDValue Op1 = Node->getOperand(1); 1933 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(), 1934 UE = Op0.getNode()->use_end(); UI != UE; ++UI) { 1935 SDNode *User = *UI; 1936 if (User == Node) 1937 continue; 1938 if (User->getOpcode() == OtherOpcode && 1939 User->getOperand(0) == Op0 && 1940 User->getOperand(1) == Op1) 1941 return true; 1942 } 1943 return false; 1944 } 1945 1946 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem 1947 /// pairs. 1948 void 1949 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node, 1950 SmallVectorImpl<SDValue> &Results) { 1951 unsigned Opcode = Node->getOpcode(); 1952 bool isSigned = Opcode == ISD::SDIVREM; 1953 1954 RTLIB::Libcall LC; 1955 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1956 default: llvm_unreachable("Unexpected request for libcall!"); 1957 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; 1958 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; 1959 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; 1960 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 1961 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break; 1962 } 1963 1964 // The input chain to this libcall is the entry node of the function. 1965 // Legalizing the call will automatically add the previous call to the 1966 // dependence. 1967 SDValue InChain = DAG.getEntryNode(); 1968 1969 EVT RetVT = Node->getValueType(0); 1970 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 1971 1972 TargetLowering::ArgListTy Args; 1973 TargetLowering::ArgListEntry Entry; 1974 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1975 EVT ArgVT = Node->getOperand(i).getValueType(); 1976 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1977 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1978 Entry.isSExt = isSigned; 1979 Entry.isZExt = !isSigned; 1980 Args.push_back(Entry); 1981 } 1982 1983 // Also pass the return address of the remainder. 1984 SDValue FIPtr = DAG.CreateStackTemporary(RetVT); 1985 Entry.Node = FIPtr; 1986 Entry.Ty = RetTy->getPointerTo(); 1987 Entry.isSExt = isSigned; 1988 Entry.isZExt = !isSigned; 1989 Args.push_back(Entry); 1990 1991 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1992 TLI.getPointerTy()); 1993 1994 DebugLoc dl = Node->getDebugLoc(); 1995 std::pair<SDValue, SDValue> CallInfo = 1996 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1997 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 1998 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 1999 Callee, Args, DAG, dl); 2000 2001 // Remainder is loaded back from the stack frame. 2002 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, 2003 MachinePointerInfo(), false, false, false, 0); 2004 Results.push_back(CallInfo.first); 2005 Results.push_back(Rem); 2006 } 2007 2008 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 2009 /// INT_TO_FP operation of the specified operand when the target requests that 2010 /// we expand it. At this point, we know that the result and operand types are 2011 /// legal for the target. 2012 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 2013 SDValue Op0, 2014 EVT DestVT, 2015 DebugLoc dl) { 2016 if (Op0.getValueType() == MVT::i32) { 2017 // simple 32-bit [signed|unsigned] integer to float/double expansion 2018 2019 // Get the stack frame index of a 8 byte buffer. 2020 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 2021 2022 // word offset constant for Hi/Lo address computation 2023 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 2024 // set up Hi and Lo (into buffer) address based on endian 2025 SDValue Hi = StackSlot; 2026 SDValue Lo = DAG.getNode(ISD::ADD, dl, 2027 TLI.getPointerTy(), StackSlot, WordOff); 2028 if (TLI.isLittleEndian()) 2029 std::swap(Hi, Lo); 2030 2031 // if signed map to unsigned space 2032 SDValue Op0Mapped; 2033 if (isSigned) { 2034 // constant used to invert sign bit (signed to unsigned mapping) 2035 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 2036 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 2037 } else { 2038 Op0Mapped = Op0; 2039 } 2040 // store the lo of the constructed double - based on integer input 2041 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 2042 Op0Mapped, Lo, MachinePointerInfo(), 2043 false, false, 0); 2044 // initial hi portion of constructed double 2045 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2046 // store the hi of the constructed double - biased exponent 2047 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi, 2048 MachinePointerInfo(), 2049 false, false, 0); 2050 // load the constructed double 2051 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, 2052 MachinePointerInfo(), false, false, false, 0); 2053 // FP constant to bias correct the final result 2054 SDValue Bias = DAG.getConstantFP(isSigned ? 2055 BitsToDouble(0x4330000080000000ULL) : 2056 BitsToDouble(0x4330000000000000ULL), 2057 MVT::f64); 2058 // subtract the bias 2059 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2060 // final result 2061 SDValue Result; 2062 // handle final rounding 2063 if (DestVT == MVT::f64) { 2064 // do nothing 2065 Result = Sub; 2066 } else if (DestVT.bitsLT(MVT::f64)) { 2067 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2068 DAG.getIntPtrConstant(0)); 2069 } else if (DestVT.bitsGT(MVT::f64)) { 2070 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2071 } 2072 return Result; 2073 } 2074 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2075 // Code below here assumes !isSigned without checking again. 2076 2077 // Implementation of unsigned i64 to f64 following the algorithm in 2078 // __floatundidf in compiler_rt. This implementation has the advantage 2079 // of performing rounding correctly, both in the default rounding mode 2080 // and in all alternate rounding modes. 2081 // TODO: Generalize this for use with other types. 2082 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2083 SDValue TwoP52 = 2084 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2085 SDValue TwoP84PlusTwoP52 = 2086 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2087 SDValue TwoP84 = 2088 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2089 2090 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2091 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2092 DAG.getConstant(32, MVT::i64)); 2093 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2094 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2095 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr); 2096 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr); 2097 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, 2098 TwoP84PlusTwoP52); 2099 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2100 } 2101 2102 // Implementation of unsigned i64 to f32. 2103 // TODO: Generalize this for use with other types. 2104 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { 2105 // For unsigned conversions, convert them to signed conversions using the 2106 // algorithm from the x86_64 __floatundidf in compiler_rt. 2107 if (!isSigned) { 2108 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); 2109 2110 SDValue ShiftConst = 2111 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType())); 2112 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); 2113 SDValue AndConst = DAG.getConstant(1, MVT::i64); 2114 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst); 2115 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr); 2116 2117 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); 2118 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt); 2119 2120 // TODO: This really should be implemented using a branch rather than a 2121 // select. We happen to get lucky and machinesink does the right 2122 // thing most of the time. This would be a good candidate for a 2123 //pseudo-op, or, even better, for whole-function isel. 2124 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2125 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT); 2126 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast); 2127 } 2128 2129 // Otherwise, implement the fully general conversion. 2130 2131 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2132 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64)); 2133 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, 2134 DAG.getConstant(UINT64_C(0x800), MVT::i64)); 2135 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2136 DAG.getConstant(UINT64_C(0x7ff), MVT::i64)); 2137 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2138 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); 2139 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0); 2140 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2141 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64), 2142 ISD::SETUGE); 2143 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0); 2144 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType()); 2145 2146 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2147 DAG.getConstant(32, SHVT)); 2148 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); 2149 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); 2150 SDValue TwoP32 = 2151 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64); 2152 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); 2153 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); 2154 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); 2155 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); 2156 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, 2157 DAG.getIntPtrConstant(0)); 2158 } 2159 2160 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2161 2162 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2163 Op0, DAG.getConstant(0, Op0.getValueType()), 2164 ISD::SETLT); 2165 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2166 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2167 SignSet, Four, Zero); 2168 2169 // If the sign bit of the integer is set, the large number will be treated 2170 // as a negative number. To counteract this, the dynamic code adds an 2171 // offset depending on the data type. 2172 uint64_t FF; 2173 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2174 default: llvm_unreachable("Unsupported integer type!"); 2175 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2176 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2177 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2178 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2179 } 2180 if (TLI.isLittleEndian()) FF <<= 32; 2181 Constant *FudgeFactor = ConstantInt::get( 2182 Type::getInt64Ty(*DAG.getContext()), FF); 2183 2184 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2185 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2186 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2187 Alignment = std::min(Alignment, 4u); 2188 SDValue FudgeInReg; 2189 if (DestVT == MVT::f32) 2190 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2191 MachinePointerInfo::getConstantPool(), 2192 false, false, false, Alignment); 2193 else { 2194 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2195 DAG.getEntryNode(), CPIdx, 2196 MachinePointerInfo::getConstantPool(), 2197 MVT::f32, false, false, Alignment); 2198 HandleSDNode Handle(Load); 2199 LegalizeOp(Load.getNode()); 2200 FudgeInReg = Handle.getValue(); 2201 } 2202 2203 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2204 } 2205 2206 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2207 /// *INT_TO_FP operation of the specified operand when the target requests that 2208 /// we promote it. At this point, we know that the result and operand types are 2209 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2210 /// operation that takes a larger input. 2211 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2212 EVT DestVT, 2213 bool isSigned, 2214 DebugLoc dl) { 2215 // First step, figure out the appropriate *INT_TO_FP operation to use. 2216 EVT NewInTy = LegalOp.getValueType(); 2217 2218 unsigned OpToUse = 0; 2219 2220 // Scan for the appropriate larger type to use. 2221 while (1) { 2222 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2223 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2224 2225 // If the target supports SINT_TO_FP of this type, use it. 2226 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2227 OpToUse = ISD::SINT_TO_FP; 2228 break; 2229 } 2230 if (isSigned) continue; 2231 2232 // If the target supports UINT_TO_FP of this type, use it. 2233 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2234 OpToUse = ISD::UINT_TO_FP; 2235 break; 2236 } 2237 2238 // Otherwise, try a larger type. 2239 } 2240 2241 // Okay, we found the operation and type to use. Zero extend our input to the 2242 // desired type then run the operation on it. 2243 return DAG.getNode(OpToUse, dl, DestVT, 2244 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2245 dl, NewInTy, LegalOp)); 2246 } 2247 2248 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2249 /// FP_TO_*INT operation of the specified operand when the target requests that 2250 /// we promote it. At this point, we know that the result and operand types are 2251 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2252 /// operation that returns a larger result. 2253 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2254 EVT DestVT, 2255 bool isSigned, 2256 DebugLoc dl) { 2257 // First step, figure out the appropriate FP_TO*INT operation to use. 2258 EVT NewOutTy = DestVT; 2259 2260 unsigned OpToUse = 0; 2261 2262 // Scan for the appropriate larger type to use. 2263 while (1) { 2264 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2265 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2266 2267 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2268 OpToUse = ISD::FP_TO_SINT; 2269 break; 2270 } 2271 2272 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2273 OpToUse = ISD::FP_TO_UINT; 2274 break; 2275 } 2276 2277 // Otherwise, try a larger type. 2278 } 2279 2280 2281 // Okay, we found the operation and type to use. 2282 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2283 2284 // Truncate the result of the extended FP_TO_*INT operation to the desired 2285 // size. 2286 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2287 } 2288 2289 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2290 /// 2291 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2292 EVT VT = Op.getValueType(); 2293 EVT SHVT = TLI.getShiftAmountTy(VT); 2294 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2295 switch (VT.getSimpleVT().SimpleTy) { 2296 default: llvm_unreachable("Unhandled Expand type in BSWAP!"); 2297 case MVT::i16: 2298 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2299 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2300 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2301 case MVT::i32: 2302 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2303 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2304 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2305 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2306 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2307 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2308 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2309 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2310 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2311 case MVT::i64: 2312 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2313 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2314 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2315 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2316 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2317 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2318 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2319 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2320 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2321 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2322 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2323 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2324 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2325 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2326 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2327 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2328 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2329 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2330 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2331 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2332 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2333 } 2334 } 2335 2336 /// SplatByte - Distribute ByteVal over NumBits bits. 2337 // FIXME: Move this helper to a common place. 2338 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) { 2339 APInt Val = APInt(NumBits, ByteVal); 2340 unsigned Shift = 8; 2341 for (unsigned i = NumBits; i > 8; i >>= 1) { 2342 Val = (Val << Shift) | Val; 2343 Shift <<= 1; 2344 } 2345 return Val; 2346 } 2347 2348 /// ExpandBitCount - Expand the specified bitcount instruction into operations. 2349 /// 2350 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2351 DebugLoc dl) { 2352 switch (Opc) { 2353 default: llvm_unreachable("Cannot expand this yet!"); 2354 case ISD::CTPOP: { 2355 EVT VT = Op.getValueType(); 2356 EVT ShVT = TLI.getShiftAmountTy(VT); 2357 unsigned Len = VT.getSizeInBits(); 2358 2359 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 && 2360 "CTPOP not implemented for this type."); 2361 2362 // This is the "best" algorithm from 2363 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel 2364 2365 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT); 2366 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT); 2367 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT); 2368 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT); 2369 2370 // v = v - ((v >> 1) & 0x55555555...) 2371 Op = DAG.getNode(ISD::SUB, dl, VT, Op, 2372 DAG.getNode(ISD::AND, dl, VT, 2373 DAG.getNode(ISD::SRL, dl, VT, Op, 2374 DAG.getConstant(1, ShVT)), 2375 Mask55)); 2376 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...) 2377 Op = DAG.getNode(ISD::ADD, dl, VT, 2378 DAG.getNode(ISD::AND, dl, VT, Op, Mask33), 2379 DAG.getNode(ISD::AND, dl, VT, 2380 DAG.getNode(ISD::SRL, dl, VT, Op, 2381 DAG.getConstant(2, ShVT)), 2382 Mask33)); 2383 // v = (v + (v >> 4)) & 0x0F0F0F0F... 2384 Op = DAG.getNode(ISD::AND, dl, VT, 2385 DAG.getNode(ISD::ADD, dl, VT, Op, 2386 DAG.getNode(ISD::SRL, dl, VT, Op, 2387 DAG.getConstant(4, ShVT))), 2388 Mask0F); 2389 // v = (v * 0x01010101...) >> (Len - 8) 2390 Op = DAG.getNode(ISD::SRL, dl, VT, 2391 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01), 2392 DAG.getConstant(Len - 8, ShVT)); 2393 2394 return Op; 2395 } 2396 case ISD::CTLZ_ZERO_UNDEF: 2397 // This trivially expands to CTLZ. 2398 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op); 2399 case ISD::CTLZ: { 2400 // for now, we do this: 2401 // x = x | (x >> 1); 2402 // x = x | (x >> 2); 2403 // ... 2404 // x = x | (x >>16); 2405 // x = x | (x >>32); // for 64-bit input 2406 // return popcount(~x); 2407 // 2408 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2409 EVT VT = Op.getValueType(); 2410 EVT ShVT = TLI.getShiftAmountTy(VT); 2411 unsigned len = VT.getSizeInBits(); 2412 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2413 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2414 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2415 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2416 } 2417 Op = DAG.getNOT(dl, Op, VT); 2418 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2419 } 2420 case ISD::CTTZ_ZERO_UNDEF: 2421 // This trivially expands to CTTZ. 2422 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op); 2423 case ISD::CTTZ: { 2424 // for now, we use: { return popcount(~x & (x - 1)); } 2425 // unless the target has ctlz but not ctpop, in which case we use: 2426 // { return 32 - nlz(~x & (x-1)); } 2427 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2428 EVT VT = Op.getValueType(); 2429 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2430 DAG.getNOT(dl, Op, VT), 2431 DAG.getNode(ISD::SUB, dl, VT, Op, 2432 DAG.getConstant(1, VT))); 2433 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2434 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2435 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2436 return DAG.getNode(ISD::SUB, dl, VT, 2437 DAG.getConstant(VT.getSizeInBits(), VT), 2438 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2439 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2440 } 2441 } 2442 } 2443 2444 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) { 2445 unsigned Opc = Node->getOpcode(); 2446 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 2447 RTLIB::Libcall LC; 2448 2449 switch (Opc) { 2450 default: 2451 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 2452 case ISD::ATOMIC_SWAP: 2453 switch (VT.SimpleTy) { 2454 default: llvm_unreachable("Unexpected value type for atomic!"); 2455 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 2456 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 2457 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 2458 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 2459 } 2460 break; 2461 case ISD::ATOMIC_CMP_SWAP: 2462 switch (VT.SimpleTy) { 2463 default: llvm_unreachable("Unexpected value type for atomic!"); 2464 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 2465 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 2466 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 2467 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 2468 } 2469 break; 2470 case ISD::ATOMIC_LOAD_ADD: 2471 switch (VT.SimpleTy) { 2472 default: llvm_unreachable("Unexpected value type for atomic!"); 2473 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 2474 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 2475 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 2476 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 2477 } 2478 break; 2479 case ISD::ATOMIC_LOAD_SUB: 2480 switch (VT.SimpleTy) { 2481 default: llvm_unreachable("Unexpected value type for atomic!"); 2482 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 2483 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 2484 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 2485 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 2486 } 2487 break; 2488 case ISD::ATOMIC_LOAD_AND: 2489 switch (VT.SimpleTy) { 2490 default: llvm_unreachable("Unexpected value type for atomic!"); 2491 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 2492 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 2493 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 2494 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 2495 } 2496 break; 2497 case ISD::ATOMIC_LOAD_OR: 2498 switch (VT.SimpleTy) { 2499 default: llvm_unreachable("Unexpected value type for atomic!"); 2500 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 2501 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 2502 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 2503 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 2504 } 2505 break; 2506 case ISD::ATOMIC_LOAD_XOR: 2507 switch (VT.SimpleTy) { 2508 default: llvm_unreachable("Unexpected value type for atomic!"); 2509 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 2510 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 2511 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 2512 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 2513 } 2514 break; 2515 case ISD::ATOMIC_LOAD_NAND: 2516 switch (VT.SimpleTy) { 2517 default: llvm_unreachable("Unexpected value type for atomic!"); 2518 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 2519 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 2520 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 2521 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 2522 } 2523 break; 2524 } 2525 2526 return ExpandChainLibCall(LC, Node, false); 2527 } 2528 2529 void SelectionDAGLegalize::ExpandNode(SDNode *Node) { 2530 SmallVector<SDValue, 8> Results; 2531 DebugLoc dl = Node->getDebugLoc(); 2532 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2533 switch (Node->getOpcode()) { 2534 case ISD::CTPOP: 2535 case ISD::CTLZ: 2536 case ISD::CTLZ_ZERO_UNDEF: 2537 case ISD::CTTZ: 2538 case ISD::CTTZ_ZERO_UNDEF: 2539 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2540 Results.push_back(Tmp1); 2541 break; 2542 case ISD::BSWAP: 2543 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2544 break; 2545 case ISD::FRAMEADDR: 2546 case ISD::RETURNADDR: 2547 case ISD::FRAME_TO_ARGS_OFFSET: 2548 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2549 break; 2550 case ISD::FLT_ROUNDS_: 2551 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2552 break; 2553 case ISD::EH_RETURN: 2554 case ISD::EH_LABEL: 2555 case ISD::PREFETCH: 2556 case ISD::VAEND: 2557 case ISD::EH_SJLJ_LONGJMP: 2558 // If the target didn't expand these, there's nothing to do, so just 2559 // preserve the chain and be done. 2560 Results.push_back(Node->getOperand(0)); 2561 break; 2562 case ISD::EH_SJLJ_SETJMP: 2563 // If the target didn't expand this, just return 'zero' and preserve the 2564 // chain. 2565 Results.push_back(DAG.getConstant(0, MVT::i32)); 2566 Results.push_back(Node->getOperand(0)); 2567 break; 2568 case ISD::ATOMIC_FENCE: 2569 case ISD::MEMBARRIER: { 2570 // If the target didn't lower this, lower it to '__sync_synchronize()' call 2571 // FIXME: handle "fence singlethread" more efficiently. 2572 TargetLowering::ArgListTy Args; 2573 std::pair<SDValue, SDValue> CallResult = 2574 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2575 false, false, false, false, 0, CallingConv::C, 2576 /*isTailCall=*/false, 2577 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2578 DAG.getExternalSymbol("__sync_synchronize", 2579 TLI.getPointerTy()), 2580 Args, DAG, dl); 2581 Results.push_back(CallResult.second); 2582 break; 2583 } 2584 case ISD::ATOMIC_LOAD: { 2585 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP. 2586 SDValue Zero = DAG.getConstant(0, Node->getValueType(0)); 2587 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 2588 cast<AtomicSDNode>(Node)->getMemoryVT(), 2589 Node->getOperand(0), 2590 Node->getOperand(1), Zero, Zero, 2591 cast<AtomicSDNode>(Node)->getMemOperand(), 2592 cast<AtomicSDNode>(Node)->getOrdering(), 2593 cast<AtomicSDNode>(Node)->getSynchScope()); 2594 Results.push_back(Swap.getValue(0)); 2595 Results.push_back(Swap.getValue(1)); 2596 break; 2597 } 2598 case ISD::ATOMIC_STORE: { 2599 // There is no libcall for atomic store; fake it with ATOMIC_SWAP. 2600 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 2601 cast<AtomicSDNode>(Node)->getMemoryVT(), 2602 Node->getOperand(0), 2603 Node->getOperand(1), Node->getOperand(2), 2604 cast<AtomicSDNode>(Node)->getMemOperand(), 2605 cast<AtomicSDNode>(Node)->getOrdering(), 2606 cast<AtomicSDNode>(Node)->getSynchScope()); 2607 Results.push_back(Swap.getValue(1)); 2608 break; 2609 } 2610 // By default, atomic intrinsics are marked Legal and lowered. Targets 2611 // which don't support them directly, however, may want libcalls, in which 2612 // case they mark them Expand, and we get here. 2613 case ISD::ATOMIC_SWAP: 2614 case ISD::ATOMIC_LOAD_ADD: 2615 case ISD::ATOMIC_LOAD_SUB: 2616 case ISD::ATOMIC_LOAD_AND: 2617 case ISD::ATOMIC_LOAD_OR: 2618 case ISD::ATOMIC_LOAD_XOR: 2619 case ISD::ATOMIC_LOAD_NAND: 2620 case ISD::ATOMIC_LOAD_MIN: 2621 case ISD::ATOMIC_LOAD_MAX: 2622 case ISD::ATOMIC_LOAD_UMIN: 2623 case ISD::ATOMIC_LOAD_UMAX: 2624 case ISD::ATOMIC_CMP_SWAP: { 2625 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node); 2626 Results.push_back(Tmp.first); 2627 Results.push_back(Tmp.second); 2628 break; 2629 } 2630 case ISD::DYNAMIC_STACKALLOC: 2631 ExpandDYNAMIC_STACKALLOC(Node, Results); 2632 break; 2633 case ISD::MERGE_VALUES: 2634 for (unsigned i = 0; i < Node->getNumValues(); i++) 2635 Results.push_back(Node->getOperand(i)); 2636 break; 2637 case ISD::UNDEF: { 2638 EVT VT = Node->getValueType(0); 2639 if (VT.isInteger()) 2640 Results.push_back(DAG.getConstant(0, VT)); 2641 else { 2642 assert(VT.isFloatingPoint() && "Unknown value type!"); 2643 Results.push_back(DAG.getConstantFP(0, VT)); 2644 } 2645 break; 2646 } 2647 case ISD::TRAP: { 2648 // If this operation is not supported, lower it to 'abort()' call 2649 TargetLowering::ArgListTy Args; 2650 std::pair<SDValue, SDValue> CallResult = 2651 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2652 false, false, false, false, 0, CallingConv::C, 2653 /*isTailCall=*/false, 2654 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2655 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2656 Args, DAG, dl); 2657 Results.push_back(CallResult.second); 2658 break; 2659 } 2660 case ISD::FP_ROUND: 2661 case ISD::BITCAST: 2662 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2663 Node->getValueType(0), dl); 2664 Results.push_back(Tmp1); 2665 break; 2666 case ISD::FP_EXTEND: 2667 Tmp1 = EmitStackConvert(Node->getOperand(0), 2668 Node->getOperand(0).getValueType(), 2669 Node->getValueType(0), dl); 2670 Results.push_back(Tmp1); 2671 break; 2672 case ISD::SIGN_EXTEND_INREG: { 2673 // NOTE: we could fall back on load/store here too for targets without 2674 // SAR. However, it is doubtful that any exist. 2675 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2676 EVT VT = Node->getValueType(0); 2677 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT); 2678 if (VT.isVector()) 2679 ShiftAmountTy = VT; 2680 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2681 ExtraVT.getScalarType().getSizeInBits(); 2682 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2683 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2684 Node->getOperand(0), ShiftCst); 2685 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2686 Results.push_back(Tmp1); 2687 break; 2688 } 2689 case ISD::FP_ROUND_INREG: { 2690 // The only way we can lower this is to turn it into a TRUNCSTORE, 2691 // EXTLOAD pair, targeting a temporary location (a stack slot). 2692 2693 // NOTE: there is a choice here between constantly creating new stack 2694 // slots and always reusing the same one. We currently always create 2695 // new ones, as reuse may inhibit scheduling. 2696 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2697 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2698 Node->getValueType(0), dl); 2699 Results.push_back(Tmp1); 2700 break; 2701 } 2702 case ISD::SINT_TO_FP: 2703 case ISD::UINT_TO_FP: 2704 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2705 Node->getOperand(0), Node->getValueType(0), dl); 2706 Results.push_back(Tmp1); 2707 break; 2708 case ISD::FP_TO_UINT: { 2709 SDValue True, False; 2710 EVT VT = Node->getOperand(0).getValueType(); 2711 EVT NVT = Node->getValueType(0); 2712 APFloat apf(APInt::getNullValue(VT.getSizeInBits())); 2713 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2714 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2715 Tmp1 = DAG.getConstantFP(apf, VT); 2716 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2717 Node->getOperand(0), 2718 Tmp1, ISD::SETLT); 2719 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2720 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2721 DAG.getNode(ISD::FSUB, dl, VT, 2722 Node->getOperand(0), Tmp1)); 2723 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2724 DAG.getConstant(x, NVT)); 2725 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2726 Results.push_back(Tmp1); 2727 break; 2728 } 2729 case ISD::VAARG: { 2730 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2731 EVT VT = Node->getValueType(0); 2732 Tmp1 = Node->getOperand(0); 2733 Tmp2 = Node->getOperand(1); 2734 unsigned Align = Node->getConstantOperandVal(3); 2735 2736 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, 2737 MachinePointerInfo(V), 2738 false, false, false, 0); 2739 SDValue VAList = VAListLoad; 2740 2741 if (Align > TLI.getMinStackArgumentAlignment()) { 2742 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2743 2744 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2745 DAG.getConstant(Align - 1, 2746 TLI.getPointerTy())); 2747 2748 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList, 2749 DAG.getConstant(-(int64_t)Align, 2750 TLI.getPointerTy())); 2751 } 2752 2753 // Increment the pointer, VAList, to the next vaarg 2754 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2755 DAG.getConstant(TLI.getTargetData()-> 2756 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2757 TLI.getPointerTy())); 2758 // Store the incremented VAList to the legalized pointer 2759 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, 2760 MachinePointerInfo(V), false, false, 0); 2761 // Load the actual argument out of the pointer VAList 2762 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), 2763 false, false, false, 0)); 2764 Results.push_back(Results[0].getValue(1)); 2765 break; 2766 } 2767 case ISD::VACOPY: { 2768 // This defaults to loading a pointer from the input and storing it to the 2769 // output, returning the chain. 2770 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2771 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2772 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2773 Node->getOperand(2), MachinePointerInfo(VS), 2774 false, false, false, 0); 2775 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), 2776 MachinePointerInfo(VD), false, false, 0); 2777 Results.push_back(Tmp1); 2778 break; 2779 } 2780 case ISD::EXTRACT_VECTOR_ELT: 2781 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2782 // This must be an access of the only element. Return it. 2783 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), 2784 Node->getOperand(0)); 2785 else 2786 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2787 Results.push_back(Tmp1); 2788 break; 2789 case ISD::EXTRACT_SUBVECTOR: 2790 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2791 break; 2792 case ISD::INSERT_SUBVECTOR: 2793 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0))); 2794 break; 2795 case ISD::CONCAT_VECTORS: { 2796 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2797 break; 2798 } 2799 case ISD::SCALAR_TO_VECTOR: 2800 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2801 break; 2802 case ISD::INSERT_VECTOR_ELT: 2803 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2804 Node->getOperand(1), 2805 Node->getOperand(2), dl)); 2806 break; 2807 case ISD::VECTOR_SHUFFLE: { 2808 SmallVector<int, 32> NewMask; 2809 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask(); 2810 2811 EVT VT = Node->getValueType(0); 2812 EVT EltVT = VT.getVectorElementType(); 2813 SDValue Op0 = Node->getOperand(0); 2814 SDValue Op1 = Node->getOperand(1); 2815 if (!TLI.isTypeLegal(EltVT)) { 2816 2817 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); 2818 2819 // BUILD_VECTOR operands are allowed to be wider than the element type. 2820 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it 2821 if (NewEltVT.bitsLT(EltVT)) { 2822 2823 // Convert shuffle node. 2824 // If original node was v4i64 and the new EltVT is i32, 2825 // cast operands to v8i32 and re-build the mask. 2826 2827 // Calculate new VT, the size of the new VT should be equal to original. 2828 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT, 2829 VT.getSizeInBits()/NewEltVT.getSizeInBits()); 2830 assert(NewVT.bitsEq(VT)); 2831 2832 // cast operands to new VT 2833 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); 2834 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); 2835 2836 // Convert the shuffle mask 2837 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements(); 2838 2839 // EltVT gets smaller 2840 assert(factor > 0); 2841 2842 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) { 2843 if (Mask[i] < 0) { 2844 for (unsigned fi = 0; fi < factor; ++fi) 2845 NewMask.push_back(Mask[i]); 2846 } 2847 else { 2848 for (unsigned fi = 0; fi < factor; ++fi) 2849 NewMask.push_back(Mask[i]*factor+fi); 2850 } 2851 } 2852 Mask = NewMask; 2853 VT = NewVT; 2854 } 2855 EltVT = NewEltVT; 2856 } 2857 unsigned NumElems = VT.getVectorNumElements(); 2858 SmallVector<SDValue, 16> Ops; 2859 for (unsigned i = 0; i != NumElems; ++i) { 2860 if (Mask[i] < 0) { 2861 Ops.push_back(DAG.getUNDEF(EltVT)); 2862 continue; 2863 } 2864 unsigned Idx = Mask[i]; 2865 if (Idx < NumElems) 2866 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2867 Op0, 2868 DAG.getIntPtrConstant(Idx))); 2869 else 2870 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2871 Op1, 2872 DAG.getIntPtrConstant(Idx - NumElems))); 2873 } 2874 2875 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2876 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type. 2877 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1); 2878 Results.push_back(Tmp1); 2879 break; 2880 } 2881 case ISD::EXTRACT_ELEMENT: { 2882 EVT OpTy = Node->getOperand(0).getValueType(); 2883 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2884 // 1 -> Hi 2885 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2886 DAG.getConstant(OpTy.getSizeInBits()/2, 2887 TLI.getShiftAmountTy(Node->getOperand(0).getValueType()))); 2888 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2889 } else { 2890 // 0 -> Lo 2891 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2892 Node->getOperand(0)); 2893 } 2894 Results.push_back(Tmp1); 2895 break; 2896 } 2897 case ISD::STACKSAVE: 2898 // Expand to CopyFromReg if the target set 2899 // StackPointerRegisterToSaveRestore. 2900 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2901 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2902 Node->getValueType(0))); 2903 Results.push_back(Results[0].getValue(1)); 2904 } else { 2905 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2906 Results.push_back(Node->getOperand(0)); 2907 } 2908 break; 2909 case ISD::STACKRESTORE: 2910 // Expand to CopyToReg if the target set 2911 // StackPointerRegisterToSaveRestore. 2912 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2913 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2914 Node->getOperand(1))); 2915 } else { 2916 Results.push_back(Node->getOperand(0)); 2917 } 2918 break; 2919 case ISD::FCOPYSIGN: 2920 Results.push_back(ExpandFCOPYSIGN(Node)); 2921 break; 2922 case ISD::FNEG: 2923 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2924 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2925 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2926 Node->getOperand(0)); 2927 Results.push_back(Tmp1); 2928 break; 2929 case ISD::FABS: { 2930 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2931 EVT VT = Node->getValueType(0); 2932 Tmp1 = Node->getOperand(0); 2933 Tmp2 = DAG.getConstantFP(0.0, VT); 2934 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2935 Tmp1, Tmp2, ISD::SETUGT); 2936 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2937 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2938 Results.push_back(Tmp1); 2939 break; 2940 } 2941 case ISD::FSQRT: 2942 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2943 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2944 break; 2945 case ISD::FSIN: 2946 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2947 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2948 break; 2949 case ISD::FCOS: 2950 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2951 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2952 break; 2953 case ISD::FLOG: 2954 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2955 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2956 break; 2957 case ISD::FLOG2: 2958 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2959 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2960 break; 2961 case ISD::FLOG10: 2962 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2963 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2964 break; 2965 case ISD::FEXP: 2966 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2967 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2968 break; 2969 case ISD::FEXP2: 2970 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2971 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2972 break; 2973 case ISD::FTRUNC: 2974 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2975 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2976 break; 2977 case ISD::FFLOOR: 2978 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2979 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2980 break; 2981 case ISD::FCEIL: 2982 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2983 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2984 break; 2985 case ISD::FRINT: 2986 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2987 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2988 break; 2989 case ISD::FNEARBYINT: 2990 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2991 RTLIB::NEARBYINT_F64, 2992 RTLIB::NEARBYINT_F80, 2993 RTLIB::NEARBYINT_PPCF128)); 2994 break; 2995 case ISD::FPOWI: 2996 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2997 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2998 break; 2999 case ISD::FPOW: 3000 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 3001 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 3002 break; 3003 case ISD::FDIV: 3004 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 3005 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 3006 break; 3007 case ISD::FREM: 3008 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 3009 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 3010 break; 3011 case ISD::FMA: 3012 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64, 3013 RTLIB::FMA_F80, RTLIB::FMA_PPCF128)); 3014 break; 3015 case ISD::FP16_TO_FP32: 3016 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 3017 break; 3018 case ISD::FP32_TO_FP16: 3019 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 3020 break; 3021 case ISD::ConstantFP: { 3022 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 3023 // Check to see if this FP immediate is already legal. 3024 // If this is a legal constant, turn it into a TargetConstantFP node. 3025 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 3026 Results.push_back(ExpandConstantFP(CFP, true)); 3027 break; 3028 } 3029 case ISD::EHSELECTION: { 3030 unsigned Reg = TLI.getExceptionSelectorRegister(); 3031 assert(Reg && "Can't expand to unknown register!"); 3032 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 3033 Node->getValueType(0))); 3034 Results.push_back(Results[0].getValue(1)); 3035 break; 3036 } 3037 case ISD::EXCEPTIONADDR: { 3038 unsigned Reg = TLI.getExceptionPointerRegister(); 3039 assert(Reg && "Can't expand to unknown register!"); 3040 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 3041 Node->getValueType(0))); 3042 Results.push_back(Results[0].getValue(1)); 3043 break; 3044 } 3045 case ISD::FSUB: { 3046 EVT VT = Node->getValueType(0); 3047 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) && 3048 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && 3049 "Don't know how to expand this FP subtraction!"); 3050 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1)); 3051 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1); 3052 Results.push_back(Tmp1); 3053 break; 3054 } 3055 case ISD::SUB: { 3056 EVT VT = Node->getValueType(0); 3057 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 3058 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 3059 "Don't know how to expand this subtraction!"); 3060 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 3061 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 3062 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 3063 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 3064 break; 3065 } 3066 case ISD::UREM: 3067 case ISD::SREM: { 3068 EVT VT = Node->getValueType(0); 3069 SDVTList VTs = DAG.getVTList(VT, VT); 3070 bool isSigned = Node->getOpcode() == ISD::SREM; 3071 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 3072 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 3073 Tmp2 = Node->getOperand(0); 3074 Tmp3 = Node->getOperand(1); 3075 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) || 3076 (isDivRemLibcallAvailable(Node, isSigned, TLI) && 3077 UseDivRem(Node, isSigned, false))) { 3078 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 3079 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 3080 // X % Y -> X-X/Y*Y 3081 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 3082 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 3083 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 3084 } else if (isSigned) 3085 Tmp1 = ExpandIntLibCall(Node, true, 3086 RTLIB::SREM_I8, 3087 RTLIB::SREM_I16, RTLIB::SREM_I32, 3088 RTLIB::SREM_I64, RTLIB::SREM_I128); 3089 else 3090 Tmp1 = ExpandIntLibCall(Node, false, 3091 RTLIB::UREM_I8, 3092 RTLIB::UREM_I16, RTLIB::UREM_I32, 3093 RTLIB::UREM_I64, RTLIB::UREM_I128); 3094 Results.push_back(Tmp1); 3095 break; 3096 } 3097 case ISD::UDIV: 3098 case ISD::SDIV: { 3099 bool isSigned = Node->getOpcode() == ISD::SDIV; 3100 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 3101 EVT VT = Node->getValueType(0); 3102 SDVTList VTs = DAG.getVTList(VT, VT); 3103 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) || 3104 (isDivRemLibcallAvailable(Node, isSigned, TLI) && 3105 UseDivRem(Node, isSigned, true))) 3106 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 3107 Node->getOperand(1)); 3108 else if (isSigned) 3109 Tmp1 = ExpandIntLibCall(Node, true, 3110 RTLIB::SDIV_I8, 3111 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 3112 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 3113 else 3114 Tmp1 = ExpandIntLibCall(Node, false, 3115 RTLIB::UDIV_I8, 3116 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 3117 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 3118 Results.push_back(Tmp1); 3119 break; 3120 } 3121 case ISD::MULHU: 3122 case ISD::MULHS: { 3123 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 3124 ISD::SMUL_LOHI; 3125 EVT VT = Node->getValueType(0); 3126 SDVTList VTs = DAG.getVTList(VT, VT); 3127 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 3128 "If this wasn't legal, it shouldn't have been created!"); 3129 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 3130 Node->getOperand(1)); 3131 Results.push_back(Tmp1.getValue(1)); 3132 break; 3133 } 3134 case ISD::SDIVREM: 3135 case ISD::UDIVREM: 3136 // Expand into divrem libcall 3137 ExpandDivRemLibCall(Node, Results); 3138 break; 3139 case ISD::MUL: { 3140 EVT VT = Node->getValueType(0); 3141 SDVTList VTs = DAG.getVTList(VT, VT); 3142 // See if multiply or divide can be lowered using two-result operations. 3143 // We just need the low half of the multiply; try both the signed 3144 // and unsigned forms. If the target supports both SMUL_LOHI and 3145 // UMUL_LOHI, form a preference by checking which forms of plain 3146 // MULH it supports. 3147 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 3148 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 3149 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 3150 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3151 unsigned OpToUse = 0; 3152 if (HasSMUL_LOHI && !HasMULHS) { 3153 OpToUse = ISD::SMUL_LOHI; 3154 } else if (HasUMUL_LOHI && !HasMULHU) { 3155 OpToUse = ISD::UMUL_LOHI; 3156 } else if (HasSMUL_LOHI) { 3157 OpToUse = ISD::SMUL_LOHI; 3158 } else if (HasUMUL_LOHI) { 3159 OpToUse = ISD::UMUL_LOHI; 3160 } 3161 if (OpToUse) { 3162 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 3163 Node->getOperand(1))); 3164 break; 3165 } 3166 Tmp1 = ExpandIntLibCall(Node, false, 3167 RTLIB::MUL_I8, 3168 RTLIB::MUL_I16, RTLIB::MUL_I32, 3169 RTLIB::MUL_I64, RTLIB::MUL_I128); 3170 Results.push_back(Tmp1); 3171 break; 3172 } 3173 case ISD::SADDO: 3174 case ISD::SSUBO: { 3175 SDValue LHS = Node->getOperand(0); 3176 SDValue RHS = Node->getOperand(1); 3177 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 3178 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3179 LHS, RHS); 3180 Results.push_back(Sum); 3181 EVT OType = Node->getValueType(1); 3182 3183 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 3184 3185 // LHSSign -> LHS >= 0 3186 // RHSSign -> RHS >= 0 3187 // SumSign -> Sum >= 0 3188 // 3189 // Add: 3190 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 3191 // Sub: 3192 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 3193 // 3194 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 3195 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 3196 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 3197 Node->getOpcode() == ISD::SADDO ? 3198 ISD::SETEQ : ISD::SETNE); 3199 3200 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 3201 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 3202 3203 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 3204 Results.push_back(Cmp); 3205 break; 3206 } 3207 case ISD::UADDO: 3208 case ISD::USUBO: { 3209 SDValue LHS = Node->getOperand(0); 3210 SDValue RHS = Node->getOperand(1); 3211 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 3212 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3213 LHS, RHS); 3214 Results.push_back(Sum); 3215 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 3216 Node->getOpcode () == ISD::UADDO ? 3217 ISD::SETULT : ISD::SETUGT)); 3218 break; 3219 } 3220 case ISD::UMULO: 3221 case ISD::SMULO: { 3222 EVT VT = Node->getValueType(0); 3223 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 3224 SDValue LHS = Node->getOperand(0); 3225 SDValue RHS = Node->getOperand(1); 3226 SDValue BottomHalf; 3227 SDValue TopHalf; 3228 static const unsigned Ops[2][3] = 3229 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 3230 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 3231 bool isSigned = Node->getOpcode() == ISD::SMULO; 3232 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 3233 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 3234 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 3235 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 3236 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 3237 RHS); 3238 TopHalf = BottomHalf.getValue(1); 3239 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), 3240 VT.getSizeInBits() * 2))) { 3241 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 3242 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 3243 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 3244 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3245 DAG.getIntPtrConstant(0)); 3246 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3247 DAG.getIntPtrConstant(1)); 3248 } else { 3249 // We can fall back to a libcall with an illegal type for the MUL if we 3250 // have a libcall big enough. 3251 // Also, we can fall back to a division in some cases, but that's a big 3252 // performance hit in the general case. 3253 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3254 if (WideVT == MVT::i16) 3255 LC = RTLIB::MUL_I16; 3256 else if (WideVT == MVT::i32) 3257 LC = RTLIB::MUL_I32; 3258 else if (WideVT == MVT::i64) 3259 LC = RTLIB::MUL_I64; 3260 else if (WideVT == MVT::i128) 3261 LC = RTLIB::MUL_I128; 3262 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!"); 3263 3264 // The high part is obtained by SRA'ing all but one of the bits of low 3265 // part. 3266 unsigned LoSize = VT.getSizeInBits(); 3267 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS, 3268 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 3269 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS, 3270 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 3271 3272 // Here we're passing the 2 arguments explicitly as 4 arguments that are 3273 // pre-lowered to the correct types. This all depends upon WideVT not 3274 // being a legal type for the architecture and thus has to be split to 3275 // two arguments. 3276 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS }; 3277 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl); 3278 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret, 3279 DAG.getIntPtrConstant(0)); 3280 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret, 3281 DAG.getIntPtrConstant(1)); 3282 // Ret is a node with an illegal type. Because such things are not 3283 // generally permitted during this phase of legalization, delete the 3284 // node. The above EXTRACT_ELEMENT nodes should have been folded. 3285 DAG.DeleteNode(Ret.getNode()); 3286 } 3287 3288 if (isSigned) { 3289 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, 3290 TLI.getShiftAmountTy(BottomHalf.getValueType())); 3291 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 3292 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 3293 ISD::SETNE); 3294 } else { 3295 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 3296 DAG.getConstant(0, VT), ISD::SETNE); 3297 } 3298 Results.push_back(BottomHalf); 3299 Results.push_back(TopHalf); 3300 break; 3301 } 3302 case ISD::BUILD_PAIR: { 3303 EVT PairTy = Node->getValueType(0); 3304 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 3305 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 3306 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 3307 DAG.getConstant(PairTy.getSizeInBits()/2, 3308 TLI.getShiftAmountTy(PairTy))); 3309 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 3310 break; 3311 } 3312 case ISD::SELECT: 3313 Tmp1 = Node->getOperand(0); 3314 Tmp2 = Node->getOperand(1); 3315 Tmp3 = Node->getOperand(2); 3316 if (Tmp1.getOpcode() == ISD::SETCC) { 3317 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 3318 Tmp2, Tmp3, 3319 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 3320 } else { 3321 Tmp1 = DAG.getSelectCC(dl, Tmp1, 3322 DAG.getConstant(0, Tmp1.getValueType()), 3323 Tmp2, Tmp3, ISD::SETNE); 3324 } 3325 Results.push_back(Tmp1); 3326 break; 3327 case ISD::BR_JT: { 3328 SDValue Chain = Node->getOperand(0); 3329 SDValue Table = Node->getOperand(1); 3330 SDValue Index = Node->getOperand(2); 3331 3332 EVT PTy = TLI.getPointerTy(); 3333 3334 const TargetData &TD = *TLI.getTargetData(); 3335 unsigned EntrySize = 3336 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 3337 3338 Index = DAG.getNode(ISD::MUL, dl, PTy, 3339 Index, DAG.getConstant(EntrySize, PTy)); 3340 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 3341 3342 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 3343 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 3344 MachinePointerInfo::getJumpTable(), MemVT, 3345 false, false, 0); 3346 Addr = LD; 3347 if (TM.getRelocationModel() == Reloc::PIC_) { 3348 // For PIC, the sequence is: 3349 // BRIND(load(Jumptable + index) + RelocBase) 3350 // RelocBase can be JumpTable, GOT or some sort of global base. 3351 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 3352 TLI.getPICJumpTableRelocBase(Table, DAG)); 3353 } 3354 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 3355 Results.push_back(Tmp1); 3356 break; 3357 } 3358 case ISD::BRCOND: 3359 // Expand brcond's setcc into its constituent parts and create a BR_CC 3360 // Node. 3361 Tmp1 = Node->getOperand(0); 3362 Tmp2 = Node->getOperand(1); 3363 if (Tmp2.getOpcode() == ISD::SETCC) { 3364 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 3365 Tmp1, Tmp2.getOperand(2), 3366 Tmp2.getOperand(0), Tmp2.getOperand(1), 3367 Node->getOperand(2)); 3368 } else { 3369 // We test only the i1 bit. Skip the AND if UNDEF. 3370 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 : 3371 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2, 3372 DAG.getConstant(1, Tmp2.getValueType())); 3373 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 3374 DAG.getCondCode(ISD::SETNE), Tmp3, 3375 DAG.getConstant(0, Tmp3.getValueType()), 3376 Node->getOperand(2)); 3377 } 3378 Results.push_back(Tmp1); 3379 break; 3380 case ISD::SETCC: { 3381 Tmp1 = Node->getOperand(0); 3382 Tmp2 = Node->getOperand(1); 3383 Tmp3 = Node->getOperand(2); 3384 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 3385 3386 // If we expanded the SETCC into an AND/OR, return the new node 3387 if (Tmp2.getNode() == 0) { 3388 Results.push_back(Tmp1); 3389 break; 3390 } 3391 3392 // Otherwise, SETCC for the given comparison type must be completely 3393 // illegal; expand it into a SELECT_CC. 3394 EVT VT = Node->getValueType(0); 3395 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3396 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 3397 Results.push_back(Tmp1); 3398 break; 3399 } 3400 case ISD::SELECT_CC: { 3401 Tmp1 = Node->getOperand(0); // LHS 3402 Tmp2 = Node->getOperand(1); // RHS 3403 Tmp3 = Node->getOperand(2); // True 3404 Tmp4 = Node->getOperand(3); // False 3405 SDValue CC = Node->getOperand(4); 3406 3407 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 3408 Tmp1, Tmp2, CC, dl); 3409 3410 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 3411 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3412 CC = DAG.getCondCode(ISD::SETNE); 3413 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 3414 Tmp3, Tmp4, CC); 3415 Results.push_back(Tmp1); 3416 break; 3417 } 3418 case ISD::BR_CC: { 3419 Tmp1 = Node->getOperand(0); // Chain 3420 Tmp2 = Node->getOperand(2); // LHS 3421 Tmp3 = Node->getOperand(3); // RHS 3422 Tmp4 = Node->getOperand(1); // CC 3423 3424 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 3425 Tmp2, Tmp3, Tmp4, dl); 3426 3427 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 3428 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 3429 Tmp4 = DAG.getCondCode(ISD::SETNE); 3430 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3431 Tmp3, Node->getOperand(4)); 3432 Results.push_back(Tmp1); 3433 break; 3434 } 3435 case ISD::BUILD_VECTOR: 3436 Results.push_back(ExpandBUILD_VECTOR(Node)); 3437 break; 3438 case ISD::SRA: 3439 case ISD::SRL: 3440 case ISD::SHL: { 3441 // Scalarize vector SRA/SRL/SHL. 3442 EVT VT = Node->getValueType(0); 3443 assert(VT.isVector() && "Unable to legalize non-vector shift"); 3444 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal"); 3445 unsigned NumElem = VT.getVectorNumElements(); 3446 3447 SmallVector<SDValue, 8> Scalars; 3448 for (unsigned Idx = 0; Idx < NumElem; Idx++) { 3449 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 3450 VT.getScalarType(), 3451 Node->getOperand(0), DAG.getIntPtrConstant(Idx)); 3452 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 3453 VT.getScalarType(), 3454 Node->getOperand(1), DAG.getIntPtrConstant(Idx)); 3455 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl, 3456 VT.getScalarType(), Ex, Sh)); 3457 } 3458 SDValue Result = 3459 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), 3460 &Scalars[0], Scalars.size()); 3461 ReplaceNode(SDValue(Node, 0), Result); 3462 break; 3463 } 3464 case ISD::GLOBAL_OFFSET_TABLE: 3465 case ISD::GlobalAddress: 3466 case ISD::GlobalTLSAddress: 3467 case ISD::ExternalSymbol: 3468 case ISD::ConstantPool: 3469 case ISD::JumpTable: 3470 case ISD::INTRINSIC_W_CHAIN: 3471 case ISD::INTRINSIC_WO_CHAIN: 3472 case ISD::INTRINSIC_VOID: 3473 // FIXME: Custom lowering for these operations shouldn't return null! 3474 break; 3475 } 3476 3477 // Replace the original node with the legalized result. 3478 if (!Results.empty()) 3479 ReplaceNode(Node, Results.data()); 3480 } 3481 3482 void SelectionDAGLegalize::PromoteNode(SDNode *Node) { 3483 SmallVector<SDValue, 8> Results; 3484 EVT OVT = Node->getValueType(0); 3485 if (Node->getOpcode() == ISD::UINT_TO_FP || 3486 Node->getOpcode() == ISD::SINT_TO_FP || 3487 Node->getOpcode() == ISD::SETCC) { 3488 OVT = Node->getOperand(0).getValueType(); 3489 } 3490 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3491 DebugLoc dl = Node->getDebugLoc(); 3492 SDValue Tmp1, Tmp2, Tmp3; 3493 switch (Node->getOpcode()) { 3494 case ISD::CTTZ: 3495 case ISD::CTTZ_ZERO_UNDEF: 3496 case ISD::CTLZ: 3497 case ISD::CTLZ_ZERO_UNDEF: 3498 case ISD::CTPOP: 3499 // Zero extend the argument. 3500 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3501 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is 3502 // already the correct result. 3503 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3504 if (Node->getOpcode() == ISD::CTTZ) { 3505 // FIXME: This should set a bit in the zero extended value instead. 3506 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3507 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3508 ISD::SETEQ); 3509 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3510 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3511 } else if (Node->getOpcode() == ISD::CTLZ || 3512 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) { 3513 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3514 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3515 DAG.getConstant(NVT.getSizeInBits() - 3516 OVT.getSizeInBits(), NVT)); 3517 } 3518 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3519 break; 3520 case ISD::BSWAP: { 3521 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3522 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3523 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3524 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3525 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT))); 3526 Results.push_back(Tmp1); 3527 break; 3528 } 3529 case ISD::FP_TO_UINT: 3530 case ISD::FP_TO_SINT: 3531 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3532 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3533 Results.push_back(Tmp1); 3534 break; 3535 case ISD::UINT_TO_FP: 3536 case ISD::SINT_TO_FP: 3537 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3538 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3539 Results.push_back(Tmp1); 3540 break; 3541 case ISD::VAARG: { 3542 SDValue Chain = Node->getOperand(0); // Get the chain. 3543 SDValue Ptr = Node->getOperand(1); // Get the pointer. 3544 3545 unsigned TruncOp; 3546 if (OVT.isVector()) { 3547 TruncOp = ISD::BITCAST; 3548 } else { 3549 assert(OVT.isInteger() 3550 && "VAARG promotion is supported only for vectors or integer types"); 3551 TruncOp = ISD::TRUNCATE; 3552 } 3553 3554 // Perform the larger operation, then convert back 3555 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2), 3556 Node->getConstantOperandVal(3)); 3557 Chain = Tmp1.getValue(1); 3558 3559 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1); 3560 3561 // Modified the chain result - switch anything that used the old chain to 3562 // use the new one. 3563 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2); 3564 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain); 3565 ReplacedNode(Node); 3566 break; 3567 } 3568 case ISD::AND: 3569 case ISD::OR: 3570 case ISD::XOR: { 3571 unsigned ExtOp, TruncOp; 3572 if (OVT.isVector()) { 3573 ExtOp = ISD::BITCAST; 3574 TruncOp = ISD::BITCAST; 3575 } else { 3576 assert(OVT.isInteger() && "Cannot promote logic operation"); 3577 ExtOp = ISD::ANY_EXTEND; 3578 TruncOp = ISD::TRUNCATE; 3579 } 3580 // Promote each of the values to the new type. 3581 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3582 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3583 // Perform the larger operation, then convert back 3584 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3585 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3586 break; 3587 } 3588 case ISD::SELECT: { 3589 unsigned ExtOp, TruncOp; 3590 if (Node->getValueType(0).isVector()) { 3591 ExtOp = ISD::BITCAST; 3592 TruncOp = ISD::BITCAST; 3593 } else if (Node->getValueType(0).isInteger()) { 3594 ExtOp = ISD::ANY_EXTEND; 3595 TruncOp = ISD::TRUNCATE; 3596 } else { 3597 ExtOp = ISD::FP_EXTEND; 3598 TruncOp = ISD::FP_ROUND; 3599 } 3600 Tmp1 = Node->getOperand(0); 3601 // Promote each of the values to the new type. 3602 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3603 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3604 // Perform the larger operation, then round down. 3605 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3606 if (TruncOp != ISD::FP_ROUND) 3607 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3608 else 3609 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3610 DAG.getIntPtrConstant(0)); 3611 Results.push_back(Tmp1); 3612 break; 3613 } 3614 case ISD::VECTOR_SHUFFLE: { 3615 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask(); 3616 3617 // Cast the two input vectors. 3618 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0)); 3619 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1)); 3620 3621 // Convert the shuffle mask to the right # elements. 3622 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3623 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1); 3624 Results.push_back(Tmp1); 3625 break; 3626 } 3627 case ISD::SETCC: { 3628 unsigned ExtOp = ISD::FP_EXTEND; 3629 if (NVT.isInteger()) { 3630 ISD::CondCode CCCode = 3631 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3632 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3633 } 3634 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3635 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3636 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3637 Tmp1, Tmp2, Node->getOperand(2))); 3638 break; 3639 } 3640 case ISD::FDIV: 3641 case ISD::FREM: 3642 case ISD::FPOW: { 3643 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); 3644 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); 3645 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3646 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, 3647 Tmp3, DAG.getIntPtrConstant(0))); 3648 break; 3649 } 3650 case ISD::FLOG2: 3651 case ISD::FEXP2: 3652 case ISD::FLOG: 3653 case ISD::FEXP: { 3654 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); 3655 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3656 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, 3657 Tmp2, DAG.getIntPtrConstant(0))); 3658 break; 3659 } 3660 } 3661 3662 // Replace the original node with the legalized result. 3663 if (!Results.empty()) 3664 ReplaceNode(Node, Results.data()); 3665 } 3666 3667 // SelectionDAG::Legalize - This is the entry point for the file. 3668 // 3669 void SelectionDAG::Legalize() { 3670 /// run - This is the main entry point to this class. 3671 /// 3672 SelectionDAGLegalize(*this).LegalizeDAG(); 3673 } 3674