| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 583 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
584 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
589 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
591 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
597 KnownZero <<= ShiftAmt;
598 KnownOne <<= ShiftAmt;
600 if (ShiftAmt)
601 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
607 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
610 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
[all...] |
| InstCombineCasts.cpp | 560 uint32_t ShiftAmt = KnownZeroMask.logBase2();
562 if (ShiftAmt) {
563 // Perform a logical shr by shiftamt.
565 In = Builder->CreateLShr(In, ConstantInt::get(In->getType(),ShiftAmt),
[all...] |
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | 168 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1);
179 ConstantInt::get(Src->getType(), ShiftAmt));
180 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize;
200 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1);
205 ConstantInt::get(Src->getType(), ShiftAmt));
206 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize;
[all...] |
| ValueTracking.cpp | 475 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
478 KnownZero <<= ShiftAmt;
479 KnownOne <<= ShiftAmt;
480 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt); // low bits known 0
488 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
493 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
494 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt);
496 KnownZero |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
504 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
509 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 802 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
803 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
808 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
822 AM.Scale = 1 << ShiftAmt;
862 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 629 unsigned ShiftAmt = SVOp->getMaskElt(i);
630 if (ShiftAmt < i) return -1;
631 ShiftAmt -= i;
636 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
641 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
644 return ShiftAmt;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
