Home | History | Annotate | Download | only in Mips 
      1 //===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines an instruction selector for the MIPS target.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #define DEBUG_TYPE "mips-isel"
     15 #include "Mips.h"
     16 #include "MipsAnalyzeImmediate.h"
     17 #include "MipsMachineFunction.h"
     18 #include "MipsRegisterInfo.h"
     19 #include "MipsSubtarget.h"
     20 #include "MipsTargetMachine.h"
     21 #include "MCTargetDesc/MipsBaseInfo.h"
     22 #include "llvm/GlobalValue.h"
     23 #include "llvm/Instructions.h"
     24 #include "llvm/Intrinsics.h"
     25 #include "llvm/Support/CFG.h"
     26 #include "llvm/Type.h"
     27 #include "llvm/CodeGen/MachineConstantPool.h"
     28 #include "llvm/CodeGen/MachineFunction.h"
     29 #include "llvm/CodeGen/MachineFrameInfo.h"
     30 #include "llvm/CodeGen/MachineInstrBuilder.h"
     31 #include "llvm/CodeGen/MachineRegisterInfo.h"
     32 #include "llvm/CodeGen/SelectionDAGISel.h"
     33 #include "llvm/CodeGen/SelectionDAGNodes.h"
     34 #include "llvm/Target/TargetMachine.h"
     35 #include "llvm/Support/Debug.h"
     36 #include "llvm/Support/ErrorHandling.h"
     37 #include "llvm/Support/raw_ostream.h"
     38 using namespace llvm;
     39 
     40 //===----------------------------------------------------------------------===//
     41 // Instruction Selector Implementation
     42 //===----------------------------------------------------------------------===//
     43 
     44 //===----------------------------------------------------------------------===//
     45 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
     46 // instructions for SelectionDAG operations.
     47 //===----------------------------------------------------------------------===//
     48 namespace {
     49 
     50 class MipsDAGToDAGISel : public SelectionDAGISel {
     51 
     52   /// TM - Keep a reference to MipsTargetMachine.
     53   MipsTargetMachine &TM;
     54 
     55   /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
     56   /// make the right decision when generating code for different targets.
     57   const MipsSubtarget &Subtarget;
     58 
     59 public:
     60   explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
     61   SelectionDAGISel(tm),
     62   TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
     63 
     64   // Pass Name
     65   virtual const char *getPassName() const {
     66     return "MIPS DAG->DAG Pattern Instruction Selection";
     67   }
     68 
     69   virtual bool runOnMachineFunction(MachineFunction &MF);
     70 
     71 private:
     72   // Include the pieces autogenerated from the target description.
     73   #include "MipsGenDAGISel.inc"
     74 
     75   /// getTargetMachine - Return a reference to the TargetMachine, casted
     76   /// to the target-specific type.
     77   const MipsTargetMachine &getTargetMachine() {
     78     return static_cast<const MipsTargetMachine &>(TM);
     79   }
     80 
     81   /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
     82   /// to the target-specific type.
     83   const MipsInstrInfo *getInstrInfo() {
     84     return getTargetMachine().getInstrInfo();
     85   }
     86 
     87   SDNode *getGlobalBaseReg();
     88 
     89   std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
     90                                          EVT Ty, bool HasLo, bool HasHi);
     91 
     92   SDNode *Select(SDNode *N);
     93 
     94   // Complex Pattern.
     95   bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
     96 
     97   // getImm - Return a target constant with the specified value.
     98   inline SDValue getImm(const SDNode *Node, unsigned Imm) {
     99     return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
    100   }
    101 
    102   void ProcessFunctionAfterISel(MachineFunction &MF);
    103   bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
    104   void InitGlobalBaseReg(MachineFunction &MF);
    105 
    106   virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
    107                                             char ConstraintCode,
    108                                             std::vector<SDValue> &OutOps);
    109 };
    110 
    111 }
    112 
    113 // Insert instructions to initialize the global base register in the
    114 // first MBB of the function. When the ABI is O32 and the relocation model is
    115 // PIC, the necessary instructions are emitted later to prevent optimization
    116 // passes from moving them.
    117 void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
    118   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
    119 
    120   if (!MipsFI->globalBaseRegSet())
    121     return;
    122 
    123   MachineBasicBlock &MBB = MF.front();
    124   MachineBasicBlock::iterator I = MBB.begin();
    125   MachineRegisterInfo &RegInfo = MF.getRegInfo();
    126   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    127   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
    128   unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
    129   bool FixGlobalBaseReg = MipsFI->globalBaseRegFixed();
    130 
    131   if (Subtarget.isABI_O32() && FixGlobalBaseReg)
    132     // $gp is the global base register.
    133     V0 = V1 = GlobalBaseReg;
    134   else {
    135     const TargetRegisterClass *RC;
    136     RC = Subtarget.isABI_N64() ?
    137          Mips::CPU64RegsRegisterClass : Mips::CPURegsRegisterClass;
    138 
    139     V0 = RegInfo.createVirtualRegister(RC);
    140     V1 = RegInfo.createVirtualRegister(RC);
    141   }
    142 
    143   if (Subtarget.isABI_N64()) {
    144     MF.getRegInfo().addLiveIn(Mips::T9_64);
    145     MBB.addLiveIn(Mips::T9_64);
    146 
    147     // lui $v0, %hi(%neg(%gp_rel(fname)))
    148     // daddu $v1, $v0, $t9
    149     // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
    150     const GlobalValue *FName = MF.getFunction();
    151     BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
    152       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
    153     BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0).addReg(Mips::T9_64);
    154     BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
    155       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
    156   } else if (MF.getTarget().getRelocationModel() == Reloc::Static) {
    157     // Set global register to __gnu_local_gp.
    158     //
    159     // lui   $v0, %hi(__gnu_local_gp)
    160     // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
    161     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
    162       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
    163     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
    164       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
    165   } else {
    166     MF.getRegInfo().addLiveIn(Mips::T9);
    167     MBB.addLiveIn(Mips::T9);
    168 
    169     if (Subtarget.isABI_N32()) {
    170       // lui $v0, %hi(%neg(%gp_rel(fname)))
    171       // addu $v1, $v0, $t9
    172       // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
    173       const GlobalValue *FName = MF.getFunction();
    174       BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
    175         .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
    176       BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
    177       BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
    178         .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
    179     } else if (!MipsFI->globalBaseRegFixed()) {
    180       assert(Subtarget.isABI_O32());
    181 
    182       BuildMI(MBB, I, DL, TII.get(Mips::SETGP2), GlobalBaseReg)
    183         .addReg(Mips::T9);
    184     }
    185   }
    186 }
    187 
    188 bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
    189                                               const MachineInstr& MI) {
    190   unsigned DstReg = 0, ZeroReg = 0;
    191 
    192   // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
    193   if ((MI.getOpcode() == Mips::ADDiu) &&
    194       (MI.getOperand(1).getReg() == Mips::ZERO) &&
    195       (MI.getOperand(2).getImm() == 0)) {
    196     DstReg = MI.getOperand(0).getReg();
    197     ZeroReg = Mips::ZERO;
    198   } else if ((MI.getOpcode() == Mips::DADDiu) &&
    199              (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
    200              (MI.getOperand(2).getImm() == 0)) {
    201     DstReg = MI.getOperand(0).getReg();
    202     ZeroReg = Mips::ZERO_64;
    203   }
    204 
    205   if (!DstReg)
    206     return false;
    207 
    208   // Replace uses with ZeroReg.
    209   for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
    210        E = MRI->use_end(); U != E; ++U) {
    211     MachineOperand &MO = U.getOperand();
    212     MachineInstr *MI = MO.getParent();
    213 
    214     // Do not replace if it is a phi's operand or is tied to def operand.
    215     if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo()))
    216       continue;
    217 
    218     MO.setReg(ZeroReg);
    219   }
    220 
    221   return true;
    222 }
    223 
    224 void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) {
    225   InitGlobalBaseReg(MF);
    226 
    227   MachineRegisterInfo *MRI = &MF.getRegInfo();
    228 
    229   for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
    230        ++MFI)
    231     for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
    232       ReplaceUsesWithZeroReg(MRI, *I);
    233 }
    234 
    235 bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
    236   bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
    237 
    238   ProcessFunctionAfterISel(MF);
    239 
    240   return Ret;
    241 }
    242 
    243 /// getGlobalBaseReg - Output the instructions required to put the
    244 /// GOT address into a register.
    245 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
    246   unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
    247   return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
    248 }
    249 
    250 /// ComplexPattern used on MipsInstrInfo
    251 /// Used on Mips Load/Store instructions
    252 bool MipsDAGToDAGISel::
    253 SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
    254   EVT ValTy = Addr.getValueType();
    255 
    256   // If Parent is an unaligned f32 load or store, select a (base + index)
    257   // floating point load/store instruction (luxc1 or suxc1).
    258   const LSBaseSDNode* LS = 0;
    259 
    260   if (Parent && (LS = dyn_cast<LSBaseSDNode>(Parent))) {
    261     EVT VT = LS->getMemoryVT();
    262 
    263     if (VT.getSizeInBits() / 8 > LS->getAlignment()) {
    264       assert(TLI.allowsUnalignedMemoryAccesses(VT) &&
    265              "Unaligned loads/stores not supported for this type.");
    266       if (VT == MVT::f32)
    267         return false;
    268     }
    269   }
    270 
    271   // if Address is FI, get the TargetFrameIndex.
    272   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
    273     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
    274     Offset = CurDAG->getTargetConstant(0, ValTy);
    275     return true;
    276   }
    277 
    278   // on PIC code Load GA
    279   if (Addr.getOpcode() == MipsISD::Wrapper) {
    280     Base   = Addr.getOperand(0);
    281     Offset = Addr.getOperand(1);
    282     return true;
    283   }
    284 
    285   if (TM.getRelocationModel() != Reloc::PIC_) {
    286     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
    287         Addr.getOpcode() == ISD::TargetGlobalAddress))
    288       return false;
    289   }
    290 
    291   // Addresses of the form FI+const or FI|const
    292   if (CurDAG->isBaseWithConstantOffset(Addr)) {
    293     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
    294     if (isInt<16>(CN->getSExtValue())) {
    295 
    296       // If the first operand is a FI, get the TargetFI Node
    297       if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
    298                                   (Addr.getOperand(0)))
    299         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
    300       else
    301         Base = Addr.getOperand(0);
    302 
    303       Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
    304       return true;
    305     }
    306   }
    307 
    308   // Operand is a result from an ADD.
    309   if (Addr.getOpcode() == ISD::ADD) {
    310     // When loading from constant pools, load the lower address part in
    311     // the instruction itself. Example, instead of:
    312     //  lui $2, %hi($CPI1_0)
    313     //  addiu $2, $2, %lo($CPI1_0)
    314     //  lwc1 $f0, 0($2)
    315     // Generate:
    316     //  lui $2, %hi($CPI1_0)
    317     //  lwc1 $f0, %lo($CPI1_0)($2)
    318     if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
    319       SDValue LoVal = Addr.getOperand(1);
    320       if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
    321           isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
    322         Base = Addr.getOperand(0);
    323         Offset = LoVal.getOperand(0);
    324         return true;
    325       }
    326     }
    327 
    328     // If an indexed floating point load/store can be emitted, return false.
    329     if (LS && (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
    330         Subtarget.hasMips32r2Or64())
    331       return false;
    332   }
    333 
    334   Base   = Addr;
    335   Offset = CurDAG->getTargetConstant(0, ValTy);
    336   return true;
    337 }
    338 
    339 /// Select multiply instructions.
    340 std::pair<SDNode*, SDNode*>
    341 MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
    342                              bool HasLo, bool HasHi) {
    343   SDNode *Lo = 0, *Hi = 0;
    344   SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
    345                                        N->getOperand(1));
    346   SDValue InFlag = SDValue(Mul, 0);
    347 
    348   if (HasLo) {
    349     Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
    350                                 Ty, MVT::Glue, InFlag);
    351     InFlag = SDValue(Lo, 1);
    352   }
    353   if (HasHi)
    354     Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
    355                                 Ty, InFlag);
    356 
    357   return std::make_pair(Lo, Hi);
    358 }
    359 
    360 
    361 /// Select instructions not customized! Used for
    362 /// expanded, promoted and normal instructions
    363 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
    364   unsigned Opcode = Node->getOpcode();
    365   DebugLoc dl = Node->getDebugLoc();
    366 
    367   // Dump information about the Node being selected
    368   DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
    369 
    370   // If we have a custom node, we already have selected!
    371   if (Node->isMachineOpcode()) {
    372     DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
    373     return NULL;
    374   }
    375 
    376   ///
    377   // Instruction Selection not handled by the auto-generated
    378   // tablegen selection should be handled here.
    379   ///
    380   EVT NodeTy = Node->getValueType(0);
    381   unsigned MultOpc;
    382 
    383   switch(Opcode) {
    384   default: break;
    385 
    386   case ISD::SUBE:
    387   case ISD::ADDE: {
    388     SDValue InFlag = Node->getOperand(2), CmpLHS;
    389     unsigned Opc = InFlag.getOpcode(); (void)Opc;
    390     assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
    391             (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
    392            "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
    393 
    394     unsigned MOp;
    395     if (Opcode == ISD::ADDE) {
    396       CmpLHS = InFlag.getValue(0);
    397       MOp = Mips::ADDu;
    398     } else {
    399       CmpLHS = InFlag.getOperand(0);
    400       MOp = Mips::SUBu;
    401     }
    402 
    403     SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
    404 
    405     SDValue LHS = Node->getOperand(0);
    406     SDValue RHS = Node->getOperand(1);
    407 
    408     EVT VT = LHS.getValueType();
    409     SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
    410     SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
    411                                               SDValue(Carry,0), RHS);
    412 
    413     return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
    414                                 LHS, SDValue(AddCarry,0));
    415   }
    416 
    417   /// Mul with two results
    418   case ISD::SMUL_LOHI:
    419   case ISD::UMUL_LOHI: {
    420     if (NodeTy == MVT::i32)
    421       MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
    422     else
    423       MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
    424 
    425     std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
    426                                                   true, true);
    427 
    428     if (!SDValue(Node, 0).use_empty())
    429       ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
    430 
    431     if (!SDValue(Node, 1).use_empty())
    432       ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
    433 
    434     return NULL;
    435   }
    436 
    437   /// Special Muls
    438   case ISD::MUL: {
    439     // Mips32 has a 32-bit three operand mul instruction.
    440     if (Subtarget.hasMips32() && NodeTy == MVT::i32)
    441       break;
    442     return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
    443                       dl, NodeTy, true, false).first;
    444   }
    445   case ISD::MULHS:
    446   case ISD::MULHU: {
    447     if (NodeTy == MVT::i32)
    448       MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
    449     else
    450       MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
    451 
    452     return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
    453   }
    454 
    455   // Get target GOT address.
    456   case ISD::GLOBAL_OFFSET_TABLE:
    457     return getGlobalBaseReg();
    458 
    459   case ISD::ConstantFP: {
    460     ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
    461     if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
    462       if (Subtarget.hasMips64()) {
    463         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
    464                                               Mips::ZERO_64, MVT::i64);
    465         return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
    466       }
    467 
    468       SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
    469                                             Mips::ZERO, MVT::i32);
    470       return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
    471                                     Zero);
    472     }
    473     break;
    474   }
    475 
    476   case ISD::Constant: {
    477     const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
    478     unsigned Size = CN->getValueSizeInBits(0);
    479 
    480     if (Size == 32)
    481       break;
    482 
    483     MipsAnalyzeImmediate AnalyzeImm;
    484     int64_t Imm = CN->getSExtValue();
    485 
    486     const MipsAnalyzeImmediate::InstSeq &Seq =
    487       AnalyzeImm.Analyze(Imm, Size, false);
    488 
    489     MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
    490     DebugLoc DL = CN->getDebugLoc();
    491     SDNode *RegOpnd;
    492     SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
    493                                                 MVT::i64);
    494 
    495     // The first instruction can be a LUi which is different from other
    496     // instructions (ADDiu, ORI and SLL) in that it does not have a register
    497     // operand.
    498     if (Inst->Opc == Mips::LUi64)
    499       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
    500     else
    501       RegOpnd =
    502         CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
    503                                CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
    504                                ImmOpnd);
    505 
    506     // The remaining instructions in the sequence are handled here.
    507     for (++Inst; Inst != Seq.end(); ++Inst) {
    508       ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
    509                                           MVT::i64);
    510       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
    511                                        SDValue(RegOpnd, 0), ImmOpnd);
    512     }
    513 
    514     return RegOpnd;
    515   }
    516 
    517   case MipsISD::ThreadPointer: {
    518     EVT PtrVT = TLI.getPointerTy();
    519     unsigned RdhwrOpc, SrcReg, DestReg;
    520 
    521     if (PtrVT == MVT::i32) {
    522       RdhwrOpc = Mips::RDHWR;
    523       SrcReg = Mips::HWR29;
    524       DestReg = Mips::V1;
    525     } else {
    526       RdhwrOpc = Mips::RDHWR64;
    527       SrcReg = Mips::HWR29_64;
    528       DestReg = Mips::V1_64;
    529     }
    530 
    531     SDNode *Rdhwr =
    532       CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
    533                              Node->getValueType(0),
    534                              CurDAG->getRegister(SrcReg, PtrVT));
    535     SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
    536                                          SDValue(Rdhwr, 0));
    537     SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
    538     ReplaceUses(SDValue(Node, 0), ResNode);
    539     return ResNode.getNode();
    540   }
    541   }
    542 
    543   // Select the default instruction
    544   SDNode *ResNode = SelectCode(Node);
    545 
    546   DEBUG(errs() << "=> ");
    547   if (ResNode == NULL || ResNode == Node)
    548     DEBUG(Node->dump(CurDAG));
    549   else
    550     DEBUG(ResNode->dump(CurDAG));
    551   DEBUG(errs() << "\n");
    552   return ResNode;
    553 }
    554 
    555 bool MipsDAGToDAGISel::
    556 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
    557                              std::vector<SDValue> &OutOps) {
    558   assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
    559   OutOps.push_back(Op);
    560   return false;
    561 }
    562 
    563 /// createMipsISelDag - This pass converts a legalized DAG into a
    564 /// MIPS-specific DAG, ready for instruction scheduling.
    565 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
    566   return new MipsDAGToDAGISel(TM);
    567 }
    568