1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares codegen opcodes and related utilities. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_ISDOPCODES_H 15 #define LLVM_CODEGEN_ISDOPCODES_H 16 17 namespace llvm { 18 19 /// ISD namespace - This namespace contains an enum which represents all of the 20 /// SelectionDAG node types and value types. 21 /// 22 namespace ISD { 23 24 //===--------------------------------------------------------------------===// 25 /// ISD::NodeType enum - This enum defines the target-independent operators 26 /// for a SelectionDAG. 27 /// 28 /// Targets may also define target-dependent operator codes for SDNodes. For 29 /// example, on x86, these are the enum values in the X86ISD namespace. 30 /// Targets should aim to use target-independent operators to model their 31 /// instruction sets as much as possible, and only use target-dependent 32 /// operators when they have special requirements. 33 /// 34 /// Finally, during and after selection proper, SNodes may use special 35 /// operator codes that correspond directly with MachineInstr opcodes. These 36 /// are used to represent selected instructions. See the isMachineOpcode() 37 /// and getMachineOpcode() member functions of SDNode. 38 /// 39 enum NodeType { 40 // DELETED_NODE - This is an illegal value that is used to catch 41 // errors. This opcode is not a legal opcode for any node. 42 DELETED_NODE, 43 44 // EntryToken - This is the marker used to indicate the start of the region. 45 EntryToken, 46 47 // TokenFactor - This node takes multiple tokens as input and produces a 48 // single token result. This is used to represent the fact that the operand 49 // operators are independent of each other. 50 TokenFactor, 51 52 // AssertSext, AssertZext - These nodes record if a register contains a 53 // value that has already been zero or sign extended from a narrower type. 54 // These nodes take two operands. The first is the node that has already 55 // been extended, and the second is a value type node indicating the width 56 // of the extension 57 AssertSext, AssertZext, 58 59 // Various leaf nodes. 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, 61 Constant, ConstantFP, 62 GlobalAddress, GlobalTLSAddress, FrameIndex, 63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress, 64 65 // The address of the GOT 66 GLOBAL_OFFSET_TABLE, 67 68 // FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 69 // llvm.returnaddress on the DAG. These nodes take one operand, the index 70 // of the frame or return address to return. An index of zero corresponds 71 // to the current function's frame or return address, an index of one to the 72 // parent's frame or return address, and so on. 73 FRAMEADDR, RETURNADDR, 74 75 // FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 76 // first (possible) on-stack argument. This is needed for correct stack 77 // adjustment during unwind. 78 FRAME_TO_ARGS_OFFSET, 79 80 // RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents the 81 // address of the exception block on entry to an landing pad block. 82 EXCEPTIONADDR, 83 84 // RESULT, OUTCHAIN = LSDAADDR(INCHAIN) - This node represents the 85 // address of the Language Specific Data Area for the enclosing function. 86 LSDAADDR, 87 88 // RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node represents 89 // the selection index of the exception thrown. 90 EHSELECTION, 91 92 // OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 93 // 'eh_return' gcc dwarf builtin, which is used to return from 94 // exception. The general meaning is: adjust stack by OFFSET and pass 95 // execution to HANDLER. Many platform-related details also :) 96 EH_RETURN, 97 98 // RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 99 // This corresponds to the eh.sjlj.setjmp intrinsic. 100 // It takes an input chain and a pointer to the jump buffer as inputs 101 // and returns an outchain. 102 EH_SJLJ_SETJMP, 103 104 // OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 105 // This corresponds to the eh.sjlj.longjmp intrinsic. 106 // It takes an input chain and a pointer to the jump buffer as inputs 107 // and returns an outchain. 108 EH_SJLJ_LONGJMP, 109 110 // TargetConstant* - Like Constant*, but the DAG does not do any folding, 111 // simplification, or lowering of the constant. They are used for constants 112 // which are known to fit in the immediate fields of their users, or for 113 // carrying magic numbers which are not values which need to be materialized 114 // in registers. 115 TargetConstant, 116 TargetConstantFP, 117 118 // TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 119 // anything else with this node, and this is valid in the target-specific 120 // dag, turning into a GlobalAddress operand. 121 TargetGlobalAddress, 122 TargetGlobalTLSAddress, 123 TargetFrameIndex, 124 TargetJumpTable, 125 TargetConstantPool, 126 TargetExternalSymbol, 127 TargetBlockAddress, 128 129 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 130 /// This node represents a target intrinsic function with no side effects. 131 /// The first operand is the ID number of the intrinsic from the 132 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 133 /// node returns the result of the intrinsic. 134 INTRINSIC_WO_CHAIN, 135 136 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 137 /// This node represents a target intrinsic function with side effects that 138 /// returns a result. The first operand is a chain pointer. The second is 139 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 140 /// operands to the intrinsic follow. The node has two results, the result 141 /// of the intrinsic and an output chain. 142 INTRINSIC_W_CHAIN, 143 144 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 145 /// This node represents a target intrinsic function with side effects that 146 /// does not return a result. The first operand is a chain pointer. The 147 /// second is the ID number of the intrinsic from the llvm::Intrinsic 148 /// namespace. The operands to the intrinsic follow. 149 INTRINSIC_VOID, 150 151 // CopyToReg - This node has three operands: a chain, a register number to 152 // set to this value, and a value. 153 CopyToReg, 154 155 // CopyFromReg - This node indicates that the input value is a virtual or 156 // physical register that is defined outside of the scope of this 157 // SelectionDAG. The register is available from the RegisterSDNode object. 158 CopyFromReg, 159 160 // UNDEF - An undefined node 161 UNDEF, 162 163 // EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 164 // a Constant, which is required to be operand #1) half of the integer or 165 // float value specified as operand #0. This is only for use before 166 // legalization, for values that will be broken into multiple registers. 167 EXTRACT_ELEMENT, 168 169 // BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. Given 170 // two values of the same integer value type, this produces a value twice as 171 // big. Like EXTRACT_ELEMENT, this can only be used before legalization. 172 BUILD_PAIR, 173 174 // MERGE_VALUES - This node takes multiple discrete operands and returns 175 // them all as its individual results. This nodes has exactly the same 176 // number of inputs and outputs. This node is useful for some pieces of the 177 // code generator that want to think about a single node with multiple 178 // results, not multiple nodes. 179 MERGE_VALUES, 180 181 // Simple integer binary arithmetic operators. 182 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, 183 184 // SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 185 // a signed/unsigned value of type i[2*N], and return the full value as 186 // two results, each of type iN. 187 SMUL_LOHI, UMUL_LOHI, 188 189 // SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 190 // remainder result. 191 SDIVREM, UDIVREM, 192 193 // CARRY_FALSE - This node is used when folding other nodes, 194 // like ADDC/SUBC, which indicate the carry result is always false. 195 CARRY_FALSE, 196 197 // Carry-setting nodes for multiple precision addition and subtraction. 198 // These nodes take two operands of the same value type, and produce two 199 // results. The first result is the normal add or sub result, the second 200 // result is the carry flag result. 201 ADDC, SUBC, 202 203 // Carry-using nodes for multiple precision addition and subtraction. These 204 // nodes take three operands: The first two are the normal lhs and rhs to 205 // the add or sub, and the third is the input carry flag. These nodes 206 // produce two results; the normal result of the add or sub, and the output 207 // carry flag. These nodes both read and write a carry flag to allow them 208 // to them to be chained together for add and sub of arbitrarily large 209 // values. 210 ADDE, SUBE, 211 212 // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 213 // These nodes take two operands: the normal LHS and RHS to the add. They 214 // produce two results: the normal result of the add, and a boolean that 215 // indicates if an overflow occurred (*not* a flag, because it may be stored 216 // to memory, etc.). If the type of the boolean is not i1 then the high 217 // bits conform to getBooleanContents. 218 // These nodes are generated from the llvm.[su]add.with.overflow intrinsics. 219 SADDO, UADDO, 220 221 // Same for subtraction 222 SSUBO, USUBO, 223 224 // Same for multiplication 225 SMULO, UMULO, 226 227 // Simple binary floating point operators. 228 FADD, FSUB, FMUL, FMA, FDIV, FREM, 229 230 // FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 231 // DAG node does not require that X and Y have the same type, just that they 232 // are both floating point. X and the result must have the same type. 233 // FCOPYSIGN(f32, f64) is allowed. 234 FCOPYSIGN, 235 236 // INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 237 // value as an integer 0/1 value. 238 FGETSIGN, 239 240 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the 241 /// specified, possibly variable, elements. The number of elements is 242 /// required to be a power of two. The types of the operands must all be 243 /// the same and must match the vector element type, except that integer 244 /// types are allowed to be larger than the element type, in which case 245 /// the operands are implicitly truncated. 246 BUILD_VECTOR, 247 248 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 249 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 250 /// element type then VAL is truncated before replacement. 251 INSERT_VECTOR_ELT, 252 253 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 254 /// identified by the (potentially variable) element number IDX. If the 255 /// return type is an integer type larger than the element type of the 256 /// vector, the result is extended to the width of the return type. 257 EXTRACT_VECTOR_ELT, 258 259 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 260 /// vector type with the same length and element type, this produces a 261 /// concatenated vector result value, with length equal to the sum of the 262 /// lengths of the input vectors. 263 CONCAT_VECTORS, 264 265 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector 266 /// with VECTOR2 inserted into VECTOR1 at the (potentially 267 /// variable) element number IDX, which must be a multiple of the 268 /// VECTOR2 vector length. The elements of VECTOR1 starting at 269 /// IDX are overwritten with VECTOR2. Elements IDX through 270 /// vector_length(VECTOR2) must be valid VECTOR1 indices. 271 INSERT_SUBVECTOR, 272 273 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 274 /// vector value) starting with the element number IDX, which must be a 275 /// constant multiple of the result vector length. 276 EXTRACT_SUBVECTOR, 277 278 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 279 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 280 /// values that indicate which value (or undef) each result element will 281 /// get. These constant ints are accessible through the 282 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 283 /// 'vperm' instruction, except that the indices must be constants and are 284 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 285 VECTOR_SHUFFLE, 286 287 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 288 /// scalar value into element 0 of the resultant vector type. The top 289 /// elements 1 to N-1 of the N-element vector are undefined. The type 290 /// of the operand must match the vector element type, except when they 291 /// are integer types. In this case the operand is allowed to be wider 292 /// than the vector element type, and is implicitly truncated to it. 293 SCALAR_TO_VECTOR, 294 295 // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing 296 // an unsigned/signed value of type i[2*N], then return the top part. 297 MULHU, MULHS, 298 299 /// Bitwise operators - logical and, logical or, logical xor. 300 AND, OR, XOR, 301 302 /// Shift and rotation operations. After legalization, the type of the 303 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 304 /// the shift amount can be any type, but care must be taken to ensure it is 305 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 306 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 307 /// to represent the shift amount. By convention, DAGCombine and 308 /// SelectionDAGBuilder forces these shift amounts to i32 for simplicity. 309 /// 310 SHL, SRA, SRL, ROTL, ROTR, 311 312 /// Byte Swap and Counting operators. 313 BSWAP, CTTZ, CTLZ, CTPOP, 314 315 /// Bit counting operators with an undefined result for zero inputs. 316 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, 317 318 // Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 319 // i1 then the high bits must conform to getBooleanContents. 320 SELECT, 321 322 // Select with a vector condition (op #0) and two vector operands (ops #1 323 // and #2), returning a vector result. All vectors have the same length. 324 // Much like the scalar select and setcc, each bit in the condition selects 325 // whether the corresponding result element is taken from op #1 or op #2. 326 // At first, the VSELECT condition is of vXi1 type. Later, targets may change 327 // the condition type in order to match the VSELECT node using a a pattern. 328 // The condition follows the BooleanContent format of the target. 329 VSELECT, 330 331 // Select with condition operator - This selects between a true value and 332 // a false value (ops #2 and #3) based on the boolean result of comparing 333 // the lhs and rhs (ops #0 and #1) of a conditional expression with the 334 // condition code in op #4, a CondCodeSDNode. 335 SELECT_CC, 336 337 // SetCC operator - This evaluates to a true value iff the condition is 338 // true. If the result value type is not i1 then the high bits conform 339 // to getBooleanContents. The operands to this are the left and right 340 // operands to compare (ops #0, and #1) and the condition code to compare 341 // them with (op #2) as a CondCodeSDNode. If the operands are vector types 342 // then the result type must also be a vector type. 343 SETCC, 344 345 // SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 346 // integer shift operations, just like ADD/SUB_PARTS. The operation 347 // ordering is: 348 // [Lo,Hi] = op [LoLHS,HiLHS], Amt 349 SHL_PARTS, SRA_PARTS, SRL_PARTS, 350 351 // Conversion operators. These are all single input single output 352 // operations. For all of these, the result type must be strictly 353 // wider or narrower (depending on the operation) than the source 354 // type. 355 356 // SIGN_EXTEND - Used for integer types, replicating the sign bit 357 // into new bits. 358 SIGN_EXTEND, 359 360 // ZERO_EXTEND - Used for integer types, zeroing the new bits. 361 ZERO_EXTEND, 362 363 // ANY_EXTEND - Used for integer types. The high bits are undefined. 364 ANY_EXTEND, 365 366 // TRUNCATE - Completely drop the high bits. 367 TRUNCATE, 368 369 // [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 370 // depends on the first letter) to floating point. 371 SINT_TO_FP, 372 UINT_TO_FP, 373 374 // SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 375 // sign extend a small value in a large integer register (e.g. sign 376 // extending the low 8 bits of a 32-bit register to fill the top 24 bits 377 // with the 7th bit). The size of the smaller type is indicated by the 1th 378 // operand, a ValueType node. 379 SIGN_EXTEND_INREG, 380 381 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 382 /// integer. 383 FP_TO_SINT, 384 FP_TO_UINT, 385 386 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 387 /// down to the precision of the destination VT. TRUNC is a flag, which is 388 /// always an integer that is zero or one. If TRUNC is 0, this is a 389 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 390 /// value of Y. 391 /// 392 /// The TRUNC = 1 case is used in cases where we know that the value will 393 /// not be modified by the node, because Y is not using any of the extra 394 /// precision of source type. This allows certain transformations like 395 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 396 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 397 FP_ROUND, 398 399 // FLT_ROUNDS_ - Returns current rounding mode: 400 // -1 Undefined 401 // 0 Round to 0 402 // 1 Round to nearest 403 // 2 Round to +inf 404 // 3 Round to -inf 405 FLT_ROUNDS_, 406 407 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and 408 /// rounds it to a floating point value. It then promotes it and returns it 409 /// in a register of the same size. This operation effectively just 410 /// discards excess precision. The type to round down to is specified by 411 /// the VT operand, a VTSDNode. 412 FP_ROUND_INREG, 413 414 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 415 FP_EXTEND, 416 417 // BITCAST - This operator converts between integer, vector and FP 418 // values, as if the value was stored to memory with one type and loaded 419 // from the same address with the other type (or equivalently for vector 420 // format conversions, etc). The source and result are required to have 421 // the same bit size (e.g. f32 <-> i32). This can also be used for 422 // int-to-int or fp-to-fp conversions, but that is a noop, deleted by 423 // getNode(). 424 BITCAST, 425 426 // CONVERT_RNDSAT - This operator is used to support various conversions 427 // between various types (float, signed, unsigned and vectors of those 428 // types) with rounding and saturation. NOTE: Avoid using this operator as 429 // most target don't support it and the operator might be removed in the 430 // future. It takes the following arguments: 431 // 0) value 432 // 1) dest type (type to convert to) 433 // 2) src type (type to convert from) 434 // 3) rounding imm 435 // 4) saturation imm 436 // 5) ISD::CvtCode indicating the type of conversion to do 437 CONVERT_RNDSAT, 438 439 // FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform 440 // promotions and truncation for half-precision (16 bit) floating 441 // numbers. We need special nodes since FP16 is a storage-only type with 442 // special semantics of operations. 443 FP16_TO_FP32, FP32_TO_FP16, 444 445 // FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 446 // FLOG, FLOG2, FLOG10, FEXP, FEXP2, 447 // FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary floating 448 // point operations. These are inspired by libm. 449 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 450 FLOG, FLOG2, FLOG10, FEXP, FEXP2, 451 FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, 452 453 // LOAD and STORE have token chains as their first operand, then the same 454 // operands as an LLVM load/store instruction, then an offset node that 455 // is added / subtracted from the base pointer to form the address (for 456 // indexed memory ops). 457 LOAD, STORE, 458 459 // DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 460 // to a specified boundary. This node always has two return values: a new 461 // stack pointer value and a chain. The first operand is the token chain, 462 // the second is the number of bytes to allocate, and the third is the 463 // alignment boundary. The size is guaranteed to be a multiple of the stack 464 // alignment, and the alignment is guaranteed to be bigger than the stack 465 // alignment (if required) or 0 to get standard stack alignment. 466 DYNAMIC_STACKALLOC, 467 468 // Control flow instructions. These all have token chains. 469 470 // BR - Unconditional branch. The first operand is the chain 471 // operand, the second is the MBB to branch to. 472 BR, 473 474 // BRIND - Indirect branch. The first operand is the chain, the second 475 // is the value to branch to, which must be of the same type as the target's 476 // pointer type. 477 BRIND, 478 479 // BR_JT - Jumptable branch. The first operand is the chain, the second 480 // is the jumptable index, the last one is the jumptable entry index. 481 BR_JT, 482 483 // BRCOND - Conditional branch. The first operand is the chain, the 484 // second is the condition, the third is the block to branch to if the 485 // condition is true. If the type of the condition is not i1, then the 486 // high bits must conform to getBooleanContents. 487 BRCOND, 488 489 // BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 490 // that the condition is represented as condition code, and two nodes to 491 // compare, rather than as a combined SetCC node. The operands in order are 492 // chain, cc, lhs, rhs, block to branch to if condition is true. 493 BR_CC, 494 495 // INLINEASM - Represents an inline asm block. This node always has two 496 // return values: a chain and a flag result. The inputs are as follows: 497 // Operand #0 : Input chain. 498 // Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 499 // Operand #2 : a MDNodeSDNode with the !srcloc metadata. 500 // Operand #3 : HasSideEffect, IsAlignStack bits. 501 // After this, it is followed by a list of operands with this format: 502 // ConstantSDNode: Flags that encode whether it is a mem or not, the 503 // of operands that follow, etc. See InlineAsm.h. 504 // ... however many operands ... 505 // Operand #last: Optional, an incoming flag. 506 // 507 // The variable width operands are required to represent target addressing 508 // modes as a single "operand", even though they may have multiple 509 // SDOperands. 510 INLINEASM, 511 512 // EH_LABEL - Represents a label in mid basic block used to track 513 // locations needed for debug and exception handling tables. These nodes 514 // take a chain as input and return a chain. 515 EH_LABEL, 516 517 // STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 518 // value, the same type as the pointer type for the system, and an output 519 // chain. 520 STACKSAVE, 521 522 // STACKRESTORE has two operands, an input chain and a pointer to restore to 523 // it returns an output chain. 524 STACKRESTORE, 525 526 // CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of 527 // a call sequence, and carry arbitrary information that target might want 528 // to know. The first operand is a chain, the rest are specified by the 529 // target and not touched by the DAG optimizers. 530 // CALLSEQ_START..CALLSEQ_END pairs may not be nested. 531 CALLSEQ_START, // Beginning of a call sequence 532 CALLSEQ_END, // End of a call sequence 533 534 // VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 535 // and the alignment. It returns a pair of values: the vaarg value and a 536 // new chain. 537 VAARG, 538 539 // VACOPY - VACOPY has five operands: an input chain, a destination pointer, 540 // a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 541 // source. 542 VACOPY, 543 544 // VAEND, VASTART - VAEND and VASTART have three operands: an input chain, a 545 // pointer, and a SRCVALUE. 546 VAEND, VASTART, 547 548 // SRCVALUE - This is a node type that holds a Value* that is used to 549 // make reference to a value in the LLVM IR. 550 SRCVALUE, 551 552 // MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 553 // reference metadata in the IR. 554 MDNODE_SDNODE, 555 556 // PCMARKER - This corresponds to the pcmarker intrinsic. 557 PCMARKER, 558 559 // READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 560 // The only operand is a chain and a value and a chain are produced. The 561 // value is the contents of the architecture specific cycle counter like 562 // register (or other high accuracy low latency clock source) 563 READCYCLECOUNTER, 564 565 // HANDLENODE node - Used as a handle for various purposes. 566 HANDLENODE, 567 568 // INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 569 // takes as input a token chain, the pointer to the trampoline, the pointer 570 // to the nested function, the pointer to pass for the 'nest' parameter, a 571 // SRCVALUE for the trampoline and another for the nested function (allowing 572 // targets to access the original Function*). It produces a token chain as 573 // output. 574 INIT_TRAMPOLINE, 575 576 // ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 577 // It takes a pointer to the trampoline and produces a (possibly) new 578 // pointer to the same trampoline with platform-specific adjustments 579 // applied. The pointer it returns points to an executable block of code. 580 ADJUST_TRAMPOLINE, 581 582 // TRAP - Trapping instruction 583 TRAP, 584 585 // PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are 586 // their first operand. The other operands are the address to prefetch, 587 // read / write specifier, locality specifier and instruction / data cache 588 // specifier. 589 PREFETCH, 590 591 // OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load, 592 // store-store, device) 593 // This corresponds to the memory.barrier intrinsic. 594 // it takes an input chain, 4 operands to specify the type of barrier, an 595 // operand specifying if the barrier applies to device and uncached memory 596 // and produces an output chain. 597 MEMBARRIER, 598 599 // OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 600 // This corresponds to the fence instruction. It takes an input chain, and 601 // two integer constants: an AtomicOrdering and a SynchronizationScope. 602 ATOMIC_FENCE, 603 604 // Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 605 // This corresponds to "load atomic" instruction. 606 ATOMIC_LOAD, 607 608 // OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val) 609 // This corresponds to "store atomic" instruction. 610 ATOMIC_STORE, 611 612 // Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 613 // This corresponds to the cmpxchg instruction. 614 ATOMIC_CMP_SWAP, 615 616 // Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 617 // Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 618 // These correspond to the atomicrmw instruction. 619 ATOMIC_SWAP, 620 ATOMIC_LOAD_ADD, 621 ATOMIC_LOAD_SUB, 622 ATOMIC_LOAD_AND, 623 ATOMIC_LOAD_OR, 624 ATOMIC_LOAD_XOR, 625 ATOMIC_LOAD_NAND, 626 ATOMIC_LOAD_MIN, 627 ATOMIC_LOAD_MAX, 628 ATOMIC_LOAD_UMIN, 629 ATOMIC_LOAD_UMAX, 630 631 /// BUILTIN_OP_END - This must be the last enum value in this list. 632 /// The target-specific pre-isel opcode values start here. 633 BUILTIN_OP_END 634 }; 635 636 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations 637 /// which do not reference a specific memory location should be less than 638 /// this value. Those that do must not be less than this value, and can 639 /// be used with SelectionDAG::getMemIntrinsicNode. 640 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+150; 641 642 //===--------------------------------------------------------------------===// 643 /// MemIndexedMode enum - This enum defines the load / store indexed 644 /// addressing modes. 645 /// 646 /// UNINDEXED "Normal" load / store. The effective address is already 647 /// computed and is available in the base pointer. The offset 648 /// operand is always undefined. In addition to producing a 649 /// chain, an unindexed load produces one value (result of the 650 /// load); an unindexed store does not produce a value. 651 /// 652 /// PRE_INC Similar to the unindexed mode where the effective address is 653 /// PRE_DEC the value of the base pointer add / subtract the offset. 654 /// It considers the computation as being folded into the load / 655 /// store operation (i.e. the load / store does the address 656 /// computation as well as performing the memory transaction). 657 /// The base operand is always undefined. In addition to 658 /// producing a chain, pre-indexed load produces two values 659 /// (result of the load and the result of the address 660 /// computation); a pre-indexed store produces one value (result 661 /// of the address computation). 662 /// 663 /// POST_INC The effective address is the value of the base pointer. The 664 /// POST_DEC value of the offset operand is then added to / subtracted 665 /// from the base after memory transaction. In addition to 666 /// producing a chain, post-indexed load produces two values 667 /// (the result of the load and the result of the base +/- offset 668 /// computation); a post-indexed store produces one value (the 669 /// the result of the base +/- offset computation). 670 enum MemIndexedMode { 671 UNINDEXED = 0, 672 PRE_INC, 673 PRE_DEC, 674 POST_INC, 675 POST_DEC, 676 LAST_INDEXED_MODE 677 }; 678 679 //===--------------------------------------------------------------------===// 680 /// LoadExtType enum - This enum defines the three variants of LOADEXT 681 /// (load with extension). 682 /// 683 /// SEXTLOAD loads the integer operand and sign extends it to a larger 684 /// integer result type. 685 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 686 /// integer result type. 687 /// EXTLOAD is used for two things: floating point extending loads and 688 /// integer extending loads [the top bits are undefined]. 689 enum LoadExtType { 690 NON_EXTLOAD = 0, 691 EXTLOAD, 692 SEXTLOAD, 693 ZEXTLOAD, 694 LAST_LOADEXT_TYPE 695 }; 696 697 //===--------------------------------------------------------------------===// 698 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 699 /// below work out, when considering SETFALSE (something that never exists 700 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 701 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 702 /// to. If the "N" column is 1, the result of the comparison is undefined if 703 /// the input is a NAN. 704 /// 705 /// All of these (except for the 'always folded ops') should be handled for 706 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 707 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 708 /// 709 /// Note that these are laid out in a specific order to allow bit-twiddling 710 /// to transform conditions. 711 enum CondCode { 712 // Opcode N U L G E Intuitive operation 713 SETFALSE, // 0 0 0 0 Always false (always folded) 714 SETOEQ, // 0 0 0 1 True if ordered and equal 715 SETOGT, // 0 0 1 0 True if ordered and greater than 716 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 717 SETOLT, // 0 1 0 0 True if ordered and less than 718 SETOLE, // 0 1 0 1 True if ordered and less than or equal 719 SETONE, // 0 1 1 0 True if ordered and operands are unequal 720 SETO, // 0 1 1 1 True if ordered (no nans) 721 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 722 SETUEQ, // 1 0 0 1 True if unordered or equal 723 SETUGT, // 1 0 1 0 True if unordered or greater than 724 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 725 SETULT, // 1 1 0 0 True if unordered or less than 726 SETULE, // 1 1 0 1 True if unordered, less than, or equal 727 SETUNE, // 1 1 1 0 True if unordered or not equal 728 SETTRUE, // 1 1 1 1 Always true (always folded) 729 // Don't care operations: undefined if the input is a nan. 730 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 731 SETEQ, // 1 X 0 0 1 True if equal 732 SETGT, // 1 X 0 1 0 True if greater than 733 SETGE, // 1 X 0 1 1 True if greater than or equal 734 SETLT, // 1 X 1 0 0 True if less than 735 SETLE, // 1 X 1 0 1 True if less than or equal 736 SETNE, // 1 X 1 1 0 True if not equal 737 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 738 739 SETCC_INVALID // Marker value. 740 }; 741 742 /// isSignedIntSetCC - Return true if this is a setcc instruction that 743 /// performs a signed comparison when used with integer operands. 744 inline bool isSignedIntSetCC(CondCode Code) { 745 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 746 } 747 748 /// isUnsignedIntSetCC - Return true if this is a setcc instruction that 749 /// performs an unsigned comparison when used with integer operands. 750 inline bool isUnsignedIntSetCC(CondCode Code) { 751 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 752 } 753 754 /// isTrueWhenEqual - Return true if the specified condition returns true if 755 /// the two operands to the condition are equal. Note that if one of the two 756 /// operands is a NaN, this value is meaningless. 757 inline bool isTrueWhenEqual(CondCode Cond) { 758 return ((int)Cond & 1) != 0; 759 } 760 761 /// getUnorderedFlavor - This function returns 0 if the condition is always 762 /// false if an operand is a NaN, 1 if the condition is always true if the 763 /// operand is a NaN, and 2 if the condition is undefined if the operand is a 764 /// NaN. 765 inline unsigned getUnorderedFlavor(CondCode Cond) { 766 return ((int)Cond >> 3) & 3; 767 } 768 769 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where 770 /// 'op' is a valid SetCC operation. 771 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 772 773 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 774 /// when given the operation for (X op Y). 775 CondCode getSetCCSwappedOperands(CondCode Operation); 776 777 /// getSetCCOrOperation - Return the result of a logical OR between different 778 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This 779 /// function returns SETCC_INVALID if it is not possible to represent the 780 /// resultant comparison. 781 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 782 783 /// getSetCCAndOperation - Return the result of a logical AND between 784 /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 785 /// function returns SETCC_INVALID if it is not possible to represent the 786 /// resultant comparison. 787 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); 788 789 //===--------------------------------------------------------------------===// 790 /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT 791 /// supports. 792 enum CvtCode { 793 CVT_FF, // Float from Float 794 CVT_FS, // Float from Signed 795 CVT_FU, // Float from Unsigned 796 CVT_SF, // Signed from Float 797 CVT_UF, // Unsigned from Float 798 CVT_SS, // Signed from Signed 799 CVT_SU, // Signed from Unsigned 800 CVT_US, // Unsigned from Signed 801 CVT_UU, // Unsigned from Unsigned 802 CVT_INVALID // Marker - Invalid opcode 803 }; 804 805 } // end llvm::ISD namespace 806 807 } // end llvm namespace 808 809 #endif 810
