| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 52 // AssertSext, AssertZext - These nodes record if a register contains a
57 AssertSext, AssertZext,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 79 case ISD::AssertSext: return "AssertSext";
|
| LegalizeIntegerTypes.cpp | 51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
156 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
371 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
[all...] |
| SelectionDAGBuilder.cpp | 96 /// (ISD::AssertSext).
215 /// (ISD::AssertSext).
694 // now, just use the tightest assertzext/assertsext possible.
718 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
[all...] |
| SelectionDAGISel.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | 738 case ISD::AssertSext:
739 return DAG.getNode(ISD::AssertSext, dl, PVT,
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 342 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 217 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
