1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the interfaces that Sparc uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "SparcISelLowering.h" 16 #include "SparcTargetMachine.h" 17 #include "SparcMachineFunctionInfo.h" 18 #include "llvm/DerivedTypes.h" 19 #include "llvm/Function.h" 20 #include "llvm/Module.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 #include "llvm/CodeGen/MachineFrameInfo.h" 23 #include "llvm/CodeGen/MachineFunction.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineRegisterInfo.h" 26 #include "llvm/CodeGen/SelectionDAG.h" 27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 28 #include "llvm/Support/ErrorHandling.h" 29 using namespace llvm; 30 31 32 //===----------------------------------------------------------------------===// 33 // Calling Convention Implementation 34 //===----------------------------------------------------------------------===// 35 36 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, 37 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 38 ISD::ArgFlagsTy &ArgFlags, CCState &State) 39 { 40 assert (ArgFlags.isSRet()); 41 42 //Assign SRet argument 43 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 44 0, 45 LocVT, LocInfo)); 46 return true; 47 } 48 49 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, 50 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 51 ISD::ArgFlagsTy &ArgFlags, CCState &State) 52 { 53 static const uint16_t RegList[] = { 54 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 55 }; 56 //Try to get first reg 57 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 58 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 59 } else { 60 //Assign whole thing in stack 61 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 62 State.AllocateStack(8,4), 63 LocVT, LocInfo)); 64 return true; 65 } 66 67 //Try to get second reg 68 if (unsigned Reg = State.AllocateReg(RegList, 6)) 69 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 70 else 71 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 72 State.AllocateStack(4,4), 73 LocVT, LocInfo)); 74 return true; 75 } 76 77 #include "SparcGenCallingConv.inc" 78 79 SDValue 80 SparcTargetLowering::LowerReturn(SDValue Chain, 81 CallingConv::ID CallConv, bool isVarArg, 82 const SmallVectorImpl<ISD::OutputArg> &Outs, 83 const SmallVectorImpl<SDValue> &OutVals, 84 DebugLoc dl, SelectionDAG &DAG) const { 85 86 MachineFunction &MF = DAG.getMachineFunction(); 87 88 // CCValAssign - represent the assignment of the return value to locations. 89 SmallVector<CCValAssign, 16> RVLocs; 90 91 // CCState - Info about the registers and stack slot. 92 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 93 DAG.getTarget(), RVLocs, *DAG.getContext()); 94 95 // Analize return values. 96 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 97 98 // If this is the first return lowered for this function, add the regs to the 99 // liveout set for the function. 100 if (MF.getRegInfo().liveout_empty()) { 101 for (unsigned i = 0; i != RVLocs.size(); ++i) 102 if (RVLocs[i].isRegLoc()) 103 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 104 } 105 106 SDValue Flag; 107 108 // Copy the result values into the output registers. 109 for (unsigned i = 0; i != RVLocs.size(); ++i) { 110 CCValAssign &VA = RVLocs[i]; 111 assert(VA.isRegLoc() && "Can only return in registers!"); 112 113 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 114 OutVals[i], Flag); 115 116 // Guarantee that all emitted copies are stuck together with flags. 117 Flag = Chain.getValue(1); 118 } 119 120 unsigned RetAddrOffset = 8; //Call Inst + Delay Slot 121 // If the function returns a struct, copy the SRetReturnReg to I0 122 if (MF.getFunction()->hasStructRetAttr()) { 123 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 124 unsigned Reg = SFI->getSRetReturnReg(); 125 if (!Reg) 126 llvm_unreachable("sret virtual register not created in the entry block"); 127 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 128 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag); 129 Flag = Chain.getValue(1); 130 if (MF.getRegInfo().liveout_empty()) 131 MF.getRegInfo().addLiveOut(SP::I0); 132 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp 133 } 134 135 SDValue RetAddrOffsetNode = DAG.getConstant(RetAddrOffset, MVT::i32); 136 137 if (Flag.getNode()) 138 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, 139 RetAddrOffsetNode, Flag); 140 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, 141 RetAddrOffsetNode); 142 } 143 144 /// LowerFormalArguments - V8 uses a very simple ABI, where all values are 145 /// passed in either one or two GPRs, including FP values. TODO: we should 146 /// pass FP values in FP registers for fastcc functions. 147 SDValue 148 SparcTargetLowering::LowerFormalArguments(SDValue Chain, 149 CallingConv::ID CallConv, bool isVarArg, 150 const SmallVectorImpl<ISD::InputArg> 151 &Ins, 152 DebugLoc dl, SelectionDAG &DAG, 153 SmallVectorImpl<SDValue> &InVals) 154 const { 155 156 MachineFunction &MF = DAG.getMachineFunction(); 157 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 158 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 159 160 // Assign locations to all of the incoming arguments. 161 SmallVector<CCValAssign, 16> ArgLocs; 162 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 163 getTargetMachine(), ArgLocs, *DAG.getContext()); 164 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); 165 166 const unsigned StackOffset = 92; 167 168 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 169 CCValAssign &VA = ArgLocs[i]; 170 171 if (i == 0 && Ins[i].Flags.isSRet()) { 172 //Get SRet from [%fp+64] 173 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true); 174 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 175 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 176 MachinePointerInfo(), 177 false, false, false, 0); 178 InVals.push_back(Arg); 179 continue; 180 } 181 182 if (VA.isRegLoc()) { 183 if (VA.needsCustom()) { 184 assert(VA.getLocVT() == MVT::f64); 185 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 186 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); 187 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); 188 189 assert(i+1 < e); 190 CCValAssign &NextVA = ArgLocs[++i]; 191 192 SDValue LoVal; 193 if (NextVA.isMemLoc()) { 194 int FrameIdx = MF.getFrameInfo()-> 195 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); 196 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 197 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 198 MachinePointerInfo(), 199 false, false, false, 0); 200 } else { 201 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), 202 &SP::IntRegsRegClass); 203 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); 204 } 205 SDValue WholeValue = 206 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 207 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 208 InVals.push_back(WholeValue); 209 continue; 210 } 211 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 212 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 213 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 214 if (VA.getLocVT() == MVT::f32) 215 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 216 else if (VA.getLocVT() != MVT::i32) { 217 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 218 DAG.getValueType(VA.getLocVT())); 219 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); 220 } 221 InVals.push_back(Arg); 222 continue; 223 } 224 225 assert(VA.isMemLoc()); 226 227 unsigned Offset = VA.getLocMemOffset()+StackOffset; 228 229 if (VA.needsCustom()) { 230 assert(VA.getValVT() == MVT::f64); 231 //If it is double-word aligned, just load. 232 if (Offset % 8 == 0) { 233 int FI = MF.getFrameInfo()->CreateFixedObject(8, 234 Offset, 235 true); 236 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 237 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 238 MachinePointerInfo(), 239 false,false, false, 0); 240 InVals.push_back(Load); 241 continue; 242 } 243 244 int FI = MF.getFrameInfo()->CreateFixedObject(4, 245 Offset, 246 true); 247 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 248 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 249 MachinePointerInfo(), 250 false, false, false, 0); 251 int FI2 = MF.getFrameInfo()->CreateFixedObject(4, 252 Offset+4, 253 true); 254 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy()); 255 256 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, 257 MachinePointerInfo(), 258 false, false, false, 0); 259 260 SDValue WholeValue = 261 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 262 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 263 InVals.push_back(WholeValue); 264 continue; 265 } 266 267 int FI = MF.getFrameInfo()->CreateFixedObject(4, 268 Offset, 269 true); 270 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 271 SDValue Load ; 272 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { 273 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 274 MachinePointerInfo(), 275 false, false, false, 0); 276 } else { 277 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 278 // Sparc is big endian, so add an offset based on the ObjectVT. 279 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); 280 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, 281 DAG.getConstant(Offset, MVT::i32)); 282 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, 283 MachinePointerInfo(), 284 VA.getValVT(), false, false,0); 285 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); 286 } 287 InVals.push_back(Load); 288 } 289 290 if (MF.getFunction()->hasStructRetAttr()) { 291 //Copy the SRet Argument to SRetReturnReg 292 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 293 unsigned Reg = SFI->getSRetReturnReg(); 294 if (!Reg) { 295 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); 296 SFI->setSRetReturnReg(Reg); 297 } 298 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 299 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 300 } 301 302 // Store remaining ArgRegs to the stack if this is a varargs function. 303 if (isVarArg) { 304 static const uint16_t ArgRegs[] = { 305 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 306 }; 307 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); 308 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; 309 unsigned ArgOffset = CCInfo.getNextStackOffset(); 310 if (NumAllocated == 6) 311 ArgOffset += StackOffset; 312 else { 313 assert(!ArgOffset); 314 ArgOffset = 68+4*NumAllocated; 315 } 316 317 // Remember the vararg offset for the va_start implementation. 318 FuncInfo->setVarArgsFrameOffset(ArgOffset); 319 320 std::vector<SDValue> OutChains; 321 322 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 323 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 324 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 325 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); 326 327 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 328 true); 329 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 330 331 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, 332 MachinePointerInfo(), 333 false, false, 0)); 334 ArgOffset += 4; 335 } 336 337 if (!OutChains.empty()) { 338 OutChains.push_back(Chain); 339 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 340 &OutChains[0], OutChains.size()); 341 } 342 } 343 344 return Chain; 345 } 346 347 SDValue 348 SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 349 CallingConv::ID CallConv, bool isVarArg, 350 bool doesNotRet, bool &isTailCall, 351 const SmallVectorImpl<ISD::OutputArg> &Outs, 352 const SmallVectorImpl<SDValue> &OutVals, 353 const SmallVectorImpl<ISD::InputArg> &Ins, 354 DebugLoc dl, SelectionDAG &DAG, 355 SmallVectorImpl<SDValue> &InVals) const { 356 // Sparc target does not yet support tail call optimization. 357 isTailCall = false; 358 359 // Analyze operands of the call, assigning locations to each operand. 360 SmallVector<CCValAssign, 16> ArgLocs; 361 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 362 DAG.getTarget(), ArgLocs, *DAG.getContext()); 363 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); 364 365 // Get the size of the outgoing arguments stack space requirement. 366 unsigned ArgsSize = CCInfo.getNextStackOffset(); 367 368 // Keep stack frames 8-byte aligned. 369 ArgsSize = (ArgsSize+7) & ~7; 370 371 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 372 373 //Create local copies for byval args. 374 SmallVector<SDValue, 8> ByValArgs; 375 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 376 ISD::ArgFlagsTy Flags = Outs[i].Flags; 377 if (!Flags.isByVal()) 378 continue; 379 380 SDValue Arg = OutVals[i]; 381 unsigned Size = Flags.getByValSize(); 382 unsigned Align = Flags.getByValAlign(); 383 384 int FI = MFI->CreateStackObject(Size, Align, false); 385 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 386 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); 387 388 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, 389 false, //isVolatile, 390 (Size <= 32), //AlwaysInline if size <= 32 391 MachinePointerInfo(), MachinePointerInfo()); 392 ByValArgs.push_back(FIPtr); 393 } 394 395 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true)); 396 397 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 398 SmallVector<SDValue, 8> MemOpChains; 399 400 const unsigned StackOffset = 92; 401 bool hasStructRetAttr = false; 402 // Walk the register/memloc assignments, inserting copies/loads. 403 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size(); 404 i != e; 405 ++i, ++realArgIdx) { 406 CCValAssign &VA = ArgLocs[i]; 407 SDValue Arg = OutVals[realArgIdx]; 408 409 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 410 411 //Use local copy if it is a byval arg. 412 if (Flags.isByVal()) 413 Arg = ByValArgs[byvalArgIdx++]; 414 415 // Promote the value if needed. 416 switch (VA.getLocInfo()) { 417 default: llvm_unreachable("Unknown loc info!"); 418 case CCValAssign::Full: break; 419 case CCValAssign::SExt: 420 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 421 break; 422 case CCValAssign::ZExt: 423 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 424 break; 425 case CCValAssign::AExt: 426 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 427 break; 428 case CCValAssign::BCvt: 429 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 430 break; 431 } 432 433 if (Flags.isSRet()) { 434 assert(VA.needsCustom()); 435 // store SRet argument in %sp+64 436 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 437 SDValue PtrOff = DAG.getIntPtrConstant(64); 438 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 439 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 440 MachinePointerInfo(), 441 false, false, 0)); 442 hasStructRetAttr = true; 443 continue; 444 } 445 446 if (VA.needsCustom()) { 447 assert(VA.getLocVT() == MVT::f64); 448 449 if (VA.isMemLoc()) { 450 unsigned Offset = VA.getLocMemOffset() + StackOffset; 451 //if it is double-word aligned, just store. 452 if (Offset % 8 == 0) { 453 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 454 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 455 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 456 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 457 MachinePointerInfo(), 458 false, false, 0)); 459 continue; 460 } 461 } 462 463 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); 464 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 465 Arg, StackPtr, MachinePointerInfo(), 466 false, false, 0); 467 // Sparc is big-endian, so the high part comes first. 468 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 469 MachinePointerInfo(), false, false, false, 0); 470 // Increment the pointer to the other half. 471 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 472 DAG.getIntPtrConstant(4)); 473 // Load the low part. 474 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 475 MachinePointerInfo(), false, false, false, 0); 476 477 if (VA.isRegLoc()) { 478 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); 479 assert(i+1 != e); 480 CCValAssign &NextVA = ArgLocs[++i]; 481 if (NextVA.isRegLoc()) { 482 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); 483 } else { 484 //Store the low part in stack. 485 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; 486 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 487 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 488 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 489 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 490 MachinePointerInfo(), 491 false, false, 0)); 492 } 493 } else { 494 unsigned Offset = VA.getLocMemOffset() + StackOffset; 495 // Store the high part. 496 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 497 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 498 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 499 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, 500 MachinePointerInfo(), 501 false, false, 0)); 502 // Store the low part. 503 PtrOff = DAG.getIntPtrConstant(Offset+4); 504 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 505 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 506 MachinePointerInfo(), 507 false, false, 0)); 508 } 509 continue; 510 } 511 512 // Arguments that can be passed on register must be kept at 513 // RegsToPass vector 514 if (VA.isRegLoc()) { 515 if (VA.getLocVT() != MVT::f32) { 516 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 517 continue; 518 } 519 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 520 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 521 continue; 522 } 523 524 assert(VA.isMemLoc()); 525 526 // Create a store off the stack pointer for this argument. 527 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 528 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset); 529 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 530 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 531 MachinePointerInfo(), 532 false, false, 0)); 533 } 534 535 536 // Emit all stores, make sure the occur before any copies into physregs. 537 if (!MemOpChains.empty()) 538 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 539 &MemOpChains[0], MemOpChains.size()); 540 541 // Build a sequence of copy-to-reg nodes chained together with token 542 // chain and flag operands which copy the outgoing args into registers. 543 // The InFlag in necessary since all emitted instructions must be 544 // stuck together. 545 SDValue InFlag; 546 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 547 unsigned Reg = RegsToPass[i].first; 548 // Remap I0->I7 -> O0->O7. 549 if (Reg >= SP::I0 && Reg <= SP::I7) 550 Reg = Reg-SP::I0+SP::O0; 551 552 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); 553 InFlag = Chain.getValue(1); 554 } 555 556 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0; 557 558 // If the callee is a GlobalAddress node (quite common, every direct call is) 559 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 560 // Likewise ExternalSymbol -> TargetExternalSymbol. 561 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 562 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 563 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 564 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 565 566 // Returns a chain & a flag for retval copy to use 567 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 568 SmallVector<SDValue, 8> Ops; 569 Ops.push_back(Chain); 570 Ops.push_back(Callee); 571 if (hasStructRetAttr) 572 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32)); 573 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 574 unsigned Reg = RegsToPass[i].first; 575 if (Reg >= SP::I0 && Reg <= SP::I7) 576 Reg = Reg-SP::I0+SP::O0; 577 578 Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType())); 579 } 580 if (InFlag.getNode()) 581 Ops.push_back(InFlag); 582 583 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 584 InFlag = Chain.getValue(1); 585 586 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 587 DAG.getIntPtrConstant(0, true), InFlag); 588 InFlag = Chain.getValue(1); 589 590 // Assign locations to each value returned by this call. 591 SmallVector<CCValAssign, 16> RVLocs; 592 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), 593 DAG.getTarget(), RVLocs, *DAG.getContext()); 594 595 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); 596 597 // Copy all of the result registers out of their specified physreg. 598 for (unsigned i = 0; i != RVLocs.size(); ++i) { 599 unsigned Reg = RVLocs[i].getLocReg(); 600 601 // Remap I0->I7 -> O0->O7. 602 if (Reg >= SP::I0 && Reg <= SP::I7) 603 Reg = Reg-SP::I0+SP::O0; 604 605 Chain = DAG.getCopyFromReg(Chain, dl, Reg, 606 RVLocs[i].getValVT(), InFlag).getValue(1); 607 InFlag = Chain.getValue(2); 608 InVals.push_back(Chain.getValue(0)); 609 } 610 611 return Chain; 612 } 613 614 unsigned 615 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const 616 { 617 const Function *CalleeFn = 0; 618 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 619 CalleeFn = dyn_cast<Function>(G->getGlobal()); 620 } else if (ExternalSymbolSDNode *E = 621 dyn_cast<ExternalSymbolSDNode>(Callee)) { 622 const Function *Fn = DAG.getMachineFunction().getFunction(); 623 const Module *M = Fn->getParent(); 624 CalleeFn = M->getFunction(E->getSymbol()); 625 } 626 627 if (!CalleeFn) 628 return 0; 629 630 assert(CalleeFn->hasStructRetAttr() && 631 "Callee does not have the StructRet attribute."); 632 633 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType()); 634 Type *ElementTy = Ty->getElementType(); 635 return getTargetData()->getTypeAllocSize(ElementTy); 636 } 637 638 //===----------------------------------------------------------------------===// 639 // TargetLowering Implementation 640 //===----------------------------------------------------------------------===// 641 642 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 643 /// condition. 644 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 645 switch (CC) { 646 default: llvm_unreachable("Unknown integer condition code!"); 647 case ISD::SETEQ: return SPCC::ICC_E; 648 case ISD::SETNE: return SPCC::ICC_NE; 649 case ISD::SETLT: return SPCC::ICC_L; 650 case ISD::SETGT: return SPCC::ICC_G; 651 case ISD::SETLE: return SPCC::ICC_LE; 652 case ISD::SETGE: return SPCC::ICC_GE; 653 case ISD::SETULT: return SPCC::ICC_CS; 654 case ISD::SETULE: return SPCC::ICC_LEU; 655 case ISD::SETUGT: return SPCC::ICC_GU; 656 case ISD::SETUGE: return SPCC::ICC_CC; 657 } 658 } 659 660 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 661 /// FCC condition. 662 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 663 switch (CC) { 664 default: llvm_unreachable("Unknown fp condition code!"); 665 case ISD::SETEQ: 666 case ISD::SETOEQ: return SPCC::FCC_E; 667 case ISD::SETNE: 668 case ISD::SETUNE: return SPCC::FCC_NE; 669 case ISD::SETLT: 670 case ISD::SETOLT: return SPCC::FCC_L; 671 case ISD::SETGT: 672 case ISD::SETOGT: return SPCC::FCC_G; 673 case ISD::SETLE: 674 case ISD::SETOLE: return SPCC::FCC_LE; 675 case ISD::SETGE: 676 case ISD::SETOGE: return SPCC::FCC_GE; 677 case ISD::SETULT: return SPCC::FCC_UL; 678 case ISD::SETULE: return SPCC::FCC_ULE; 679 case ISD::SETUGT: return SPCC::FCC_UG; 680 case ISD::SETUGE: return SPCC::FCC_UGE; 681 case ISD::SETUO: return SPCC::FCC_U; 682 case ISD::SETO: return SPCC::FCC_O; 683 case ISD::SETONE: return SPCC::FCC_LG; 684 case ISD::SETUEQ: return SPCC::FCC_UE; 685 } 686 } 687 688 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 689 : TargetLowering(TM, new TargetLoweringObjectFileELF()) { 690 691 // Set up the register classes. 692 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 693 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 694 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 695 696 // Turn FP extload into load/fextend 697 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 698 // Sparc doesn't have i1 sign extending load 699 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 700 // Turn FP truncstore into trunc + store. 701 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 702 703 // Custom legalize GlobalAddress nodes into LO/HI parts. 704 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 705 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 706 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 707 708 // Sparc doesn't have sext_inreg, replace them with shl/sra 709 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 710 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 711 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 712 713 // Sparc has no REM or DIVREM operations. 714 setOperationAction(ISD::UREM, MVT::i32, Expand); 715 setOperationAction(ISD::SREM, MVT::i32, Expand); 716 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 717 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 718 719 // Custom expand fp<->sint 720 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 721 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 722 723 // Expand fp<->uint 724 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 725 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 726 727 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 728 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 729 730 // Sparc has no select or setcc: expand to SELECT_CC. 731 setOperationAction(ISD::SELECT, MVT::i32, Expand); 732 setOperationAction(ISD::SELECT, MVT::f32, Expand); 733 setOperationAction(ISD::SELECT, MVT::f64, Expand); 734 setOperationAction(ISD::SETCC, MVT::i32, Expand); 735 setOperationAction(ISD::SETCC, MVT::f32, Expand); 736 setOperationAction(ISD::SETCC, MVT::f64, Expand); 737 738 // Sparc doesn't have BRCOND either, it has BR_CC. 739 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 740 setOperationAction(ISD::BRIND, MVT::Other, Expand); 741 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 742 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 743 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 744 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 745 746 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 747 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 748 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 749 750 // FIXME: There are instructions available for ATOMIC_FENCE 751 // on SparcV8 and later. 752 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 753 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 754 755 setOperationAction(ISD::FSIN , MVT::f64, Expand); 756 setOperationAction(ISD::FCOS , MVT::f64, Expand); 757 setOperationAction(ISD::FREM , MVT::f64, Expand); 758 setOperationAction(ISD::FMA , MVT::f64, Expand); 759 setOperationAction(ISD::FSIN , MVT::f32, Expand); 760 setOperationAction(ISD::FCOS , MVT::f32, Expand); 761 setOperationAction(ISD::FREM , MVT::f32, Expand); 762 setOperationAction(ISD::FMA , MVT::f32, Expand); 763 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 764 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 765 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 766 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 767 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 768 setOperationAction(ISD::ROTL , MVT::i32, Expand); 769 setOperationAction(ISD::ROTR , MVT::i32, Expand); 770 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 771 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 772 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 773 setOperationAction(ISD::FPOW , MVT::f64, Expand); 774 setOperationAction(ISD::FPOW , MVT::f32, Expand); 775 776 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 777 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 778 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 779 780 // FIXME: Sparc provides these multiplies, but we don't have them yet. 781 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 782 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 783 784 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 785 786 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 787 setOperationAction(ISD::VASTART , MVT::Other, Custom); 788 // VAARG needs to be lowered to not do unaligned accesses for doubles. 789 setOperationAction(ISD::VAARG , MVT::Other, Custom); 790 791 // Use the default implementation. 792 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 793 setOperationAction(ISD::VAEND , MVT::Other, Expand); 794 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 795 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 796 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 797 798 // No debug info support yet. 799 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 800 801 setStackPointerRegisterToSaveRestore(SP::O6); 802 803 if (TM.getSubtarget<SparcSubtarget>().isV9()) 804 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 805 806 setMinFunctionAlignment(2); 807 808 computeRegisterProperties(); 809 } 810 811 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 812 switch (Opcode) { 813 default: return 0; 814 case SPISD::CMPICC: return "SPISD::CMPICC"; 815 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 816 case SPISD::BRICC: return "SPISD::BRICC"; 817 case SPISD::BRFCC: return "SPISD::BRFCC"; 818 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 819 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 820 case SPISD::Hi: return "SPISD::Hi"; 821 case SPISD::Lo: return "SPISD::Lo"; 822 case SPISD::FTOI: return "SPISD::FTOI"; 823 case SPISD::ITOF: return "SPISD::ITOF"; 824 case SPISD::CALL: return "SPISD::CALL"; 825 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 826 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; 827 case SPISD::FLUSHW: return "SPISD::FLUSHW"; 828 } 829 } 830 831 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 832 /// be zero. Op is expected to be a target specific node. Used by DAG 833 /// combiner. 834 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 835 APInt &KnownZero, 836 APInt &KnownOne, 837 const SelectionDAG &DAG, 838 unsigned Depth) const { 839 APInt KnownZero2, KnownOne2; 840 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 841 842 switch (Op.getOpcode()) { 843 default: break; 844 case SPISD::SELECT_ICC: 845 case SPISD::SELECT_FCC: 846 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); 847 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); 848 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 849 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 850 851 // Only known if known in both the LHS and RHS. 852 KnownOne &= KnownOne2; 853 KnownZero &= KnownZero2; 854 break; 855 } 856 } 857 858 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 859 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 860 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, 861 ISD::CondCode CC, unsigned &SPCC) { 862 if (isa<ConstantSDNode>(RHS) && 863 cast<ConstantSDNode>(RHS)->isNullValue() && 864 CC == ISD::SETNE && 865 ((LHS.getOpcode() == SPISD::SELECT_ICC && 866 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 867 (LHS.getOpcode() == SPISD::SELECT_FCC && 868 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 869 isa<ConstantSDNode>(LHS.getOperand(0)) && 870 isa<ConstantSDNode>(LHS.getOperand(1)) && 871 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() && 872 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) { 873 SDValue CMPCC = LHS.getOperand(3); 874 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); 875 LHS = CMPCC.getOperand(0); 876 RHS = CMPCC.getOperand(1); 877 } 878 } 879 880 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, 881 SelectionDAG &DAG) const { 882 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 883 // FIXME there isn't really any debug info here 884 DebugLoc dl = Op.getDebugLoc(); 885 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32); 886 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA); 887 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA); 888 889 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 890 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 891 892 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl, 893 getPointerTy()); 894 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 895 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, 896 GlobalBase, RelAddr); 897 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 898 AbsAddr, MachinePointerInfo(), false, false, false, 0); 899 } 900 901 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, 902 SelectionDAG &DAG) const { 903 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 904 // FIXME there isn't really any debug info here 905 DebugLoc dl = Op.getDebugLoc(); 906 const Constant *C = N->getConstVal(); 907 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); 908 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP); 909 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP); 910 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 911 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 912 913 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl, 914 getPointerTy()); 915 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 916 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, 917 GlobalBase, RelAddr); 918 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 919 AbsAddr, MachinePointerInfo(), false, false, false, 0); 920 } 921 922 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 923 DebugLoc dl = Op.getDebugLoc(); 924 // Convert the fp value to integer in an FP register. 925 assert(Op.getValueType() == MVT::i32); 926 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); 927 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 928 } 929 930 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 931 DebugLoc dl = Op.getDebugLoc(); 932 assert(Op.getOperand(0).getValueType() == MVT::i32); 933 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 934 // Convert the int value to FP in an FP register. 935 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp); 936 } 937 938 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 939 SDValue Chain = Op.getOperand(0); 940 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 941 SDValue LHS = Op.getOperand(2); 942 SDValue RHS = Op.getOperand(3); 943 SDValue Dest = Op.getOperand(4); 944 DebugLoc dl = Op.getDebugLoc(); 945 unsigned Opc, SPCC = ~0U; 946 947 // If this is a br_cc of a "setcc", and if the setcc got lowered into 948 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 949 LookThroughSetCC(LHS, RHS, CC, SPCC); 950 951 // Get the condition flag. 952 SDValue CompareFlag; 953 if (LHS.getValueType() == MVT::i32) { 954 std::vector<EVT> VTs; 955 VTs.push_back(MVT::i32); 956 VTs.push_back(MVT::Glue); 957 SDValue Ops[2] = { LHS, RHS }; 958 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 959 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 960 Opc = SPISD::BRICC; 961 } else { 962 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 963 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 964 Opc = SPISD::BRFCC; 965 } 966 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, 967 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 968 } 969 970 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 971 SDValue LHS = Op.getOperand(0); 972 SDValue RHS = Op.getOperand(1); 973 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 974 SDValue TrueVal = Op.getOperand(2); 975 SDValue FalseVal = Op.getOperand(3); 976 DebugLoc dl = Op.getDebugLoc(); 977 unsigned Opc, SPCC = ~0U; 978 979 // If this is a select_cc of a "setcc", and if the setcc got lowered into 980 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 981 LookThroughSetCC(LHS, RHS, CC, SPCC); 982 983 SDValue CompareFlag; 984 if (LHS.getValueType() == MVT::i32) { 985 std::vector<EVT> VTs; 986 VTs.push_back(LHS.getValueType()); // subcc returns a value 987 VTs.push_back(MVT::Glue); 988 SDValue Ops[2] = { LHS, RHS }; 989 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 990 Opc = SPISD::SELECT_ICC; 991 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 992 } else { 993 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 994 Opc = SPISD::SELECT_FCC; 995 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 996 } 997 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 998 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 999 } 1000 1001 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 1002 const SparcTargetLowering &TLI) { 1003 MachineFunction &MF = DAG.getMachineFunction(); 1004 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 1005 1006 // vastart just stores the address of the VarArgsFrameIndex slot into the 1007 // memory location argument. 1008 DebugLoc dl = Op.getDebugLoc(); 1009 SDValue Offset = 1010 DAG.getNode(ISD::ADD, dl, MVT::i32, 1011 DAG.getRegister(SP::I6, MVT::i32), 1012 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(), 1013 MVT::i32)); 1014 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1015 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), 1016 MachinePointerInfo(SV), false, false, 0); 1017 } 1018 1019 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { 1020 SDNode *Node = Op.getNode(); 1021 EVT VT = Node->getValueType(0); 1022 SDValue InChain = Node->getOperand(0); 1023 SDValue VAListPtr = Node->getOperand(1); 1024 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1025 DebugLoc dl = Node->getDebugLoc(); 1026 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, 1027 MachinePointerInfo(SV), false, false, false, 0); 1028 // Increment the pointer, VAList, to the next vaarg 1029 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList, 1030 DAG.getConstant(VT.getSizeInBits()/8, 1031 MVT::i32)); 1032 // Store the incremented VAList to the legalized pointer 1033 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr, 1034 VAListPtr, MachinePointerInfo(SV), false, false, 0); 1035 // Load the actual argument out of the pointer VAList, unless this is an 1036 // f64 load. 1037 if (VT != MVT::f64) 1038 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(), 1039 false, false, false, 0); 1040 1041 // Otherwise, load it as i64, then do a bitconvert. 1042 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(), 1043 false, false, false, 0); 1044 1045 // Bit-Convert the value to f64. 1046 SDValue Ops[2] = { 1047 DAG.getNode(ISD::BITCAST, dl, MVT::f64, V), 1048 V.getValue(1) 1049 }; 1050 return DAG.getMergeValues(Ops, 2, dl); 1051 } 1052 1053 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { 1054 SDValue Chain = Op.getOperand(0); // Legalize the chain. 1055 SDValue Size = Op.getOperand(1); // Legalize the size. 1056 DebugLoc dl = Op.getDebugLoc(); 1057 1058 unsigned SPReg = SP::O6; 1059 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); 1060 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value 1061 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain 1062 1063 // The resultant pointer is actually 16 words from the bottom of the stack, 1064 // to provide a register spill area. 1065 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, 1066 DAG.getConstant(96, MVT::i32)); 1067 SDValue Ops[2] = { NewVal, Chain }; 1068 return DAG.getMergeValues(Ops, 2, dl); 1069 } 1070 1071 1072 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) { 1073 DebugLoc dl = Op.getDebugLoc(); 1074 SDValue Chain = DAG.getNode(SPISD::FLUSHW, 1075 dl, MVT::Other, DAG.getEntryNode()); 1076 return Chain; 1077 } 1078 1079 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 1080 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1081 MFI->setFrameAddressIsTaken(true); 1082 1083 EVT VT = Op.getValueType(); 1084 DebugLoc dl = Op.getDebugLoc(); 1085 unsigned FrameReg = SP::I6; 1086 1087 uint64_t depth = Op.getConstantOperandVal(0); 1088 1089 SDValue FrameAddr; 1090 if (depth == 0) 1091 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 1092 else { 1093 // flush first to make sure the windowed registers' values are in stack 1094 SDValue Chain = getFLUSHW(Op, DAG); 1095 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT); 1096 1097 for (uint64_t i = 0; i != depth; ++i) { 1098 SDValue Ptr = DAG.getNode(ISD::ADD, 1099 dl, MVT::i32, 1100 FrameAddr, DAG.getIntPtrConstant(56)); 1101 FrameAddr = DAG.getLoad(MVT::i32, dl, 1102 Chain, 1103 Ptr, 1104 MachinePointerInfo(), false, false, false, 0); 1105 } 1106 } 1107 return FrameAddr; 1108 } 1109 1110 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 1111 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1112 MFI->setReturnAddressIsTaken(true); 1113 1114 EVT VT = Op.getValueType(); 1115 DebugLoc dl = Op.getDebugLoc(); 1116 unsigned RetReg = SP::I7; 1117 1118 uint64_t depth = Op.getConstantOperandVal(0); 1119 1120 SDValue RetAddr; 1121 if (depth == 0) 1122 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); 1123 else { 1124 // flush first to make sure the windowed registers' values are in stack 1125 SDValue Chain = getFLUSHW(Op, DAG); 1126 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT); 1127 1128 for (uint64_t i = 0; i != depth; ++i) { 1129 SDValue Ptr = DAG.getNode(ISD::ADD, 1130 dl, MVT::i32, 1131 RetAddr, 1132 DAG.getIntPtrConstant((i == depth-1)?60:56)); 1133 RetAddr = DAG.getLoad(MVT::i32, dl, 1134 Chain, 1135 Ptr, 1136 MachinePointerInfo(), false, false, false, 0); 1137 } 1138 } 1139 return RetAddr; 1140 } 1141 1142 SDValue SparcTargetLowering:: 1143 LowerOperation(SDValue Op, SelectionDAG &DAG) const { 1144 switch (Op.getOpcode()) { 1145 default: llvm_unreachable("Should not custom lower this!"); 1146 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 1147 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 1148 case ISD::GlobalTLSAddress: 1149 llvm_unreachable("TLS not implemented for Sparc."); 1150 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 1151 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1152 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 1153 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 1154 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 1155 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1156 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 1157 case ISD::VAARG: return LowerVAARG(Op, DAG); 1158 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 1159 } 1160 } 1161 1162 MachineBasicBlock * 1163 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1164 MachineBasicBlock *BB) const { 1165 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 1166 unsigned BROpcode; 1167 unsigned CC; 1168 DebugLoc dl = MI->getDebugLoc(); 1169 // Figure out the conditional branch opcode to use for this select_cc. 1170 switch (MI->getOpcode()) { 1171 default: llvm_unreachable("Unknown SELECT_CC!"); 1172 case SP::SELECT_CC_Int_ICC: 1173 case SP::SELECT_CC_FP_ICC: 1174 case SP::SELECT_CC_DFP_ICC: 1175 BROpcode = SP::BCOND; 1176 break; 1177 case SP::SELECT_CC_Int_FCC: 1178 case SP::SELECT_CC_FP_FCC: 1179 case SP::SELECT_CC_DFP_FCC: 1180 BROpcode = SP::FBCOND; 1181 break; 1182 } 1183 1184 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 1185 1186 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1187 // control-flow pattern. The incoming instruction knows the destination vreg 1188 // to set, the condition code register to branch on, the true/false values to 1189 // select between, and a branch opcode to use. 1190 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1191 MachineFunction::iterator It = BB; 1192 ++It; 1193 1194 // thisMBB: 1195 // ... 1196 // TrueVal = ... 1197 // [f]bCC copy1MBB 1198 // fallthrough --> copy0MBB 1199 MachineBasicBlock *thisMBB = BB; 1200 MachineFunction *F = BB->getParent(); 1201 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1202 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1203 F->insert(It, copy0MBB); 1204 F->insert(It, sinkMBB); 1205 1206 // Transfer the remainder of BB and its successor edges to sinkMBB. 1207 sinkMBB->splice(sinkMBB->begin(), BB, 1208 llvm::next(MachineBasicBlock::iterator(MI)), 1209 BB->end()); 1210 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1211 1212 // Add the true and fallthrough blocks as its successors. 1213 BB->addSuccessor(copy0MBB); 1214 BB->addSuccessor(sinkMBB); 1215 1216 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 1217 1218 // copy0MBB: 1219 // %FalseValue = ... 1220 // # fallthrough to sinkMBB 1221 BB = copy0MBB; 1222 1223 // Update machine-CFG edges 1224 BB->addSuccessor(sinkMBB); 1225 1226 // sinkMBB: 1227 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1228 // ... 1229 BB = sinkMBB; 1230 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) 1231 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1232 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1233 1234 MI->eraseFromParent(); // The pseudo instruction is gone now. 1235 return BB; 1236 } 1237 1238 //===----------------------------------------------------------------------===// 1239 // Sparc Inline Assembly Support 1240 //===----------------------------------------------------------------------===// 1241 1242 /// getConstraintType - Given a constraint letter, return the type of 1243 /// constraint it is for this target. 1244 SparcTargetLowering::ConstraintType 1245 SparcTargetLowering::getConstraintType(const std::string &Constraint) const { 1246 if (Constraint.size() == 1) { 1247 switch (Constraint[0]) { 1248 default: break; 1249 case 'r': return C_RegisterClass; 1250 } 1251 } 1252 1253 return TargetLowering::getConstraintType(Constraint); 1254 } 1255 1256 std::pair<unsigned, const TargetRegisterClass*> 1257 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1258 EVT VT) const { 1259 if (Constraint.size() == 1) { 1260 switch (Constraint[0]) { 1261 case 'r': 1262 return std::make_pair(0U, SP::IntRegsRegisterClass); 1263 } 1264 } 1265 1266 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1267 } 1268 1269 bool 1270 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1271 // The Sparc target isn't yet aware of offsets. 1272 return false; 1273 } 1274
