| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 29 case ISD::ROTR: return ARM_AM::ror;
30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
|
| ARMISelLowering.cpp | [all...] |
| /external/openssl/crypto/sha/ |
| sha512.c | 309 # define ROTR(a,n) ({ SHA_LONG64 ret; \
339 # define ROTR(a,n) ({ SHA_LONG64 ret; \
347 # define ROTR(a,n) _rotr64((a),n)
382 #ifndef ROTR
383 #define ROTR(x,s) (((x)>>s) | (x)<<(64-s))
386 #define Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
387 #define Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)
[all...] |
| /external/openssl/crypto/sha/asm/ |
| sha512-armv4.pl | 75 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
130 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
305 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
322 @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6)
[all...] |
| sha512-armv4.s | 131 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
186 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
225 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
242 @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 310 SHL, SRA, SRL, ROTL, ROTR,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 187 case ISD::ROTR:
|
| SelectionDAGDumper.cpp | 174 case ISD::ROTR: return "rotr";
|
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 229 // FIXME: Change from "expand" to appropriate type once ROTR is supported in
231 setOperationAction(ISD::ROTR, MVT::i32, Expand /*Legal*/);
232 setOperationAction(ISD::ROTR, MVT::i16, Expand /*Legal*/);
233 setOperationAction(ISD::ROTR, MVT::i8, Expand /*Custom*/);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 102 setOperationAction(ISD::ROTR, MVT::i8, Expand);
104 setOperationAction(ISD::ROTR, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 165 setOperationAction(ISD::ROTR, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 769 setOperationAction(ISD::ROTR , MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 195 setOperationAction(ISD::ROTR, MVT::i32, Expand);
198 setOperationAction(ISD::ROTR, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 110 setOperationAction(ISD::ROTR , MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 163 // PowerPC does not have ROTR
164 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
165 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
