1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/MC/MCAsmInfo.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/Target/TargetData.h" 18 #include "llvm/Target/TargetLoweringObjectFile.h" 19 #include "llvm/Target/TargetMachine.h" 20 #include "llvm/Target/TargetRegisterInfo.h" 21 #include "llvm/GlobalVariable.h" 22 #include "llvm/DerivedTypes.h" 23 #include "llvm/CodeGen/Analysis.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineJumpTableInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/SelectionDAG.h" 28 #include "llvm/ADT/STLExtras.h" 29 #include "llvm/Support/CommandLine.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/MathExtras.h" 32 #include <cctype> 33 using namespace llvm; 34 35 /// We are in the process of implementing a new TypeLegalization action 36 /// - the promotion of vector elements. This feature is disabled by default 37 /// and only enabled using this flag. 38 static cl::opt<bool> 39 AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true), 40 cl::desc("Allow promotion of integer vector element types")); 41 42 /// InitLibcallNames - Set default libcall names. 43 /// 44 static void InitLibcallNames(const char **Names) { 45 Names[RTLIB::SHL_I16] = "__ashlhi3"; 46 Names[RTLIB::SHL_I32] = "__ashlsi3"; 47 Names[RTLIB::SHL_I64] = "__ashldi3"; 48 Names[RTLIB::SHL_I128] = "__ashlti3"; 49 Names[RTLIB::SRL_I16] = "__lshrhi3"; 50 Names[RTLIB::SRL_I32] = "__lshrsi3"; 51 Names[RTLIB::SRL_I64] = "__lshrdi3"; 52 Names[RTLIB::SRL_I128] = "__lshrti3"; 53 Names[RTLIB::SRA_I16] = "__ashrhi3"; 54 Names[RTLIB::SRA_I32] = "__ashrsi3"; 55 Names[RTLIB::SRA_I64] = "__ashrdi3"; 56 Names[RTLIB::SRA_I128] = "__ashrti3"; 57 Names[RTLIB::MUL_I8] = "__mulqi3"; 58 Names[RTLIB::MUL_I16] = "__mulhi3"; 59 Names[RTLIB::MUL_I32] = "__mulsi3"; 60 Names[RTLIB::MUL_I64] = "__muldi3"; 61 Names[RTLIB::MUL_I128] = "__multi3"; 62 Names[RTLIB::MULO_I32] = "__mulosi4"; 63 Names[RTLIB::MULO_I64] = "__mulodi4"; 64 Names[RTLIB::MULO_I128] = "__muloti4"; 65 Names[RTLIB::SDIV_I8] = "__divqi3"; 66 Names[RTLIB::SDIV_I16] = "__divhi3"; 67 Names[RTLIB::SDIV_I32] = "__divsi3"; 68 Names[RTLIB::SDIV_I64] = "__divdi3"; 69 Names[RTLIB::SDIV_I128] = "__divti3"; 70 Names[RTLIB::UDIV_I8] = "__udivqi3"; 71 Names[RTLIB::UDIV_I16] = "__udivhi3"; 72 Names[RTLIB::UDIV_I32] = "__udivsi3"; 73 Names[RTLIB::UDIV_I64] = "__udivdi3"; 74 Names[RTLIB::UDIV_I128] = "__udivti3"; 75 Names[RTLIB::SREM_I8] = "__modqi3"; 76 Names[RTLIB::SREM_I16] = "__modhi3"; 77 Names[RTLIB::SREM_I32] = "__modsi3"; 78 Names[RTLIB::SREM_I64] = "__moddi3"; 79 Names[RTLIB::SREM_I128] = "__modti3"; 80 Names[RTLIB::UREM_I8] = "__umodqi3"; 81 Names[RTLIB::UREM_I16] = "__umodhi3"; 82 Names[RTLIB::UREM_I32] = "__umodsi3"; 83 Names[RTLIB::UREM_I64] = "__umoddi3"; 84 Names[RTLIB::UREM_I128] = "__umodti3"; 85 86 // These are generally not available. 87 Names[RTLIB::SDIVREM_I8] = 0; 88 Names[RTLIB::SDIVREM_I16] = 0; 89 Names[RTLIB::SDIVREM_I32] = 0; 90 Names[RTLIB::SDIVREM_I64] = 0; 91 Names[RTLIB::SDIVREM_I128] = 0; 92 Names[RTLIB::UDIVREM_I8] = 0; 93 Names[RTLIB::UDIVREM_I16] = 0; 94 Names[RTLIB::UDIVREM_I32] = 0; 95 Names[RTLIB::UDIVREM_I64] = 0; 96 Names[RTLIB::UDIVREM_I128] = 0; 97 98 Names[RTLIB::NEG_I32] = "__negsi2"; 99 Names[RTLIB::NEG_I64] = "__negdi2"; 100 Names[RTLIB::ADD_F32] = "__addsf3"; 101 Names[RTLIB::ADD_F64] = "__adddf3"; 102 Names[RTLIB::ADD_F80] = "__addxf3"; 103 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 104 Names[RTLIB::SUB_F32] = "__subsf3"; 105 Names[RTLIB::SUB_F64] = "__subdf3"; 106 Names[RTLIB::SUB_F80] = "__subxf3"; 107 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 108 Names[RTLIB::MUL_F32] = "__mulsf3"; 109 Names[RTLIB::MUL_F64] = "__muldf3"; 110 Names[RTLIB::MUL_F80] = "__mulxf3"; 111 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 112 Names[RTLIB::DIV_F32] = "__divsf3"; 113 Names[RTLIB::DIV_F64] = "__divdf3"; 114 Names[RTLIB::DIV_F80] = "__divxf3"; 115 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 116 Names[RTLIB::REM_F32] = "fmodf"; 117 Names[RTLIB::REM_F64] = "fmod"; 118 Names[RTLIB::REM_F80] = "fmodl"; 119 Names[RTLIB::REM_PPCF128] = "fmodl"; 120 Names[RTLIB::FMA_F32] = "fmaf"; 121 Names[RTLIB::FMA_F64] = "fma"; 122 Names[RTLIB::FMA_F80] = "fmal"; 123 Names[RTLIB::FMA_PPCF128] = "fmal"; 124 Names[RTLIB::POWI_F32] = "__powisf2"; 125 Names[RTLIB::POWI_F64] = "__powidf2"; 126 Names[RTLIB::POWI_F80] = "__powixf2"; 127 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 128 Names[RTLIB::SQRT_F32] = "sqrtf"; 129 Names[RTLIB::SQRT_F64] = "sqrt"; 130 Names[RTLIB::SQRT_F80] = "sqrtl"; 131 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 132 Names[RTLIB::LOG_F32] = "logf"; 133 Names[RTLIB::LOG_F64] = "log"; 134 Names[RTLIB::LOG_F80] = "logl"; 135 Names[RTLIB::LOG_PPCF128] = "logl"; 136 Names[RTLIB::LOG2_F32] = "log2f"; 137 Names[RTLIB::LOG2_F64] = "log2"; 138 Names[RTLIB::LOG2_F80] = "log2l"; 139 Names[RTLIB::LOG2_PPCF128] = "log2l"; 140 Names[RTLIB::LOG10_F32] = "log10f"; 141 Names[RTLIB::LOG10_F64] = "log10"; 142 Names[RTLIB::LOG10_F80] = "log10l"; 143 Names[RTLIB::LOG10_PPCF128] = "log10l"; 144 Names[RTLIB::EXP_F32] = "expf"; 145 Names[RTLIB::EXP_F64] = "exp"; 146 Names[RTLIB::EXP_F80] = "expl"; 147 Names[RTLIB::EXP_PPCF128] = "expl"; 148 Names[RTLIB::EXP2_F32] = "exp2f"; 149 Names[RTLIB::EXP2_F64] = "exp2"; 150 Names[RTLIB::EXP2_F80] = "exp2l"; 151 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 152 Names[RTLIB::SIN_F32] = "sinf"; 153 Names[RTLIB::SIN_F64] = "sin"; 154 Names[RTLIB::SIN_F80] = "sinl"; 155 Names[RTLIB::SIN_PPCF128] = "sinl"; 156 Names[RTLIB::COS_F32] = "cosf"; 157 Names[RTLIB::COS_F64] = "cos"; 158 Names[RTLIB::COS_F80] = "cosl"; 159 Names[RTLIB::COS_PPCF128] = "cosl"; 160 Names[RTLIB::POW_F32] = "powf"; 161 Names[RTLIB::POW_F64] = "pow"; 162 Names[RTLIB::POW_F80] = "powl"; 163 Names[RTLIB::POW_PPCF128] = "powl"; 164 Names[RTLIB::CEIL_F32] = "ceilf"; 165 Names[RTLIB::CEIL_F64] = "ceil"; 166 Names[RTLIB::CEIL_F80] = "ceill"; 167 Names[RTLIB::CEIL_PPCF128] = "ceill"; 168 Names[RTLIB::TRUNC_F32] = "truncf"; 169 Names[RTLIB::TRUNC_F64] = "trunc"; 170 Names[RTLIB::TRUNC_F80] = "truncl"; 171 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 172 Names[RTLIB::RINT_F32] = "rintf"; 173 Names[RTLIB::RINT_F64] = "rint"; 174 Names[RTLIB::RINT_F80] = "rintl"; 175 Names[RTLIB::RINT_PPCF128] = "rintl"; 176 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 177 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 178 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 179 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 180 Names[RTLIB::FLOOR_F32] = "floorf"; 181 Names[RTLIB::FLOOR_F64] = "floor"; 182 Names[RTLIB::FLOOR_F80] = "floorl"; 183 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 184 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 185 Names[RTLIB::COPYSIGN_F64] = "copysign"; 186 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 187 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 188 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 189 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 190 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 191 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 192 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 193 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 194 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 195 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 196 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 197 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 198 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 199 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 200 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 201 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 202 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 203 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 204 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 205 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 206 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 207 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 208 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 209 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 210 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 211 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 212 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 213 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 214 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 215 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 216 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 217 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 218 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 219 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 220 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 221 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 222 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 223 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 224 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 225 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 226 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 227 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 228 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 229 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 230 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 231 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 232 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 233 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 234 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 235 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 236 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 237 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 238 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 239 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 240 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 241 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 242 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 243 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 244 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 245 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 246 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 247 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 248 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 249 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 250 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 251 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 252 Names[RTLIB::OEQ_F32] = "__eqsf2"; 253 Names[RTLIB::OEQ_F64] = "__eqdf2"; 254 Names[RTLIB::UNE_F32] = "__nesf2"; 255 Names[RTLIB::UNE_F64] = "__nedf2"; 256 Names[RTLIB::OGE_F32] = "__gesf2"; 257 Names[RTLIB::OGE_F64] = "__gedf2"; 258 Names[RTLIB::OLT_F32] = "__ltsf2"; 259 Names[RTLIB::OLT_F64] = "__ltdf2"; 260 Names[RTLIB::OLE_F32] = "__lesf2"; 261 Names[RTLIB::OLE_F64] = "__ledf2"; 262 Names[RTLIB::OGT_F32] = "__gtsf2"; 263 Names[RTLIB::OGT_F64] = "__gtdf2"; 264 Names[RTLIB::UO_F32] = "__unordsf2"; 265 Names[RTLIB::UO_F64] = "__unorddf2"; 266 Names[RTLIB::O_F32] = "__unordsf2"; 267 Names[RTLIB::O_F64] = "__unorddf2"; 268 Names[RTLIB::MEMCPY] = "memcpy"; 269 Names[RTLIB::MEMMOVE] = "memmove"; 270 Names[RTLIB::MEMSET] = "memset"; 271 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 272 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 273 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 274 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 275 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 276 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 277 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 278 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 279 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 280 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 281 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 282 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 283 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 284 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 285 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 286 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 287 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 288 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 289 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 290 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 291 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 292 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 293 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 294 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 295 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 296 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 297 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 298 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 299 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 300 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 301 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 302 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 303 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 304 } 305 306 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 307 /// 308 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 309 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 310 CCs[i] = CallingConv::C; 311 } 312 } 313 314 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 315 /// UNKNOWN_LIBCALL if there is none. 316 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 317 if (OpVT == MVT::f32) { 318 if (RetVT == MVT::f64) 319 return FPEXT_F32_F64; 320 } 321 322 return UNKNOWN_LIBCALL; 323 } 324 325 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 326 /// UNKNOWN_LIBCALL if there is none. 327 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 328 if (RetVT == MVT::f32) { 329 if (OpVT == MVT::f64) 330 return FPROUND_F64_F32; 331 if (OpVT == MVT::f80) 332 return FPROUND_F80_F32; 333 if (OpVT == MVT::ppcf128) 334 return FPROUND_PPCF128_F32; 335 } else if (RetVT == MVT::f64) { 336 if (OpVT == MVT::f80) 337 return FPROUND_F80_F64; 338 if (OpVT == MVT::ppcf128) 339 return FPROUND_PPCF128_F64; 340 } 341 342 return UNKNOWN_LIBCALL; 343 } 344 345 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 346 /// UNKNOWN_LIBCALL if there is none. 347 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 348 if (OpVT == MVT::f32) { 349 if (RetVT == MVT::i8) 350 return FPTOSINT_F32_I8; 351 if (RetVT == MVT::i16) 352 return FPTOSINT_F32_I16; 353 if (RetVT == MVT::i32) 354 return FPTOSINT_F32_I32; 355 if (RetVT == MVT::i64) 356 return FPTOSINT_F32_I64; 357 if (RetVT == MVT::i128) 358 return FPTOSINT_F32_I128; 359 } else if (OpVT == MVT::f64) { 360 if (RetVT == MVT::i8) 361 return FPTOSINT_F64_I8; 362 if (RetVT == MVT::i16) 363 return FPTOSINT_F64_I16; 364 if (RetVT == MVT::i32) 365 return FPTOSINT_F64_I32; 366 if (RetVT == MVT::i64) 367 return FPTOSINT_F64_I64; 368 if (RetVT == MVT::i128) 369 return FPTOSINT_F64_I128; 370 } else if (OpVT == MVT::f80) { 371 if (RetVT == MVT::i32) 372 return FPTOSINT_F80_I32; 373 if (RetVT == MVT::i64) 374 return FPTOSINT_F80_I64; 375 if (RetVT == MVT::i128) 376 return FPTOSINT_F80_I128; 377 } else if (OpVT == MVT::ppcf128) { 378 if (RetVT == MVT::i32) 379 return FPTOSINT_PPCF128_I32; 380 if (RetVT == MVT::i64) 381 return FPTOSINT_PPCF128_I64; 382 if (RetVT == MVT::i128) 383 return FPTOSINT_PPCF128_I128; 384 } 385 return UNKNOWN_LIBCALL; 386 } 387 388 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 389 /// UNKNOWN_LIBCALL if there is none. 390 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 391 if (OpVT == MVT::f32) { 392 if (RetVT == MVT::i8) 393 return FPTOUINT_F32_I8; 394 if (RetVT == MVT::i16) 395 return FPTOUINT_F32_I16; 396 if (RetVT == MVT::i32) 397 return FPTOUINT_F32_I32; 398 if (RetVT == MVT::i64) 399 return FPTOUINT_F32_I64; 400 if (RetVT == MVT::i128) 401 return FPTOUINT_F32_I128; 402 } else if (OpVT == MVT::f64) { 403 if (RetVT == MVT::i8) 404 return FPTOUINT_F64_I8; 405 if (RetVT == MVT::i16) 406 return FPTOUINT_F64_I16; 407 if (RetVT == MVT::i32) 408 return FPTOUINT_F64_I32; 409 if (RetVT == MVT::i64) 410 return FPTOUINT_F64_I64; 411 if (RetVT == MVT::i128) 412 return FPTOUINT_F64_I128; 413 } else if (OpVT == MVT::f80) { 414 if (RetVT == MVT::i32) 415 return FPTOUINT_F80_I32; 416 if (RetVT == MVT::i64) 417 return FPTOUINT_F80_I64; 418 if (RetVT == MVT::i128) 419 return FPTOUINT_F80_I128; 420 } else if (OpVT == MVT::ppcf128) { 421 if (RetVT == MVT::i32) 422 return FPTOUINT_PPCF128_I32; 423 if (RetVT == MVT::i64) 424 return FPTOUINT_PPCF128_I64; 425 if (RetVT == MVT::i128) 426 return FPTOUINT_PPCF128_I128; 427 } 428 return UNKNOWN_LIBCALL; 429 } 430 431 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 432 /// UNKNOWN_LIBCALL if there is none. 433 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 434 if (OpVT == MVT::i32) { 435 if (RetVT == MVT::f32) 436 return SINTTOFP_I32_F32; 437 else if (RetVT == MVT::f64) 438 return SINTTOFP_I32_F64; 439 else if (RetVT == MVT::f80) 440 return SINTTOFP_I32_F80; 441 else if (RetVT == MVT::ppcf128) 442 return SINTTOFP_I32_PPCF128; 443 } else if (OpVT == MVT::i64) { 444 if (RetVT == MVT::f32) 445 return SINTTOFP_I64_F32; 446 else if (RetVT == MVT::f64) 447 return SINTTOFP_I64_F64; 448 else if (RetVT == MVT::f80) 449 return SINTTOFP_I64_F80; 450 else if (RetVT == MVT::ppcf128) 451 return SINTTOFP_I64_PPCF128; 452 } else if (OpVT == MVT::i128) { 453 if (RetVT == MVT::f32) 454 return SINTTOFP_I128_F32; 455 else if (RetVT == MVT::f64) 456 return SINTTOFP_I128_F64; 457 else if (RetVT == MVT::f80) 458 return SINTTOFP_I128_F80; 459 else if (RetVT == MVT::ppcf128) 460 return SINTTOFP_I128_PPCF128; 461 } 462 return UNKNOWN_LIBCALL; 463 } 464 465 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 466 /// UNKNOWN_LIBCALL if there is none. 467 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 468 if (OpVT == MVT::i32) { 469 if (RetVT == MVT::f32) 470 return UINTTOFP_I32_F32; 471 else if (RetVT == MVT::f64) 472 return UINTTOFP_I32_F64; 473 else if (RetVT == MVT::f80) 474 return UINTTOFP_I32_F80; 475 else if (RetVT == MVT::ppcf128) 476 return UINTTOFP_I32_PPCF128; 477 } else if (OpVT == MVT::i64) { 478 if (RetVT == MVT::f32) 479 return UINTTOFP_I64_F32; 480 else if (RetVT == MVT::f64) 481 return UINTTOFP_I64_F64; 482 else if (RetVT == MVT::f80) 483 return UINTTOFP_I64_F80; 484 else if (RetVT == MVT::ppcf128) 485 return UINTTOFP_I64_PPCF128; 486 } else if (OpVT == MVT::i128) { 487 if (RetVT == MVT::f32) 488 return UINTTOFP_I128_F32; 489 else if (RetVT == MVT::f64) 490 return UINTTOFP_I128_F64; 491 else if (RetVT == MVT::f80) 492 return UINTTOFP_I128_F80; 493 else if (RetVT == MVT::ppcf128) 494 return UINTTOFP_I128_PPCF128; 495 } 496 return UNKNOWN_LIBCALL; 497 } 498 499 /// InitCmpLibcallCCs - Set default comparison libcall CC. 500 /// 501 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 502 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 503 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 504 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 505 CCs[RTLIB::UNE_F32] = ISD::SETNE; 506 CCs[RTLIB::UNE_F64] = ISD::SETNE; 507 CCs[RTLIB::OGE_F32] = ISD::SETGE; 508 CCs[RTLIB::OGE_F64] = ISD::SETGE; 509 CCs[RTLIB::OLT_F32] = ISD::SETLT; 510 CCs[RTLIB::OLT_F64] = ISD::SETLT; 511 CCs[RTLIB::OLE_F32] = ISD::SETLE; 512 CCs[RTLIB::OLE_F64] = ISD::SETLE; 513 CCs[RTLIB::OGT_F32] = ISD::SETGT; 514 CCs[RTLIB::OGT_F64] = ISD::SETGT; 515 CCs[RTLIB::UO_F32] = ISD::SETNE; 516 CCs[RTLIB::UO_F64] = ISD::SETNE; 517 CCs[RTLIB::O_F32] = ISD::SETEQ; 518 CCs[RTLIB::O_F64] = ISD::SETEQ; 519 } 520 521 /// NOTE: The constructor takes ownership of TLOF. 522 TargetLowering::TargetLowering(const TargetMachine &tm, 523 const TargetLoweringObjectFile *tlof) 524 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof), 525 mayPromoteElements(AllowPromoteIntElem) { 526 // All operations default to being supported. 527 memset(OpActions, 0, sizeof(OpActions)); 528 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 529 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 530 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 531 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 532 533 // Set default actions for various operations. 534 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 535 // Default all indexed load / store to expand. 536 for (unsigned IM = (unsigned)ISD::PRE_INC; 537 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 538 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 539 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 540 } 541 542 // These operations default to expand. 543 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 544 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 545 } 546 547 // Most targets ignore the @llvm.prefetch intrinsic. 548 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 549 550 // ConstantFP nodes default to expand. Targets can either change this to 551 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 552 // to optimize expansions for certain constants. 553 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 554 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 555 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 556 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 557 558 // These library functions default to expand. 559 setOperationAction(ISD::FLOG , MVT::f16, Expand); 560 setOperationAction(ISD::FLOG2, MVT::f16, Expand); 561 setOperationAction(ISD::FLOG10, MVT::f16, Expand); 562 setOperationAction(ISD::FEXP , MVT::f16, Expand); 563 setOperationAction(ISD::FEXP2, MVT::f16, Expand); 564 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); 565 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); 566 setOperationAction(ISD::FCEIL, MVT::f16, Expand); 567 setOperationAction(ISD::FRINT, MVT::f16, Expand); 568 setOperationAction(ISD::FTRUNC, MVT::f16, Expand); 569 setOperationAction(ISD::FLOG , MVT::f32, Expand); 570 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 571 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 572 setOperationAction(ISD::FEXP , MVT::f32, Expand); 573 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 574 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); 575 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); 576 setOperationAction(ISD::FCEIL, MVT::f32, Expand); 577 setOperationAction(ISD::FRINT, MVT::f32, Expand); 578 setOperationAction(ISD::FTRUNC, MVT::f32, Expand); 579 setOperationAction(ISD::FLOG , MVT::f64, Expand); 580 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 581 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 582 setOperationAction(ISD::FEXP , MVT::f64, Expand); 583 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 584 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); 585 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); 586 setOperationAction(ISD::FCEIL, MVT::f64, Expand); 587 setOperationAction(ISD::FRINT, MVT::f64, Expand); 588 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); 589 590 // Default ISD::TRAP to expand (which turns it into abort). 591 setOperationAction(ISD::TRAP, MVT::Other, Expand); 592 593 IsLittleEndian = TD->isLittleEndian(); 594 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 595 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 596 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 597 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 598 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize 599 = maxStoresPerMemmoveOptSize = 4; 600 benefitFromCodePlacementOpt = false; 601 UseUnderscoreSetJmp = false; 602 UseUnderscoreLongJmp = false; 603 SelectIsExpensive = false; 604 IntDivIsCheap = false; 605 Pow2DivIsCheap = false; 606 JumpIsExpensive = false; 607 StackPointerRegisterToSaveRestore = 0; 608 ExceptionPointerRegister = 0; 609 ExceptionSelectorRegister = 0; 610 BooleanContents = UndefinedBooleanContent; 611 BooleanVectorContents = UndefinedBooleanContent; 612 SchedPreferenceInfo = Sched::ILP; 613 JumpBufSize = 0; 614 JumpBufAlignment = 0; 615 MinFunctionAlignment = 0; 616 PrefFunctionAlignment = 0; 617 PrefLoopAlignment = 0; 618 MinStackArgumentAlignment = 1; 619 ShouldFoldAtomicFences = false; 620 InsertFencesForAtomic = false; 621 622 InitLibcallNames(LibcallRoutineNames); 623 InitCmpLibcallCCs(CmpLibcallCCs); 624 InitLibcallCallingConvs(LibcallCallingConvs); 625 } 626 627 TargetLowering::~TargetLowering() { 628 delete &TLOF; 629 } 630 631 MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const { 632 return MVT::getIntegerVT(8*TD->getPointerSize()); 633 } 634 635 /// canOpTrap - Returns true if the operation can trap for the value type. 636 /// VT must be a legal type. 637 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 638 assert(isTypeLegal(VT)); 639 switch (Op) { 640 default: 641 return false; 642 case ISD::FDIV: 643 case ISD::FREM: 644 case ISD::SDIV: 645 case ISD::UDIV: 646 case ISD::SREM: 647 case ISD::UREM: 648 return true; 649 } 650 } 651 652 653 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 654 unsigned &NumIntermediates, 655 EVT &RegisterVT, 656 TargetLowering *TLI) { 657 // Figure out the right, legal destination reg to copy into. 658 unsigned NumElts = VT.getVectorNumElements(); 659 MVT EltTy = VT.getVectorElementType(); 660 661 unsigned NumVectorRegs = 1; 662 663 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 664 // could break down into LHS/RHS like LegalizeDAG does. 665 if (!isPowerOf2_32(NumElts)) { 666 NumVectorRegs = NumElts; 667 NumElts = 1; 668 } 669 670 // Divide the input until we get to a supported size. This will always 671 // end with a scalar if the target doesn't support vectors. 672 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 673 NumElts >>= 1; 674 NumVectorRegs <<= 1; 675 } 676 677 NumIntermediates = NumVectorRegs; 678 679 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 680 if (!TLI->isTypeLegal(NewVT)) 681 NewVT = EltTy; 682 IntermediateVT = NewVT; 683 684 unsigned NewVTSize = NewVT.getSizeInBits(); 685 686 // Convert sizes such as i33 to i64. 687 if (!isPowerOf2_32(NewVTSize)) 688 NewVTSize = NextPowerOf2(NewVTSize); 689 690 EVT DestVT = TLI->getRegisterType(NewVT); 691 RegisterVT = DestVT; 692 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 693 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 694 695 // Otherwise, promotion or legal types use the same number of registers as 696 // the vector decimated to the appropriate level. 697 return NumVectorRegs; 698 } 699 700 /// isLegalRC - Return true if the value types that can be represented by the 701 /// specified register class are all legal. 702 bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const { 703 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 704 I != E; ++I) { 705 if (isTypeLegal(*I)) 706 return true; 707 } 708 return false; 709 } 710 711 /// hasLegalSuperRegRegClasses - Return true if the specified register class 712 /// has one or more super-reg register classes that are legal. 713 bool 714 TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{ 715 if (*RC->superregclasses_begin() == 0) 716 return false; 717 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 718 E = RC->superregclasses_end(); I != E; ++I) { 719 const TargetRegisterClass *RRC = *I; 720 if (isLegalRC(RRC)) 721 return true; 722 } 723 return false; 724 } 725 726 /// findRepresentativeClass - Return the largest legal super-reg register class 727 /// of the register class for the specified type and its associated "cost". 728 std::pair<const TargetRegisterClass*, uint8_t> 729 TargetLowering::findRepresentativeClass(EVT VT) const { 730 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 731 if (!RC) 732 return std::make_pair(RC, 0); 733 const TargetRegisterClass *BestRC = RC; 734 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 735 E = RC->superregclasses_end(); I != E; ++I) { 736 const TargetRegisterClass *RRC = *I; 737 if (RRC->isASubClass() || !isLegalRC(RRC)) 738 continue; 739 if (!hasLegalSuperRegRegClasses(RRC)) 740 return std::make_pair(RRC, 1); 741 BestRC = RRC; 742 } 743 return std::make_pair(BestRC, 1); 744 } 745 746 747 /// computeRegisterProperties - Once all of the register classes are added, 748 /// this allows us to compute derived properties we expose. 749 void TargetLowering::computeRegisterProperties() { 750 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 751 "Too many value types for ValueTypeActions to hold!"); 752 753 // Everything defaults to needing one register. 754 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 755 NumRegistersForVT[i] = 1; 756 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 757 } 758 // ...except isVoid, which doesn't need any registers. 759 NumRegistersForVT[MVT::isVoid] = 0; 760 761 // Find the largest integer register class. 762 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 763 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 764 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 765 766 // Every integer value type larger than this largest register takes twice as 767 // many registers to represent as the previous ValueType. 768 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 769 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 770 if (!ExpandedVT.isInteger()) 771 break; 772 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 773 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 774 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 775 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger); 776 } 777 778 // Inspect all of the ValueType's smaller than the largest integer 779 // register to see which ones need promotion. 780 unsigned LegalIntReg = LargestIntReg; 781 for (unsigned IntReg = LargestIntReg - 1; 782 IntReg >= (unsigned)MVT::i1; --IntReg) { 783 EVT IVT = (MVT::SimpleValueType)IntReg; 784 if (isTypeLegal(IVT)) { 785 LegalIntReg = IntReg; 786 } else { 787 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 788 (MVT::SimpleValueType)LegalIntReg; 789 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 790 } 791 } 792 793 // ppcf128 type is really two f64's. 794 if (!isTypeLegal(MVT::ppcf128)) { 795 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 796 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 797 TransformToType[MVT::ppcf128] = MVT::f64; 798 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 799 } 800 801 // Decide how to handle f64. If the target does not have native f64 support, 802 // expand it to i64 and we will be generating soft float library calls. 803 if (!isTypeLegal(MVT::f64)) { 804 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 805 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 806 TransformToType[MVT::f64] = MVT::i64; 807 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 808 } 809 810 // Decide how to handle f32. If the target does not have native support for 811 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 812 if (!isTypeLegal(MVT::f32)) { 813 if (isTypeLegal(MVT::f64)) { 814 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 815 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 816 TransformToType[MVT::f32] = MVT::f64; 817 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 818 } else { 819 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 820 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 821 TransformToType[MVT::f32] = MVT::i32; 822 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 823 } 824 } 825 826 // Loop over all of the vector value types to see which need transformations. 827 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 828 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 829 MVT VT = (MVT::SimpleValueType)i; 830 if (isTypeLegal(VT)) continue; 831 832 // Determine if there is a legal wider type. If so, we should promote to 833 // that wider vector type. 834 EVT EltVT = VT.getVectorElementType(); 835 unsigned NElts = VT.getVectorNumElements(); 836 if (NElts != 1) { 837 bool IsLegalWiderType = false; 838 // If we allow the promotion of vector elements using a flag, 839 // then return TypePromoteInteger on vector elements. 840 // First try to promote the elements of integer vectors. If no legal 841 // promotion was found, fallback to the widen-vector method. 842 if (mayPromoteElements) 843 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 844 EVT SVT = (MVT::SimpleValueType)nVT; 845 // Promote vectors of integers to vectors with the same number 846 // of elements, with a wider element type. 847 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 848 && SVT.getVectorNumElements() == NElts && 849 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { 850 TransformToType[i] = SVT; 851 RegisterTypeForVT[i] = SVT; 852 NumRegistersForVT[i] = 1; 853 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 854 IsLegalWiderType = true; 855 break; 856 } 857 } 858 859 if (IsLegalWiderType) continue; 860 861 // Try to widen the vector. 862 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 863 EVT SVT = (MVT::SimpleValueType)nVT; 864 if (SVT.getVectorElementType() == EltVT && 865 SVT.getVectorNumElements() > NElts && 866 isTypeLegal(SVT)) { 867 TransformToType[i] = SVT; 868 RegisterTypeForVT[i] = SVT; 869 NumRegistersForVT[i] = 1; 870 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 871 IsLegalWiderType = true; 872 break; 873 } 874 } 875 if (IsLegalWiderType) continue; 876 } 877 878 MVT IntermediateVT; 879 EVT RegisterVT; 880 unsigned NumIntermediates; 881 NumRegistersForVT[i] = 882 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 883 RegisterVT, this); 884 RegisterTypeForVT[i] = RegisterVT; 885 886 EVT NVT = VT.getPow2VectorType(); 887 if (NVT == VT) { 888 // Type is already a power of 2. The default action is to split. 889 TransformToType[i] = MVT::Other; 890 unsigned NumElts = VT.getVectorNumElements(); 891 ValueTypeActions.setTypeAction(VT, 892 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 893 } else { 894 TransformToType[i] = NVT; 895 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 896 } 897 } 898 899 // Determine the 'representative' register class for each value type. 900 // An representative register class is the largest (meaning one which is 901 // not a sub-register class / subreg register class) legal register class for 902 // a group of value types. For example, on i386, i8, i16, and i32 903 // representative would be GR32; while on x86_64 it's GR64. 904 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 905 const TargetRegisterClass* RRC; 906 uint8_t Cost; 907 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 908 RepRegClassForVT[i] = RRC; 909 RepRegClassCostForVT[i] = Cost; 910 } 911 } 912 913 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 914 return NULL; 915 } 916 917 918 EVT TargetLowering::getSetCCResultType(EVT VT) const { 919 assert(!VT.isVector() && "No default SetCC type for vectors!"); 920 return PointerTy.SimpleTy; 921 } 922 923 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 924 return MVT::i32; // return the default value 925 } 926 927 /// getVectorTypeBreakdown - Vector types are broken down into some number of 928 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 929 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 930 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 931 /// 932 /// This method returns the number of registers needed, and the VT for each 933 /// register. It also returns the VT and quantity of the intermediate values 934 /// before they are promoted/expanded. 935 /// 936 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 937 EVT &IntermediateVT, 938 unsigned &NumIntermediates, 939 EVT &RegisterVT) const { 940 unsigned NumElts = VT.getVectorNumElements(); 941 942 // If there is a wider vector type with the same element type as this one, 943 // we should widen to that legal vector type. This handles things like 944 // <2 x float> -> <4 x float>. 945 if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) { 946 RegisterVT = getTypeToTransformTo(Context, VT); 947 if (isTypeLegal(RegisterVT)) { 948 IntermediateVT = RegisterVT; 949 NumIntermediates = 1; 950 return 1; 951 } 952 } 953 954 // Figure out the right, legal destination reg to copy into. 955 EVT EltTy = VT.getVectorElementType(); 956 957 unsigned NumVectorRegs = 1; 958 959 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 960 // could break down into LHS/RHS like LegalizeDAG does. 961 if (!isPowerOf2_32(NumElts)) { 962 NumVectorRegs = NumElts; 963 NumElts = 1; 964 } 965 966 // Divide the input until we get to a supported size. This will always 967 // end with a scalar if the target doesn't support vectors. 968 while (NumElts > 1 && !isTypeLegal( 969 EVT::getVectorVT(Context, EltTy, NumElts))) { 970 NumElts >>= 1; 971 NumVectorRegs <<= 1; 972 } 973 974 NumIntermediates = NumVectorRegs; 975 976 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 977 if (!isTypeLegal(NewVT)) 978 NewVT = EltTy; 979 IntermediateVT = NewVT; 980 981 EVT DestVT = getRegisterType(Context, NewVT); 982 RegisterVT = DestVT; 983 unsigned NewVTSize = NewVT.getSizeInBits(); 984 985 // Convert sizes such as i33 to i64. 986 if (!isPowerOf2_32(NewVTSize)) 987 NewVTSize = NextPowerOf2(NewVTSize); 988 989 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 990 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 991 992 // Otherwise, promotion or legal types use the same number of registers as 993 // the vector decimated to the appropriate level. 994 return NumVectorRegs; 995 } 996 997 /// Get the EVTs and ArgFlags collections that represent the legalized return 998 /// type of the given function. This does not require a DAG or a return value, 999 /// and is suitable for use before any DAGs for the function are constructed. 1000 /// TODO: Move this out of TargetLowering.cpp. 1001 void llvm::GetReturnInfo(Type* ReturnType, Attributes attr, 1002 SmallVectorImpl<ISD::OutputArg> &Outs, 1003 const TargetLowering &TLI, 1004 SmallVectorImpl<uint64_t> *Offsets) { 1005 SmallVector<EVT, 4> ValueVTs; 1006 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1007 unsigned NumValues = ValueVTs.size(); 1008 if (NumValues == 0) return; 1009 unsigned Offset = 0; 1010 1011 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1012 EVT VT = ValueVTs[j]; 1013 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1014 1015 if (attr & Attribute::SExt) 1016 ExtendKind = ISD::SIGN_EXTEND; 1017 else if (attr & Attribute::ZExt) 1018 ExtendKind = ISD::ZERO_EXTEND; 1019 1020 // FIXME: C calling convention requires the return type to be promoted to 1021 // at least 32-bit. But this is not necessary for non-C calling 1022 // conventions. The frontend should mark functions whose return values 1023 // require promoting with signext or zeroext attributes. 1024 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1025 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1026 if (VT.bitsLT(MinVT)) 1027 VT = MinVT; 1028 } 1029 1030 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1031 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1032 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 1033 PartVT.getTypeForEVT(ReturnType->getContext())); 1034 1035 // 'inreg' on function refers to return value 1036 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1037 if (attr & Attribute::InReg) 1038 Flags.setInReg(); 1039 1040 // Propagate extension type if any 1041 if (attr & Attribute::SExt) 1042 Flags.setSExt(); 1043 else if (attr & Attribute::ZExt) 1044 Flags.setZExt(); 1045 1046 for (unsigned i = 0; i < NumParts; ++i) { 1047 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true)); 1048 if (Offsets) { 1049 Offsets->push_back(Offset); 1050 Offset += PartSize; 1051 } 1052 } 1053 } 1054 } 1055 1056 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1057 /// function arguments in the caller parameter area. This is the actual 1058 /// alignment, not its logarithm. 1059 unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const { 1060 return TD->getCallFrameTypeAlignment(Ty); 1061 } 1062 1063 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 1064 /// current function. The returned value is a member of the 1065 /// MachineJumpTableInfo::JTEntryKind enum. 1066 unsigned TargetLowering::getJumpTableEncoding() const { 1067 // In non-pic modes, just use the address of a block. 1068 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1069 return MachineJumpTableInfo::EK_BlockAddress; 1070 1071 // In PIC mode, if the target supports a GPRel32 directive, use it. 1072 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 1073 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 1074 1075 // Otherwise, use a label difference. 1076 return MachineJumpTableInfo::EK_LabelDifference32; 1077 } 1078 1079 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1080 SelectionDAG &DAG) const { 1081 // If our PIC model is GP relative, use the global offset table as the base. 1082 unsigned JTEncoding = getJumpTableEncoding(); 1083 1084 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) || 1085 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress)) 1086 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1087 1088 return Table; 1089 } 1090 1091 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1092 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1093 /// MCExpr. 1094 const MCExpr * 1095 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1096 unsigned JTI,MCContext &Ctx) const{ 1097 // The normal PIC reloc base is the label at the start of the jump table. 1098 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 1099 } 1100 1101 bool 1102 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1103 // Assume that everything is safe in static mode. 1104 if (getTargetMachine().getRelocationModel() == Reloc::Static) 1105 return true; 1106 1107 // In dynamic-no-pic mode, assume that known defined values are safe. 1108 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 1109 GA && 1110 !GA->getGlobal()->isDeclaration() && 1111 !GA->getGlobal()->isWeakForLinker()) 1112 return true; 1113 1114 // Otherwise assume nothing is safe. 1115 return false; 1116 } 1117 1118 //===----------------------------------------------------------------------===// 1119 // Optimization Methods 1120 //===----------------------------------------------------------------------===// 1121 1122 /// ShrinkDemandedConstant - Check to see if the specified operand of the 1123 /// specified instruction is a constant integer. If so, check to see if there 1124 /// are any bits set in the constant that are not demanded. If so, shrink the 1125 /// constant and return true. 1126 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 1127 const APInt &Demanded) { 1128 DebugLoc dl = Op.getDebugLoc(); 1129 1130 // FIXME: ISD::SELECT, ISD::SELECT_CC 1131 switch (Op.getOpcode()) { 1132 default: break; 1133 case ISD::XOR: 1134 case ISD::AND: 1135 case ISD::OR: { 1136 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1137 if (!C) return false; 1138 1139 if (Op.getOpcode() == ISD::XOR && 1140 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 1141 return false; 1142 1143 // if we can expand it to have all bits set, do it 1144 if (C->getAPIntValue().intersects(~Demanded)) { 1145 EVT VT = Op.getValueType(); 1146 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 1147 DAG.getConstant(Demanded & 1148 C->getAPIntValue(), 1149 VT)); 1150 return CombineTo(Op, New); 1151 } 1152 1153 break; 1154 } 1155 } 1156 1157 return false; 1158 } 1159 1160 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1161 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1162 /// cast, but it could be generalized for targets with other types of 1163 /// implicit widening casts. 1164 bool 1165 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1166 unsigned BitWidth, 1167 const APInt &Demanded, 1168 DebugLoc dl) { 1169 assert(Op.getNumOperands() == 2 && 1170 "ShrinkDemandedOp only supports binary operators!"); 1171 assert(Op.getNode()->getNumValues() == 1 && 1172 "ShrinkDemandedOp only supports nodes with one result!"); 1173 1174 // Don't do this if the node has another user, which may require the 1175 // full value. 1176 if (!Op.getNode()->hasOneUse()) 1177 return false; 1178 1179 // Search for the smallest integer type with free casts to and from 1180 // Op's type. For expedience, just check power-of-2 integer types. 1181 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1182 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 1183 if (!isPowerOf2_32(SmallVTBits)) 1184 SmallVTBits = NextPowerOf2(SmallVTBits); 1185 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1186 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1187 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1188 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1189 // We found a type with free casts. 1190 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1191 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1192 Op.getNode()->getOperand(0)), 1193 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1194 Op.getNode()->getOperand(1))); 1195 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 1196 return CombineTo(Op, Z); 1197 } 1198 } 1199 return false; 1200 } 1201 1202 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1203 /// DemandedMask bits of the result of Op are ever used downstream. If we can 1204 /// use this information to simplify Op, create a new simplified DAG node and 1205 /// return true, returning the original and new nodes in Old and New. Otherwise, 1206 /// analyze the expression and return a mask of KnownOne and KnownZero bits for 1207 /// the expression (used to simplify the caller). The KnownZero/One bits may 1208 /// only be accurate for those bits in the DemandedMask. 1209 bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1210 const APInt &DemandedMask, 1211 APInt &KnownZero, 1212 APInt &KnownOne, 1213 TargetLoweringOpt &TLO, 1214 unsigned Depth) const { 1215 unsigned BitWidth = DemandedMask.getBitWidth(); 1216 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1217 "Mask size mismatches value type size!"); 1218 APInt NewMask = DemandedMask; 1219 DebugLoc dl = Op.getDebugLoc(); 1220 1221 // Don't know anything. 1222 KnownZero = KnownOne = APInt(BitWidth, 0); 1223 1224 // Other users may use these bits. 1225 if (!Op.getNode()->hasOneUse()) { 1226 if (Depth != 0) { 1227 // If not at the root, Just compute the KnownZero/KnownOne bits to 1228 // simplify things downstream. 1229 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 1230 return false; 1231 } 1232 // If this is the root being simplified, allow it to have multiple uses, 1233 // just set the NewMask to all bits. 1234 NewMask = APInt::getAllOnesValue(BitWidth); 1235 } else if (DemandedMask == 0) { 1236 // Not demanding any bits from Op. 1237 if (Op.getOpcode() != ISD::UNDEF) 1238 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1239 return false; 1240 } else if (Depth == 6) { // Limit search depth. 1241 return false; 1242 } 1243 1244 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1245 switch (Op.getOpcode()) { 1246 case ISD::Constant: 1247 // We know all of the bits for a constant! 1248 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue(); 1249 KnownZero = ~KnownOne; 1250 return false; // Don't fall through, will infinitely loop. 1251 case ISD::AND: 1252 // If the RHS is a constant, check to see if the LHS would be zero without 1253 // using the bits from the RHS. Below, we use knowledge about the RHS to 1254 // simplify the LHS, here we're using information from the LHS to simplify 1255 // the RHS. 1256 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1257 APInt LHSZero, LHSOne; 1258 // Do not increment Depth here; that can cause an infinite loop. 1259 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth); 1260 // If the LHS already has zeros where RHSC does, this and is dead. 1261 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1262 return TLO.CombineTo(Op, Op.getOperand(0)); 1263 // If any of the set bits in the RHS are known zero on the LHS, shrink 1264 // the constant. 1265 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1266 return true; 1267 } 1268 1269 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1270 KnownOne, TLO, Depth+1)) 1271 return true; 1272 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1273 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1274 KnownZero2, KnownOne2, TLO, Depth+1)) 1275 return true; 1276 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1277 1278 // If all of the demanded bits are known one on one side, return the other. 1279 // These bits cannot contribute to the result of the 'and'. 1280 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1281 return TLO.CombineTo(Op, Op.getOperand(0)); 1282 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1283 return TLO.CombineTo(Op, Op.getOperand(1)); 1284 // If all of the demanded bits in the inputs are known zeros, return zero. 1285 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1286 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1287 // If the RHS is a constant, see if we can simplify it. 1288 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1289 return true; 1290 // If the operation can be done in a smaller type, do so. 1291 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1292 return true; 1293 1294 // Output known-1 bits are only known if set in both the LHS & RHS. 1295 KnownOne &= KnownOne2; 1296 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1297 KnownZero |= KnownZero2; 1298 break; 1299 case ISD::OR: 1300 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1301 KnownOne, TLO, Depth+1)) 1302 return true; 1303 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1304 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1305 KnownZero2, KnownOne2, TLO, Depth+1)) 1306 return true; 1307 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1308 1309 // If all of the demanded bits are known zero on one side, return the other. 1310 // These bits cannot contribute to the result of the 'or'. 1311 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1312 return TLO.CombineTo(Op, Op.getOperand(0)); 1313 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1314 return TLO.CombineTo(Op, Op.getOperand(1)); 1315 // If all of the potentially set bits on one side are known to be set on 1316 // the other side, just use the 'other' side. 1317 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1318 return TLO.CombineTo(Op, Op.getOperand(0)); 1319 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1320 return TLO.CombineTo(Op, Op.getOperand(1)); 1321 // If the RHS is a constant, see if we can simplify it. 1322 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1323 return true; 1324 // If the operation can be done in a smaller type, do so. 1325 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1326 return true; 1327 1328 // Output known-0 bits are only known if clear in both the LHS & RHS. 1329 KnownZero &= KnownZero2; 1330 // Output known-1 are known to be set if set in either the LHS | RHS. 1331 KnownOne |= KnownOne2; 1332 break; 1333 case ISD::XOR: 1334 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1335 KnownOne, TLO, Depth+1)) 1336 return true; 1337 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1338 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1339 KnownOne2, TLO, Depth+1)) 1340 return true; 1341 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1342 1343 // If all of the demanded bits are known zero on one side, return the other. 1344 // These bits cannot contribute to the result of the 'xor'. 1345 if ((KnownZero & NewMask) == NewMask) 1346 return TLO.CombineTo(Op, Op.getOperand(0)); 1347 if ((KnownZero2 & NewMask) == NewMask) 1348 return TLO.CombineTo(Op, Op.getOperand(1)); 1349 // If the operation can be done in a smaller type, do so. 1350 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1351 return true; 1352 1353 // If all of the unknown bits are known to be zero on one side or the other 1354 // (but not both) turn this into an *inclusive* or. 1355 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1356 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1357 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1358 Op.getOperand(0), 1359 Op.getOperand(1))); 1360 1361 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1362 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1363 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1364 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1365 1366 // If all of the demanded bits on one side are known, and all of the set 1367 // bits on that side are also known to be set on the other side, turn this 1368 // into an AND, as we know the bits will be cleared. 1369 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1370 // NB: it is okay if more bits are known than are requested 1371 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side 1372 if (KnownOne == KnownOne2) { // set bits are the same on both sides 1373 EVT VT = Op.getValueType(); 1374 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1375 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1376 Op.getOperand(0), ANDC)); 1377 } 1378 } 1379 1380 // If the RHS is a constant, see if we can simplify it. 1381 // for XOR, we prefer to force bits to 1 if they will make a -1. 1382 // if we can't force bits, try to shrink constant 1383 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1384 APInt Expanded = C->getAPIntValue() | (~NewMask); 1385 // if we can expand it to have all bits set, do it 1386 if (Expanded.isAllOnesValue()) { 1387 if (Expanded != C->getAPIntValue()) { 1388 EVT VT = Op.getValueType(); 1389 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1390 TLO.DAG.getConstant(Expanded, VT)); 1391 return TLO.CombineTo(Op, New); 1392 } 1393 // if it already has all the bits set, nothing to change 1394 // but don't shrink either! 1395 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1396 return true; 1397 } 1398 } 1399 1400 KnownZero = KnownZeroOut; 1401 KnownOne = KnownOneOut; 1402 break; 1403 case ISD::SELECT: 1404 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1405 KnownOne, TLO, Depth+1)) 1406 return true; 1407 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1408 KnownOne2, TLO, Depth+1)) 1409 return true; 1410 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1411 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1412 1413 // If the operands are constants, see if we can simplify them. 1414 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1415 return true; 1416 1417 // Only known if known in both the LHS and RHS. 1418 KnownOne &= KnownOne2; 1419 KnownZero &= KnownZero2; 1420 break; 1421 case ISD::SELECT_CC: 1422 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1423 KnownOne, TLO, Depth+1)) 1424 return true; 1425 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1426 KnownOne2, TLO, Depth+1)) 1427 return true; 1428 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1429 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1430 1431 // If the operands are constants, see if we can simplify them. 1432 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1433 return true; 1434 1435 // Only known if known in both the LHS and RHS. 1436 KnownOne &= KnownOne2; 1437 KnownZero &= KnownZero2; 1438 break; 1439 case ISD::SHL: 1440 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1441 unsigned ShAmt = SA->getZExtValue(); 1442 SDValue InOp = Op.getOperand(0); 1443 1444 // If the shift count is an invalid immediate, don't do anything. 1445 if (ShAmt >= BitWidth) 1446 break; 1447 1448 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1449 // single shift. We can do this if the bottom bits (which are shifted 1450 // out) are never demanded. 1451 if (InOp.getOpcode() == ISD::SRL && 1452 isa<ConstantSDNode>(InOp.getOperand(1))) { 1453 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1454 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1455 unsigned Opc = ISD::SHL; 1456 int Diff = ShAmt-C1; 1457 if (Diff < 0) { 1458 Diff = -Diff; 1459 Opc = ISD::SRL; 1460 } 1461 1462 SDValue NewSA = 1463 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1464 EVT VT = Op.getValueType(); 1465 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1466 InOp.getOperand(0), NewSA)); 1467 } 1468 } 1469 1470 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 1471 KnownZero, KnownOne, TLO, Depth+1)) 1472 return true; 1473 1474 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 1475 // are not demanded. This will likely allow the anyext to be folded away. 1476 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 1477 SDValue InnerOp = InOp.getNode()->getOperand(0); 1478 EVT InnerVT = InnerOp.getValueType(); 1479 unsigned InnerBits = InnerVT.getSizeInBits(); 1480 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 && 1481 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1482 EVT ShTy = getShiftAmountTy(InnerVT); 1483 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 1484 ShTy = InnerVT; 1485 SDValue NarrowShl = 1486 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1487 TLO.DAG.getConstant(ShAmt, ShTy)); 1488 return 1489 TLO.CombineTo(Op, 1490 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 1491 NarrowShl)); 1492 } 1493 } 1494 1495 KnownZero <<= SA->getZExtValue(); 1496 KnownOne <<= SA->getZExtValue(); 1497 // low bits known zero. 1498 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1499 } 1500 break; 1501 case ISD::SRL: 1502 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1503 EVT VT = Op.getValueType(); 1504 unsigned ShAmt = SA->getZExtValue(); 1505 unsigned VTSize = VT.getSizeInBits(); 1506 SDValue InOp = Op.getOperand(0); 1507 1508 // If the shift count is an invalid immediate, don't do anything. 1509 if (ShAmt >= BitWidth) 1510 break; 1511 1512 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1513 // single shift. We can do this if the top bits (which are shifted out) 1514 // are never demanded. 1515 if (InOp.getOpcode() == ISD::SHL && 1516 isa<ConstantSDNode>(InOp.getOperand(1))) { 1517 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1518 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1519 unsigned Opc = ISD::SRL; 1520 int Diff = ShAmt-C1; 1521 if (Diff < 0) { 1522 Diff = -Diff; 1523 Opc = ISD::SHL; 1524 } 1525 1526 SDValue NewSA = 1527 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1528 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1529 InOp.getOperand(0), NewSA)); 1530 } 1531 } 1532 1533 // Compute the new bits that are at the top now. 1534 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1535 KnownZero, KnownOne, TLO, Depth+1)) 1536 return true; 1537 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1538 KnownZero = KnownZero.lshr(ShAmt); 1539 KnownOne = KnownOne.lshr(ShAmt); 1540 1541 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1542 KnownZero |= HighBits; // High bits known zero. 1543 } 1544 break; 1545 case ISD::SRA: 1546 // If this is an arithmetic shift right and only the low-bit is set, we can 1547 // always convert this into a logical shr, even if the shift amount is 1548 // variable. The low bit of the shift cannot be an input sign bit unless 1549 // the shift amount is >= the size of the datatype, which is undefined. 1550 if (NewMask == 1) 1551 return TLO.CombineTo(Op, 1552 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1553 Op.getOperand(0), Op.getOperand(1))); 1554 1555 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1556 EVT VT = Op.getValueType(); 1557 unsigned ShAmt = SA->getZExtValue(); 1558 1559 // If the shift count is an invalid immediate, don't do anything. 1560 if (ShAmt >= BitWidth) 1561 break; 1562 1563 APInt InDemandedMask = (NewMask << ShAmt); 1564 1565 // If any of the demanded bits are produced by the sign extension, we also 1566 // demand the input sign bit. 1567 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1568 if (HighBits.intersects(NewMask)) 1569 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1570 1571 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1572 KnownZero, KnownOne, TLO, Depth+1)) 1573 return true; 1574 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1575 KnownZero = KnownZero.lshr(ShAmt); 1576 KnownOne = KnownOne.lshr(ShAmt); 1577 1578 // Handle the sign bit, adjusted to where it is now in the mask. 1579 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1580 1581 // If the input sign bit is known to be zero, or if none of the top bits 1582 // are demanded, turn this into an unsigned shift right. 1583 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1584 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1585 Op.getOperand(0), 1586 Op.getOperand(1))); 1587 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1588 KnownOne |= HighBits; 1589 } 1590 } 1591 break; 1592 case ISD::SIGN_EXTEND_INREG: { 1593 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1594 1595 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1); 1596 // If we only care about the highest bit, don't bother shifting right. 1597 if (MsbMask == DemandedMask) { 1598 unsigned ShAmt = ExVT.getScalarType().getSizeInBits(); 1599 SDValue InOp = Op.getOperand(0); 1600 1601 // Compute the correct shift amount type, which must be getShiftAmountTy 1602 // for scalar types after legalization. 1603 EVT ShiftAmtTy = Op.getValueType(); 1604 if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) 1605 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy); 1606 1607 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy); 1608 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1609 Op.getValueType(), InOp, ShiftAmt)); 1610 } 1611 1612 // Sign extension. Compute the demanded bits in the result that are not 1613 // present in the input. 1614 APInt NewBits = 1615 APInt::getHighBitsSet(BitWidth, 1616 BitWidth - ExVT.getScalarType().getSizeInBits()); 1617 1618 // If none of the extended bits are demanded, eliminate the sextinreg. 1619 if ((NewBits & NewMask) == 0) 1620 return TLO.CombineTo(Op, Op.getOperand(0)); 1621 1622 APInt InSignBit = 1623 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth); 1624 APInt InputDemandedBits = 1625 APInt::getLowBitsSet(BitWidth, 1626 ExVT.getScalarType().getSizeInBits()) & 1627 NewMask; 1628 1629 // Since the sign extended bits are demanded, we know that the sign 1630 // bit is demanded. 1631 InputDemandedBits |= InSignBit; 1632 1633 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1634 KnownZero, KnownOne, TLO, Depth+1)) 1635 return true; 1636 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1637 1638 // If the sign bit of the input is known set or clear, then we know the 1639 // top bits of the result. 1640 1641 // If the input sign bit is known zero, convert this into a zero extension. 1642 if (KnownZero.intersects(InSignBit)) 1643 return TLO.CombineTo(Op, 1644 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT)); 1645 1646 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1647 KnownOne |= NewBits; 1648 KnownZero &= ~NewBits; 1649 } else { // Input sign bit unknown 1650 KnownZero &= ~NewBits; 1651 KnownOne &= ~NewBits; 1652 } 1653 break; 1654 } 1655 case ISD::ZERO_EXTEND: { 1656 unsigned OperandBitWidth = 1657 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1658 APInt InMask = NewMask.trunc(OperandBitWidth); 1659 1660 // If none of the top bits are demanded, convert this into an any_extend. 1661 APInt NewBits = 1662 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1663 if (!NewBits.intersects(NewMask)) 1664 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1665 Op.getValueType(), 1666 Op.getOperand(0))); 1667 1668 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1669 KnownZero, KnownOne, TLO, Depth+1)) 1670 return true; 1671 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1672 KnownZero = KnownZero.zext(BitWidth); 1673 KnownOne = KnownOne.zext(BitWidth); 1674 KnownZero |= NewBits; 1675 break; 1676 } 1677 case ISD::SIGN_EXTEND: { 1678 EVT InVT = Op.getOperand(0).getValueType(); 1679 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1680 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1681 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1682 APInt NewBits = ~InMask & NewMask; 1683 1684 // If none of the top bits are demanded, convert this into an any_extend. 1685 if (NewBits == 0) 1686 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1687 Op.getValueType(), 1688 Op.getOperand(0))); 1689 1690 // Since some of the sign extended bits are demanded, we know that the sign 1691 // bit is demanded. 1692 APInt InDemandedBits = InMask & NewMask; 1693 InDemandedBits |= InSignBit; 1694 InDemandedBits = InDemandedBits.trunc(InBits); 1695 1696 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1697 KnownOne, TLO, Depth+1)) 1698 return true; 1699 KnownZero = KnownZero.zext(BitWidth); 1700 KnownOne = KnownOne.zext(BitWidth); 1701 1702 // If the sign bit is known zero, convert this to a zero extend. 1703 if (KnownZero.intersects(InSignBit)) 1704 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1705 Op.getValueType(), 1706 Op.getOperand(0))); 1707 1708 // If the sign bit is known one, the top bits match. 1709 if (KnownOne.intersects(InSignBit)) { 1710 KnownOne |= NewBits; 1711 assert((KnownZero & NewBits) == 0); 1712 } else { // Otherwise, top bits aren't known. 1713 assert((KnownOne & NewBits) == 0); 1714 assert((KnownZero & NewBits) == 0); 1715 } 1716 break; 1717 } 1718 case ISD::ANY_EXTEND: { 1719 unsigned OperandBitWidth = 1720 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1721 APInt InMask = NewMask.trunc(OperandBitWidth); 1722 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1723 KnownZero, KnownOne, TLO, Depth+1)) 1724 return true; 1725 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1726 KnownZero = KnownZero.zext(BitWidth); 1727 KnownOne = KnownOne.zext(BitWidth); 1728 break; 1729 } 1730 case ISD::TRUNCATE: { 1731 // Simplify the input, using demanded bit information, and compute the known 1732 // zero/one bits live out. 1733 unsigned OperandBitWidth = 1734 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1735 APInt TruncMask = NewMask.zext(OperandBitWidth); 1736 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1737 KnownZero, KnownOne, TLO, Depth+1)) 1738 return true; 1739 KnownZero = KnownZero.trunc(BitWidth); 1740 KnownOne = KnownOne.trunc(BitWidth); 1741 1742 // If the input is only used by this truncate, see if we can shrink it based 1743 // on the known demanded bits. 1744 if (Op.getOperand(0).getNode()->hasOneUse()) { 1745 SDValue In = Op.getOperand(0); 1746 switch (In.getOpcode()) { 1747 default: break; 1748 case ISD::SRL: 1749 // Shrink SRL by a constant if none of the high bits shifted in are 1750 // demanded. 1751 if (TLO.LegalTypes() && 1752 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1753 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1754 // undesirable. 1755 break; 1756 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1757 if (!ShAmt) 1758 break; 1759 SDValue Shift = In.getOperand(1); 1760 if (TLO.LegalTypes()) { 1761 uint64_t ShVal = ShAmt->getZExtValue(); 1762 Shift = 1763 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType())); 1764 } 1765 1766 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1767 OperandBitWidth - BitWidth); 1768 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 1769 1770 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1771 // None of the shifted in bits are needed. Add a truncate of the 1772 // shift input, then shift it. 1773 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1774 Op.getValueType(), 1775 In.getOperand(0)); 1776 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1777 Op.getValueType(), 1778 NewTrunc, 1779 Shift)); 1780 } 1781 break; 1782 } 1783 } 1784 1785 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1786 break; 1787 } 1788 case ISD::AssertZext: { 1789 // AssertZext demands all of the high bits, plus any of the low bits 1790 // demanded by its users. 1791 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1792 APInt InMask = APInt::getLowBitsSet(BitWidth, 1793 VT.getSizeInBits()); 1794 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask, 1795 KnownZero, KnownOne, TLO, Depth+1)) 1796 return true; 1797 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1798 1799 KnownZero |= ~InMask & NewMask; 1800 break; 1801 } 1802 case ISD::BITCAST: 1803 // If this is an FP->Int bitcast and if the sign bit is the only 1804 // thing demanded, turn this into a FGETSIGN. 1805 if (!TLO.LegalOperations() && 1806 !Op.getValueType().isVector() && 1807 !Op.getOperand(0).getValueType().isVector() && 1808 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && 1809 Op.getOperand(0).getValueType().isFloatingPoint()) { 1810 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); 1811 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); 1812 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { 1813 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; 1814 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1815 // place. We expect the SHL to be eliminated by other optimizations. 1816 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); 1817 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); 1818 if (!OpVTLegal && OpVTSizeInBits > 32) 1819 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); 1820 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1821 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); 1822 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1823 Op.getValueType(), 1824 Sign, ShAmt)); 1825 } 1826 } 1827 break; 1828 case ISD::ADD: 1829 case ISD::MUL: 1830 case ISD::SUB: { 1831 // Add, Sub, and Mul don't demand any bits in positions beyond that 1832 // of the highest bit demanded of them. 1833 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1834 BitWidth - NewMask.countLeadingZeros()); 1835 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1836 KnownOne2, TLO, Depth+1)) 1837 return true; 1838 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1839 KnownOne2, TLO, Depth+1)) 1840 return true; 1841 // See if the operation should be performed at a smaller bit width. 1842 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1843 return true; 1844 } 1845 // FALL THROUGH 1846 default: 1847 // Just use ComputeMaskedBits to compute output bits. 1848 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 1849 break; 1850 } 1851 1852 // If we know the value of all of the demanded bits, return this as a 1853 // constant. 1854 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1855 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1856 1857 return false; 1858 } 1859 1860 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 1861 /// in Mask are known to be either zero or one and return them in the 1862 /// KnownZero/KnownOne bitsets. 1863 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1864 APInt &KnownZero, 1865 APInt &KnownOne, 1866 const SelectionDAG &DAG, 1867 unsigned Depth) const { 1868 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1869 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1870 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1871 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1872 "Should use MaskedValueIsZero if you don't know whether Op" 1873 " is a target node!"); 1874 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); 1875 } 1876 1877 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 1878 /// targets that want to expose additional information about sign bits to the 1879 /// DAG Combiner. 1880 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1881 unsigned Depth) const { 1882 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1883 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1884 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1885 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1886 "Should use ComputeNumSignBits if you don't know whether Op" 1887 " is a target node!"); 1888 return 1; 1889 } 1890 1891 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1892 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1893 /// determine which bit is set. 1894 /// 1895 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1896 // A left-shift of a constant one will have exactly one bit set, because 1897 // shifting the bit off the end is undefined. 1898 if (Val.getOpcode() == ISD::SHL) 1899 if (ConstantSDNode *C = 1900 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1901 if (C->getAPIntValue() == 1) 1902 return true; 1903 1904 // Similarly, a right-shift of a constant sign-bit will have exactly 1905 // one bit set. 1906 if (Val.getOpcode() == ISD::SRL) 1907 if (ConstantSDNode *C = 1908 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1909 if (C->getAPIntValue().isSignBit()) 1910 return true; 1911 1912 // More could be done here, though the above checks are enough 1913 // to handle some common cases. 1914 1915 // Fall back to ComputeMaskedBits to catch other known cases. 1916 EVT OpVT = Val.getValueType(); 1917 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1918 APInt KnownZero, KnownOne; 1919 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne); 1920 return (KnownZero.countPopulation() == BitWidth - 1) && 1921 (KnownOne.countPopulation() == 1); 1922 } 1923 1924 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 1925 /// and cc. If it is unable to simplify it, return a null SDValue. 1926 SDValue 1927 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1928 ISD::CondCode Cond, bool foldBooleans, 1929 DAGCombinerInfo &DCI, DebugLoc dl) const { 1930 SelectionDAG &DAG = DCI.DAG; 1931 1932 // These setcc operations always fold. 1933 switch (Cond) { 1934 default: break; 1935 case ISD::SETFALSE: 1936 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1937 case ISD::SETTRUE: 1938 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1939 } 1940 1941 // Ensure that the constant occurs on the RHS, and fold constant 1942 // comparisons. 1943 if (isa<ConstantSDNode>(N0.getNode())) 1944 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1945 1946 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1947 const APInt &C1 = N1C->getAPIntValue(); 1948 1949 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1950 // equality comparison, then we're just comparing whether X itself is 1951 // zero. 1952 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1953 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1954 N0.getOperand(1).getOpcode() == ISD::Constant) { 1955 const APInt &ShAmt 1956 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1957 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1958 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1959 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1960 // (srl (ctlz x), 5) == 0 -> X != 0 1961 // (srl (ctlz x), 5) != 1 -> X != 0 1962 Cond = ISD::SETNE; 1963 } else { 1964 // (srl (ctlz x), 5) != 0 -> X == 0 1965 // (srl (ctlz x), 5) == 1 -> X == 0 1966 Cond = ISD::SETEQ; 1967 } 1968 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1969 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1970 Zero, Cond); 1971 } 1972 } 1973 1974 SDValue CTPOP = N0; 1975 // Look through truncs that don't change the value of a ctpop. 1976 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 1977 CTPOP = N0.getOperand(0); 1978 1979 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 1980 (N0 == CTPOP || N0.getValueType().getSizeInBits() > 1981 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 1982 EVT CTVT = CTPOP.getValueType(); 1983 SDValue CTOp = CTPOP.getOperand(0); 1984 1985 // (ctpop x) u< 2 -> (x & x-1) == 0 1986 // (ctpop x) u> 1 -> (x & x-1) != 0 1987 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1988 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 1989 DAG.getConstant(1, CTVT)); 1990 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 1991 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1992 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 1993 } 1994 1995 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 1996 } 1997 1998 // (zext x) == C --> x == (trunc C) 1999 if (DCI.isBeforeLegalize() && N0->hasOneUse() && 2000 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2001 unsigned MinBits = N0.getValueSizeInBits(); 2002 SDValue PreZExt; 2003 if (N0->getOpcode() == ISD::ZERO_EXTEND) { 2004 // ZExt 2005 MinBits = N0->getOperand(0).getValueSizeInBits(); 2006 PreZExt = N0->getOperand(0); 2007 } else if (N0->getOpcode() == ISD::AND) { 2008 // DAGCombine turns costly ZExts into ANDs 2009 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) 2010 if ((C->getAPIntValue()+1).isPowerOf2()) { 2011 MinBits = C->getAPIntValue().countTrailingOnes(); 2012 PreZExt = N0->getOperand(0); 2013 } 2014 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) { 2015 // ZEXTLOAD 2016 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { 2017 MinBits = LN0->getMemoryVT().getSizeInBits(); 2018 PreZExt = N0; 2019 } 2020 } 2021 2022 // Make sure we're not loosing bits from the constant. 2023 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) { 2024 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); 2025 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { 2026 // Will get folded away. 2027 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt); 2028 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT); 2029 return DAG.getSetCC(dl, VT, Trunc, C, Cond); 2030 } 2031 } 2032 } 2033 2034 // If the LHS is '(and load, const)', the RHS is 0, 2035 // the test is for equality or unsigned, and all 1 bits of the const are 2036 // in the same partial word, see if we can shorten the load. 2037 if (DCI.isBeforeLegalize() && 2038 N0.getOpcode() == ISD::AND && C1 == 0 && 2039 N0.getNode()->hasOneUse() && 2040 isa<LoadSDNode>(N0.getOperand(0)) && 2041 N0.getOperand(0).getNode()->hasOneUse() && 2042 isa<ConstantSDNode>(N0.getOperand(1))) { 2043 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 2044 APInt bestMask; 2045 unsigned bestWidth = 0, bestOffset = 0; 2046 if (!Lod->isVolatile() && Lod->isUnindexed()) { 2047 unsigned origWidth = N0.getValueType().getSizeInBits(); 2048 unsigned maskWidth = origWidth; 2049 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 2050 // 8 bits, but have to be careful... 2051 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 2052 origWidth = Lod->getMemoryVT().getSizeInBits(); 2053 const APInt &Mask = 2054 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2055 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 2056 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 2057 for (unsigned offset=0; offset<origWidth/width; offset++) { 2058 if ((newMask & Mask) == Mask) { 2059 if (!TD->isLittleEndian()) 2060 bestOffset = (origWidth/width - offset - 1) * (width/8); 2061 else 2062 bestOffset = (uint64_t)offset * (width/8); 2063 bestMask = Mask.lshr(offset * (width/8) * 8); 2064 bestWidth = width; 2065 break; 2066 } 2067 newMask = newMask << width; 2068 } 2069 } 2070 } 2071 if (bestWidth) { 2072 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); 2073 if (newVT.isRound()) { 2074 EVT PtrType = Lod->getOperand(1).getValueType(); 2075 SDValue Ptr = Lod->getBasePtr(); 2076 if (bestOffset != 0) 2077 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 2078 DAG.getConstant(bestOffset, PtrType)); 2079 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 2080 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 2081 Lod->getPointerInfo().getWithOffset(bestOffset), 2082 false, false, false, NewAlign); 2083 return DAG.getSetCC(dl, VT, 2084 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 2085 DAG.getConstant(bestMask.trunc(bestWidth), 2086 newVT)), 2087 DAG.getConstant(0LL, newVT), Cond); 2088 } 2089 } 2090 } 2091 2092 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2093 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2094 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 2095 2096 // If the comparison constant has bits in the upper part, the 2097 // zero-extended value could never match. 2098 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 2099 C1.getBitWidth() - InSize))) { 2100 switch (Cond) { 2101 case ISD::SETUGT: 2102 case ISD::SETUGE: 2103 case ISD::SETEQ: return DAG.getConstant(0, VT); 2104 case ISD::SETULT: 2105 case ISD::SETULE: 2106 case ISD::SETNE: return DAG.getConstant(1, VT); 2107 case ISD::SETGT: 2108 case ISD::SETGE: 2109 // True if the sign bit of C1 is set. 2110 return DAG.getConstant(C1.isNegative(), VT); 2111 case ISD::SETLT: 2112 case ISD::SETLE: 2113 // True if the sign bit of C1 isn't set. 2114 return DAG.getConstant(C1.isNonNegative(), VT); 2115 default: 2116 break; 2117 } 2118 } 2119 2120 // Otherwise, we can perform the comparison with the low bits. 2121 switch (Cond) { 2122 case ISD::SETEQ: 2123 case ISD::SETNE: 2124 case ISD::SETUGT: 2125 case ISD::SETUGE: 2126 case ISD::SETULT: 2127 case ISD::SETULE: { 2128 EVT newVT = N0.getOperand(0).getValueType(); 2129 if (DCI.isBeforeLegalizeOps() || 2130 (isOperationLegal(ISD::SETCC, newVT) && 2131 getCondCodeAction(Cond, newVT)==Legal)) 2132 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2133 DAG.getConstant(C1.trunc(InSize), newVT), 2134 Cond); 2135 break; 2136 } 2137 default: 2138 break; // todo, be more careful with signed comparisons 2139 } 2140 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2141 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2142 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2143 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 2144 EVT ExtDstTy = N0.getValueType(); 2145 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 2146 2147 // If the constant doesn't fit into the number of bits for the source of 2148 // the sign extension, it is impossible for both sides to be equal. 2149 if (C1.getMinSignedBits() > ExtSrcTyBits) 2150 return DAG.getConstant(Cond == ISD::SETNE, VT); 2151 2152 SDValue ZextOp; 2153 EVT Op0Ty = N0.getOperand(0).getValueType(); 2154 if (Op0Ty == ExtSrcTy) { 2155 ZextOp = N0.getOperand(0); 2156 } else { 2157 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 2158 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 2159 DAG.getConstant(Imm, Op0Ty)); 2160 } 2161 if (!DCI.isCalledByLegalizer()) 2162 DCI.AddToWorklist(ZextOp.getNode()); 2163 // Otherwise, make this a use of a zext. 2164 return DAG.getSetCC(dl, VT, ZextOp, 2165 DAG.getConstant(C1 & APInt::getLowBitsSet( 2166 ExtDstTyBits, 2167 ExtSrcTyBits), 2168 ExtDstTy), 2169 Cond); 2170 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 2171 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2172 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 2173 if (N0.getOpcode() == ISD::SETCC && 2174 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 2175 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 2176 if (TrueWhenTrue) 2177 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 2178 // Invert the condition. 2179 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 2180 CC = ISD::getSetCCInverse(CC, 2181 N0.getOperand(0).getValueType().isInteger()); 2182 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 2183 } 2184 2185 if ((N0.getOpcode() == ISD::XOR || 2186 (N0.getOpcode() == ISD::AND && 2187 N0.getOperand(0).getOpcode() == ISD::XOR && 2188 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2189 isa<ConstantSDNode>(N0.getOperand(1)) && 2190 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 2191 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 2192 // can only do this if the top bits are known zero. 2193 unsigned BitWidth = N0.getValueSizeInBits(); 2194 if (DAG.MaskedValueIsZero(N0, 2195 APInt::getHighBitsSet(BitWidth, 2196 BitWidth-1))) { 2197 // Okay, get the un-inverted input value. 2198 SDValue Val; 2199 if (N0.getOpcode() == ISD::XOR) 2200 Val = N0.getOperand(0); 2201 else { 2202 assert(N0.getOpcode() == ISD::AND && 2203 N0.getOperand(0).getOpcode() == ISD::XOR); 2204 // ((X^1)&1)^1 -> X & 1 2205 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 2206 N0.getOperand(0).getOperand(0), 2207 N0.getOperand(1)); 2208 } 2209 2210 return DAG.getSetCC(dl, VT, Val, N1, 2211 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2212 } 2213 } else if (N1C->getAPIntValue() == 1 && 2214 (VT == MVT::i1 || 2215 getBooleanContents(false) == ZeroOrOneBooleanContent)) { 2216 SDValue Op0 = N0; 2217 if (Op0.getOpcode() == ISD::TRUNCATE) 2218 Op0 = Op0.getOperand(0); 2219 2220 if ((Op0.getOpcode() == ISD::XOR) && 2221 Op0.getOperand(0).getOpcode() == ISD::SETCC && 2222 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 2223 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 2224 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 2225 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 2226 Cond); 2227 } else if (Op0.getOpcode() == ISD::AND && 2228 isa<ConstantSDNode>(Op0.getOperand(1)) && 2229 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 2230 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 2231 if (Op0.getValueType().bitsGT(VT)) 2232 Op0 = DAG.getNode(ISD::AND, dl, VT, 2233 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 2234 DAG.getConstant(1, VT)); 2235 else if (Op0.getValueType().bitsLT(VT)) 2236 Op0 = DAG.getNode(ISD::AND, dl, VT, 2237 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 2238 DAG.getConstant(1, VT)); 2239 2240 return DAG.getSetCC(dl, VT, Op0, 2241 DAG.getConstant(0, Op0.getValueType()), 2242 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2243 } 2244 } 2245 } 2246 2247 APInt MinVal, MaxVal; 2248 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 2249 if (ISD::isSignedIntSetCC(Cond)) { 2250 MinVal = APInt::getSignedMinValue(OperandBitSize); 2251 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 2252 } else { 2253 MinVal = APInt::getMinValue(OperandBitSize); 2254 MaxVal = APInt::getMaxValue(OperandBitSize); 2255 } 2256 2257 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2258 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2259 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2260 // X >= C0 --> X > (C0-1) 2261 return DAG.getSetCC(dl, VT, N0, 2262 DAG.getConstant(C1-1, N1.getValueType()), 2263 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2264 } 2265 2266 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2267 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2268 // X <= C0 --> X < (C0+1) 2269 return DAG.getSetCC(dl, VT, N0, 2270 DAG.getConstant(C1+1, N1.getValueType()), 2271 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2272 } 2273 2274 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2275 return DAG.getConstant(0, VT); // X < MIN --> false 2276 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2277 return DAG.getConstant(1, VT); // X >= MIN --> true 2278 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2279 return DAG.getConstant(0, VT); // X > MAX --> false 2280 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2281 return DAG.getConstant(1, VT); // X <= MAX --> true 2282 2283 // Canonicalize setgt X, Min --> setne X, Min 2284 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2285 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2286 // Canonicalize setlt X, Max --> setne X, Max 2287 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2288 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2289 2290 // If we have setult X, 1, turn it into seteq X, 0 2291 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2292 return DAG.getSetCC(dl, VT, N0, 2293 DAG.getConstant(MinVal, N0.getValueType()), 2294 ISD::SETEQ); 2295 // If we have setugt X, Max-1, turn it into seteq X, Max 2296 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2297 return DAG.getSetCC(dl, VT, N0, 2298 DAG.getConstant(MaxVal, N0.getValueType()), 2299 ISD::SETEQ); 2300 2301 // If we have "setcc X, C0", check to see if we can shrink the immediate 2302 // by changing cc. 2303 2304 // SETUGT X, SINTMAX -> SETLT X, 0 2305 if (Cond == ISD::SETUGT && 2306 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2307 return DAG.getSetCC(dl, VT, N0, 2308 DAG.getConstant(0, N1.getValueType()), 2309 ISD::SETLT); 2310 2311 // SETULT X, SINTMIN -> SETGT X, -1 2312 if (Cond == ISD::SETULT && 2313 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2314 SDValue ConstMinusOne = 2315 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2316 N1.getValueType()); 2317 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2318 } 2319 2320 // Fold bit comparisons when we can. 2321 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2322 (VT == N0.getValueType() || 2323 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2324 N0.getOpcode() == ISD::AND) 2325 if (ConstantSDNode *AndRHS = 2326 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2327 EVT ShiftTy = DCI.isBeforeLegalize() ? 2328 getPointerTy() : getShiftAmountTy(N0.getValueType()); 2329 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2330 // Perform the xform if the AND RHS is a single bit. 2331 if (AndRHS->getAPIntValue().isPowerOf2()) { 2332 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2333 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2334 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2335 } 2336 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2337 // (X & 8) == 8 --> (X & 8) >> 3 2338 // Perform the xform if C1 is a single bit. 2339 if (C1.isPowerOf2()) { 2340 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2341 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2342 DAG.getConstant(C1.logBase2(), ShiftTy))); 2343 } 2344 } 2345 } 2346 } 2347 2348 if (isa<ConstantFPSDNode>(N0.getNode())) { 2349 // Constant fold or commute setcc. 2350 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2351 if (O.getNode()) return O; 2352 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2353 // If the RHS of an FP comparison is a constant, simplify it away in 2354 // some cases. 2355 if (CFP->getValueAPF().isNaN()) { 2356 // If an operand is known to be a nan, we can fold it. 2357 switch (ISD::getUnorderedFlavor(Cond)) { 2358 default: llvm_unreachable("Unknown flavor!"); 2359 case 0: // Known false. 2360 return DAG.getConstant(0, VT); 2361 case 1: // Known true. 2362 return DAG.getConstant(1, VT); 2363 case 2: // Undefined. 2364 return DAG.getUNDEF(VT); 2365 } 2366 } 2367 2368 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2369 // constant if knowing that the operand is non-nan is enough. We prefer to 2370 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2371 // materialize 0.0. 2372 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2373 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2374 2375 // If the condition is not legal, see if we can find an equivalent one 2376 // which is legal. 2377 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2378 // If the comparison was an awkward floating-point == or != and one of 2379 // the comparison operands is infinity or negative infinity, convert the 2380 // condition to a less-awkward <= or >=. 2381 if (CFP->getValueAPF().isInfinity()) { 2382 if (CFP->getValueAPF().isNegative()) { 2383 if (Cond == ISD::SETOEQ && 2384 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2385 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2386 if (Cond == ISD::SETUEQ && 2387 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2388 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2389 if (Cond == ISD::SETUNE && 2390 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2391 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2392 if (Cond == ISD::SETONE && 2393 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2394 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2395 } else { 2396 if (Cond == ISD::SETOEQ && 2397 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2398 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2399 if (Cond == ISD::SETUEQ && 2400 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2401 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2402 if (Cond == ISD::SETUNE && 2403 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2404 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2405 if (Cond == ISD::SETONE && 2406 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2407 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2408 } 2409 } 2410 } 2411 } 2412 2413 if (N0 == N1) { 2414 // We can always fold X == X for integer setcc's. 2415 if (N0.getValueType().isInteger()) { 2416 switch (getBooleanContents(N0.getValueType().isVector())) { 2417 case UndefinedBooleanContent: 2418 case ZeroOrOneBooleanContent: 2419 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2420 case ZeroOrNegativeOneBooleanContent: 2421 return DAG.getConstant(ISD::isTrueWhenEqual(Cond) ? -1 : 0, VT); 2422 } 2423 } 2424 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2425 if (UOF == 2) // FP operators that are undefined on NaNs. 2426 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2427 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2428 return DAG.getConstant(UOF, VT); 2429 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2430 // if it is not already. 2431 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2432 if (NewCond != Cond) 2433 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2434 } 2435 2436 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2437 N0.getValueType().isInteger()) { 2438 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2439 N0.getOpcode() == ISD::XOR) { 2440 // Simplify (X+Y) == (X+Z) --> Y == Z 2441 if (N0.getOpcode() == N1.getOpcode()) { 2442 if (N0.getOperand(0) == N1.getOperand(0)) 2443 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2444 if (N0.getOperand(1) == N1.getOperand(1)) 2445 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2446 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2447 // If X op Y == Y op X, try other combinations. 2448 if (N0.getOperand(0) == N1.getOperand(1)) 2449 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2450 Cond); 2451 if (N0.getOperand(1) == N1.getOperand(0)) 2452 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2453 Cond); 2454 } 2455 } 2456 2457 // If RHS is a legal immediate value for a compare instruction, we need 2458 // to be careful about increasing register pressure needlessly. 2459 bool LegalRHSImm = false; 2460 2461 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2462 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2463 // Turn (X+C1) == C2 --> X == C2-C1 2464 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2465 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2466 DAG.getConstant(RHSC->getAPIntValue()- 2467 LHSR->getAPIntValue(), 2468 N0.getValueType()), Cond); 2469 } 2470 2471 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2472 if (N0.getOpcode() == ISD::XOR) 2473 // If we know that all of the inverted bits are zero, don't bother 2474 // performing the inversion. 2475 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2476 return 2477 DAG.getSetCC(dl, VT, N0.getOperand(0), 2478 DAG.getConstant(LHSR->getAPIntValue() ^ 2479 RHSC->getAPIntValue(), 2480 N0.getValueType()), 2481 Cond); 2482 } 2483 2484 // Turn (C1-X) == C2 --> X == C1-C2 2485 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2486 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2487 return 2488 DAG.getSetCC(dl, VT, N0.getOperand(1), 2489 DAG.getConstant(SUBC->getAPIntValue() - 2490 RHSC->getAPIntValue(), 2491 N0.getValueType()), 2492 Cond); 2493 } 2494 } 2495 2496 // Could RHSC fold directly into a compare? 2497 if (RHSC->getValueType(0).getSizeInBits() <= 64) 2498 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue()); 2499 } 2500 2501 // Simplify (X+Z) == X --> Z == 0 2502 // Don't do this if X is an immediate that can fold into a cmp 2503 // instruction and X+Z has other uses. It could be an induction variable 2504 // chain, and the transform would increase register pressure. 2505 if (!LegalRHSImm || N0.getNode()->hasOneUse()) { 2506 if (N0.getOperand(0) == N1) 2507 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2508 DAG.getConstant(0, N0.getValueType()), Cond); 2509 if (N0.getOperand(1) == N1) { 2510 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2511 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2512 DAG.getConstant(0, N0.getValueType()), Cond); 2513 else if (N0.getNode()->hasOneUse()) { 2514 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2515 // (Z-X) == X --> Z == X<<1 2516 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, 2517 DAG.getConstant(1, getShiftAmountTy(N1.getValueType()))); 2518 if (!DCI.isCalledByLegalizer()) 2519 DCI.AddToWorklist(SH.getNode()); 2520 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2521 } 2522 } 2523 } 2524 } 2525 2526 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2527 N1.getOpcode() == ISD::XOR) { 2528 // Simplify X == (X+Z) --> Z == 0 2529 if (N1.getOperand(0) == N0) { 2530 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2531 DAG.getConstant(0, N1.getValueType()), Cond); 2532 } else if (N1.getOperand(1) == N0) { 2533 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2534 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2535 DAG.getConstant(0, N1.getValueType()), Cond); 2536 } else if (N1.getNode()->hasOneUse()) { 2537 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2538 // X == (Z-X) --> X<<1 == Z 2539 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2540 DAG.getConstant(1, getShiftAmountTy(N0.getValueType()))); 2541 if (!DCI.isCalledByLegalizer()) 2542 DCI.AddToWorklist(SH.getNode()); 2543 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2544 } 2545 } 2546 } 2547 2548 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2549 // Note that where y is variable and is known to have at most 2550 // one bit set (for example, if it is z&1) we cannot do this; 2551 // the expressions are not equivalent when y==0. 2552 if (N0.getOpcode() == ISD::AND) 2553 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2554 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2555 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2556 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2557 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2558 } 2559 } 2560 if (N1.getOpcode() == ISD::AND) 2561 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2562 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2563 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2564 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2565 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2566 } 2567 } 2568 } 2569 2570 // Fold away ALL boolean setcc's. 2571 SDValue Temp; 2572 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2573 switch (Cond) { 2574 default: llvm_unreachable("Unknown integer setcc!"); 2575 case ISD::SETEQ: // X == Y -> ~(X^Y) 2576 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2577 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2578 if (!DCI.isCalledByLegalizer()) 2579 DCI.AddToWorklist(Temp.getNode()); 2580 break; 2581 case ISD::SETNE: // X != Y --> (X^Y) 2582 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2583 break; 2584 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2585 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2586 Temp = DAG.getNOT(dl, N0, MVT::i1); 2587 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2588 if (!DCI.isCalledByLegalizer()) 2589 DCI.AddToWorklist(Temp.getNode()); 2590 break; 2591 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2592 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2593 Temp = DAG.getNOT(dl, N1, MVT::i1); 2594 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2595 if (!DCI.isCalledByLegalizer()) 2596 DCI.AddToWorklist(Temp.getNode()); 2597 break; 2598 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2599 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2600 Temp = DAG.getNOT(dl, N0, MVT::i1); 2601 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2602 if (!DCI.isCalledByLegalizer()) 2603 DCI.AddToWorklist(Temp.getNode()); 2604 break; 2605 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2606 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2607 Temp = DAG.getNOT(dl, N1, MVT::i1); 2608 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2609 break; 2610 } 2611 if (VT != MVT::i1) { 2612 if (!DCI.isCalledByLegalizer()) 2613 DCI.AddToWorklist(N0.getNode()); 2614 // FIXME: If running after legalize, we probably can't do this. 2615 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2616 } 2617 return N0; 2618 } 2619 2620 // Could not fold it. 2621 return SDValue(); 2622 } 2623 2624 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2625 /// node is a GlobalAddress + offset. 2626 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 2627 int64_t &Offset) const { 2628 if (isa<GlobalAddressSDNode>(N)) { 2629 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2630 GA = GASD->getGlobal(); 2631 Offset += GASD->getOffset(); 2632 return true; 2633 } 2634 2635 if (N->getOpcode() == ISD::ADD) { 2636 SDValue N1 = N->getOperand(0); 2637 SDValue N2 = N->getOperand(1); 2638 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2639 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2640 if (V) { 2641 Offset += V->getSExtValue(); 2642 return true; 2643 } 2644 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2645 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2646 if (V) { 2647 Offset += V->getSExtValue(); 2648 return true; 2649 } 2650 } 2651 } 2652 2653 return false; 2654 } 2655 2656 2657 SDValue TargetLowering:: 2658 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2659 // Default implementation: no optimization. 2660 return SDValue(); 2661 } 2662 2663 //===----------------------------------------------------------------------===// 2664 // Inline Assembler Implementation Methods 2665 //===----------------------------------------------------------------------===// 2666 2667 2668 TargetLowering::ConstraintType 2669 TargetLowering::getConstraintType(const std::string &Constraint) const { 2670 if (Constraint.size() == 1) { 2671 switch (Constraint[0]) { 2672 default: break; 2673 case 'r': return C_RegisterClass; 2674 case 'm': // memory 2675 case 'o': // offsetable 2676 case 'V': // not offsetable 2677 return C_Memory; 2678 case 'i': // Simple Integer or Relocatable Constant 2679 case 'n': // Simple Integer 2680 case 'E': // Floating Point Constant 2681 case 'F': // Floating Point Constant 2682 case 's': // Relocatable Constant 2683 case 'p': // Address. 2684 case 'X': // Allow ANY value. 2685 case 'I': // Target registers. 2686 case 'J': 2687 case 'K': 2688 case 'L': 2689 case 'M': 2690 case 'N': 2691 case 'O': 2692 case 'P': 2693 case '<': 2694 case '>': 2695 return C_Other; 2696 } 2697 } 2698 2699 if (Constraint.size() > 1 && Constraint[0] == '{' && 2700 Constraint[Constraint.size()-1] == '}') 2701 return C_Register; 2702 return C_Unknown; 2703 } 2704 2705 /// LowerXConstraint - try to replace an X constraint, which matches anything, 2706 /// with another that has more specific requirements based on the type of the 2707 /// corresponding operand. 2708 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2709 if (ConstraintVT.isInteger()) 2710 return "r"; 2711 if (ConstraintVT.isFloatingPoint()) 2712 return "f"; // works for many targets 2713 return 0; 2714 } 2715 2716 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2717 /// vector. If it is invalid, don't add anything to Ops. 2718 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2719 std::string &Constraint, 2720 std::vector<SDValue> &Ops, 2721 SelectionDAG &DAG) const { 2722 2723 if (Constraint.length() > 1) return; 2724 2725 char ConstraintLetter = Constraint[0]; 2726 switch (ConstraintLetter) { 2727 default: break; 2728 case 'X': // Allows any operand; labels (basic block) use this. 2729 if (Op.getOpcode() == ISD::BasicBlock) { 2730 Ops.push_back(Op); 2731 return; 2732 } 2733 // fall through 2734 case 'i': // Simple Integer or Relocatable Constant 2735 case 'n': // Simple Integer 2736 case 's': { // Relocatable Constant 2737 // These operands are interested in values of the form (GV+C), where C may 2738 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2739 // is possible and fine if either GV or C are missing. 2740 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2741 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2742 2743 // If we have "(add GV, C)", pull out GV/C 2744 if (Op.getOpcode() == ISD::ADD) { 2745 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2746 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2747 if (C == 0 || GA == 0) { 2748 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2749 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2750 } 2751 if (C == 0 || GA == 0) 2752 C = 0, GA = 0; 2753 } 2754 2755 // If we find a valid operand, map to the TargetXXX version so that the 2756 // value itself doesn't get selected. 2757 if (GA) { // Either &GV or &GV+C 2758 if (ConstraintLetter != 'n') { 2759 int64_t Offs = GA->getOffset(); 2760 if (C) Offs += C->getZExtValue(); 2761 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2762 C ? C->getDebugLoc() : DebugLoc(), 2763 Op.getValueType(), Offs)); 2764 return; 2765 } 2766 } 2767 if (C) { // just C, no GV. 2768 // Simple constants are not allowed for 's'. 2769 if (ConstraintLetter != 's') { 2770 // gcc prints these as sign extended. Sign extend value to 64 bits 2771 // now; without this it would get ZExt'd later in 2772 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2773 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2774 MVT::i64)); 2775 return; 2776 } 2777 } 2778 break; 2779 } 2780 } 2781 } 2782 2783 std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2784 getRegForInlineAsmConstraint(const std::string &Constraint, 2785 EVT VT) const { 2786 if (Constraint[0] != '{') 2787 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2788 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2789 2790 // Remove the braces from around the name. 2791 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2792 2793 // Figure out which register class contains this reg. 2794 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2795 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2796 E = RI->regclass_end(); RCI != E; ++RCI) { 2797 const TargetRegisterClass *RC = *RCI; 2798 2799 // If none of the value types for this register class are valid, we 2800 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2801 if (!isLegalRC(RC)) 2802 continue; 2803 2804 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2805 I != E; ++I) { 2806 if (RegName.equals_lower(RI->getName(*I))) 2807 return std::make_pair(*I, RC); 2808 } 2809 } 2810 2811 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2812 } 2813 2814 //===----------------------------------------------------------------------===// 2815 // Constraint Selection. 2816 2817 /// isMatchingInputConstraint - Return true of this is an input operand that is 2818 /// a matching constraint like "4". 2819 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2820 assert(!ConstraintCode.empty() && "No known constraint!"); 2821 return isdigit(ConstraintCode[0]); 2822 } 2823 2824 /// getMatchedOperand - If this is an input matching constraint, this method 2825 /// returns the output operand it matches. 2826 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2827 assert(!ConstraintCode.empty() && "No known constraint!"); 2828 return atoi(ConstraintCode.c_str()); 2829 } 2830 2831 2832 /// ParseConstraints - Split up the constraint string from the inline 2833 /// assembly value into the specific constraints and their prefixes, 2834 /// and also tie in the associated operand values. 2835 /// If this returns an empty vector, and if the constraint string itself 2836 /// isn't empty, there was an error parsing. 2837 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2838 ImmutableCallSite CS) const { 2839 /// ConstraintOperands - Information about all of the constraints. 2840 AsmOperandInfoVector ConstraintOperands; 2841 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2842 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2843 2844 // Do a prepass over the constraints, canonicalizing them, and building up the 2845 // ConstraintOperands list. 2846 InlineAsm::ConstraintInfoVector 2847 ConstraintInfos = IA->ParseConstraints(); 2848 2849 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2850 unsigned ResNo = 0; // ResNo - The result number of the next output. 2851 2852 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2853 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2854 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2855 2856 // Update multiple alternative constraint count. 2857 if (OpInfo.multipleAlternatives.size() > maCount) 2858 maCount = OpInfo.multipleAlternatives.size(); 2859 2860 OpInfo.ConstraintVT = MVT::Other; 2861 2862 // Compute the value type for each operand. 2863 switch (OpInfo.Type) { 2864 case InlineAsm::isOutput: 2865 // Indirect outputs just consume an argument. 2866 if (OpInfo.isIndirect) { 2867 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2868 break; 2869 } 2870 2871 // The return value of the call is this value. As such, there is no 2872 // corresponding argument. 2873 assert(!CS.getType()->isVoidTy() && 2874 "Bad inline asm!"); 2875 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 2876 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo)); 2877 } else { 2878 assert(ResNo == 0 && "Asm only has one result!"); 2879 OpInfo.ConstraintVT = getValueType(CS.getType()); 2880 } 2881 ++ResNo; 2882 break; 2883 case InlineAsm::isInput: 2884 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2885 break; 2886 case InlineAsm::isClobber: 2887 // Nothing to do. 2888 break; 2889 } 2890 2891 if (OpInfo.CallOperandVal) { 2892 llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2893 if (OpInfo.isIndirect) { 2894 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2895 if (!PtrTy) 2896 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2897 OpTy = PtrTy->getElementType(); 2898 } 2899 2900 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 2901 if (StructType *STy = dyn_cast<StructType>(OpTy)) 2902 if (STy->getNumElements() == 1) 2903 OpTy = STy->getElementType(0); 2904 2905 // If OpTy is not a single value, it may be a struct/union that we 2906 // can tile with integers. 2907 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2908 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 2909 switch (BitSize) { 2910 default: break; 2911 case 1: 2912 case 8: 2913 case 16: 2914 case 32: 2915 case 64: 2916 case 128: 2917 OpInfo.ConstraintVT = 2918 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2919 break; 2920 } 2921 } else if (dyn_cast<PointerType>(OpTy)) { 2922 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize()); 2923 } else { 2924 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true); 2925 } 2926 } 2927 } 2928 2929 // If we have multiple alternative constraints, select the best alternative. 2930 if (ConstraintInfos.size()) { 2931 if (maCount) { 2932 unsigned bestMAIndex = 0; 2933 int bestWeight = -1; 2934 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2935 int weight = -1; 2936 unsigned maIndex; 2937 // Compute the sums of the weights for each alternative, keeping track 2938 // of the best (highest weight) one so far. 2939 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2940 int weightSum = 0; 2941 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2942 cIndex != eIndex; ++cIndex) { 2943 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2944 if (OpInfo.Type == InlineAsm::isClobber) 2945 continue; 2946 2947 // If this is an output operand with a matching input operand, 2948 // look up the matching input. If their types mismatch, e.g. one 2949 // is an integer, the other is floating point, or their sizes are 2950 // different, flag it as an maCantMatch. 2951 if (OpInfo.hasMatchingInput()) { 2952 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2953 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2954 if ((OpInfo.ConstraintVT.isInteger() != 2955 Input.ConstraintVT.isInteger()) || 2956 (OpInfo.ConstraintVT.getSizeInBits() != 2957 Input.ConstraintVT.getSizeInBits())) { 2958 weightSum = -1; // Can't match. 2959 break; 2960 } 2961 } 2962 } 2963 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2964 if (weight == -1) { 2965 weightSum = -1; 2966 break; 2967 } 2968 weightSum += weight; 2969 } 2970 // Update best. 2971 if (weightSum > bestWeight) { 2972 bestWeight = weightSum; 2973 bestMAIndex = maIndex; 2974 } 2975 } 2976 2977 // Now select chosen alternative in each constraint. 2978 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2979 cIndex != eIndex; ++cIndex) { 2980 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2981 if (cInfo.Type == InlineAsm::isClobber) 2982 continue; 2983 cInfo.selectAlternative(bestMAIndex); 2984 } 2985 } 2986 } 2987 2988 // Check and hook up tied operands, choose constraint code to use. 2989 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2990 cIndex != eIndex; ++cIndex) { 2991 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2992 2993 // If this is an output operand with a matching input operand, look up the 2994 // matching input. If their types mismatch, e.g. one is an integer, the 2995 // other is floating point, or their sizes are different, flag it as an 2996 // error. 2997 if (OpInfo.hasMatchingInput()) { 2998 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2999 3000 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 3001 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 3002 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT); 3003 std::pair<unsigned, const TargetRegisterClass*> InputRC = 3004 getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT); 3005 if ((OpInfo.ConstraintVT.isInteger() != 3006 Input.ConstraintVT.isInteger()) || 3007 (MatchRC.second != InputRC.second)) { 3008 report_fatal_error("Unsupported asm: input constraint" 3009 " with a matching output constraint of" 3010 " incompatible type!"); 3011 } 3012 } 3013 3014 } 3015 } 3016 3017 return ConstraintOperands; 3018 } 3019 3020 3021 /// getConstraintGenerality - Return an integer indicating how general CT 3022 /// is. 3023 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3024 switch (CT) { 3025 case TargetLowering::C_Other: 3026 case TargetLowering::C_Unknown: 3027 return 0; 3028 case TargetLowering::C_Register: 3029 return 1; 3030 case TargetLowering::C_RegisterClass: 3031 return 2; 3032 case TargetLowering::C_Memory: 3033 return 3; 3034 } 3035 llvm_unreachable("Invalid constraint type"); 3036 } 3037 3038 /// Examine constraint type and operand type and determine a weight value. 3039 /// This object must already have been set up with the operand type 3040 /// and the current alternative constraint selected. 3041 TargetLowering::ConstraintWeight 3042 TargetLowering::getMultipleConstraintMatchWeight( 3043 AsmOperandInfo &info, int maIndex) const { 3044 InlineAsm::ConstraintCodeVector *rCodes; 3045 if (maIndex >= (int)info.multipleAlternatives.size()) 3046 rCodes = &info.Codes; 3047 else 3048 rCodes = &info.multipleAlternatives[maIndex].Codes; 3049 ConstraintWeight BestWeight = CW_Invalid; 3050 3051 // Loop over the options, keeping track of the most general one. 3052 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 3053 ConstraintWeight weight = 3054 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 3055 if (weight > BestWeight) 3056 BestWeight = weight; 3057 } 3058 3059 return BestWeight; 3060 } 3061 3062 /// Examine constraint type and operand type and determine a weight value. 3063 /// This object must already have been set up with the operand type 3064 /// and the current alternative constraint selected. 3065 TargetLowering::ConstraintWeight 3066 TargetLowering::getSingleConstraintMatchWeight( 3067 AsmOperandInfo &info, const char *constraint) const { 3068 ConstraintWeight weight = CW_Invalid; 3069 Value *CallOperandVal = info.CallOperandVal; 3070 // If we don't have a value, we can't do a match, 3071 // but allow it at the lowest weight. 3072 if (CallOperandVal == NULL) 3073 return CW_Default; 3074 // Look at the constraint type. 3075 switch (*constraint) { 3076 case 'i': // immediate integer. 3077 case 'n': // immediate integer with a known value. 3078 if (isa<ConstantInt>(CallOperandVal)) 3079 weight = CW_Constant; 3080 break; 3081 case 's': // non-explicit intregal immediate. 3082 if (isa<GlobalValue>(CallOperandVal)) 3083 weight = CW_Constant; 3084 break; 3085 case 'E': // immediate float if host format. 3086 case 'F': // immediate float. 3087 if (isa<ConstantFP>(CallOperandVal)) 3088 weight = CW_Constant; 3089 break; 3090 case '<': // memory operand with autodecrement. 3091 case '>': // memory operand with autoincrement. 3092 case 'm': // memory operand. 3093 case 'o': // offsettable memory operand 3094 case 'V': // non-offsettable memory operand 3095 weight = CW_Memory; 3096 break; 3097 case 'r': // general register. 3098 case 'g': // general register, memory operand or immediate integer. 3099 // note: Clang converts "g" to "imr". 3100 if (CallOperandVal->getType()->isIntegerTy()) 3101 weight = CW_Register; 3102 break; 3103 case 'X': // any operand. 3104 default: 3105 weight = CW_Default; 3106 break; 3107 } 3108 return weight; 3109 } 3110 3111 /// ChooseConstraint - If there are multiple different constraints that we 3112 /// could pick for this operand (e.g. "imr") try to pick the 'best' one. 3113 /// This is somewhat tricky: constraints fall into four classes: 3114 /// Other -> immediates and magic values 3115 /// Register -> one specific register 3116 /// RegisterClass -> a group of regs 3117 /// Memory -> memory 3118 /// Ideally, we would pick the most specific constraint possible: if we have 3119 /// something that fits into a register, we would pick it. The problem here 3120 /// is that if we have something that could either be in a register or in 3121 /// memory that use of the register could cause selection of *other* 3122 /// operands to fail: they might only succeed if we pick memory. Because of 3123 /// this the heuristic we use is: 3124 /// 3125 /// 1) If there is an 'other' constraint, and if the operand is valid for 3126 /// that constraint, use it. This makes us take advantage of 'i' 3127 /// constraints when available. 3128 /// 2) Otherwise, pick the most general constraint present. This prefers 3129 /// 'm' over 'r', for example. 3130 /// 3131 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 3132 const TargetLowering &TLI, 3133 SDValue Op, SelectionDAG *DAG) { 3134 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 3135 unsigned BestIdx = 0; 3136 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 3137 int BestGenerality = -1; 3138 3139 // Loop over the options, keeping track of the most general one. 3140 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 3141 TargetLowering::ConstraintType CType = 3142 TLI.getConstraintType(OpInfo.Codes[i]); 3143 3144 // If this is an 'other' constraint, see if the operand is valid for it. 3145 // For example, on X86 we might have an 'rI' constraint. If the operand 3146 // is an integer in the range [0..31] we want to use I (saving a load 3147 // of a register), otherwise we must use 'r'. 3148 if (CType == TargetLowering::C_Other && Op.getNode()) { 3149 assert(OpInfo.Codes[i].size() == 1 && 3150 "Unhandled multi-letter 'other' constraint"); 3151 std::vector<SDValue> ResultOps; 3152 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], 3153 ResultOps, *DAG); 3154 if (!ResultOps.empty()) { 3155 BestType = CType; 3156 BestIdx = i; 3157 break; 3158 } 3159 } 3160 3161 // Things with matching constraints can only be registers, per gcc 3162 // documentation. This mainly affects "g" constraints. 3163 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 3164 continue; 3165 3166 // This constraint letter is more general than the previous one, use it. 3167 int Generality = getConstraintGenerality(CType); 3168 if (Generality > BestGenerality) { 3169 BestType = CType; 3170 BestIdx = i; 3171 BestGenerality = Generality; 3172 } 3173 } 3174 3175 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 3176 OpInfo.ConstraintType = BestType; 3177 } 3178 3179 /// ComputeConstraintToUse - Determines the constraint code and constraint 3180 /// type to use for the specific AsmOperandInfo, setting 3181 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. 3182 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 3183 SDValue Op, 3184 SelectionDAG *DAG) const { 3185 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 3186 3187 // Single-letter constraints ('r') are very common. 3188 if (OpInfo.Codes.size() == 1) { 3189 OpInfo.ConstraintCode = OpInfo.Codes[0]; 3190 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3191 } else { 3192 ChooseConstraint(OpInfo, *this, Op, DAG); 3193 } 3194 3195 // 'X' matches anything. 3196 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 3197 // Labels and constants are handled elsewhere ('X' is the only thing 3198 // that matches labels). For Functions, the type here is the type of 3199 // the result, which is not what we want to look at; leave them alone. 3200 Value *v = OpInfo.CallOperandVal; 3201 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 3202 OpInfo.CallOperandVal = v; 3203 return; 3204 } 3205 3206 // Otherwise, try to resolve it to something we know about by looking at 3207 // the actual operand type. 3208 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 3209 OpInfo.ConstraintCode = Repl; 3210 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3211 } 3212 } 3213 } 3214 3215 //===----------------------------------------------------------------------===// 3216 // Loop Strength Reduction hooks 3217 //===----------------------------------------------------------------------===// 3218 3219 /// isLegalAddressingMode - Return true if the addressing mode represented 3220 /// by AM is legal for this target, for a load/store of the specified type. 3221 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 3222 Type *Ty) const { 3223 // The default implementation of this implements a conservative RISCy, r+r and 3224 // r+i addr mode. 3225 3226 // Allows a sign-extended 16-bit immediate field. 3227 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3228 return false; 3229 3230 // No global is ever allowed as a base. 3231 if (AM.BaseGV) 3232 return false; 3233 3234 // Only support r+r, 3235 switch (AM.Scale) { 3236 case 0: // "r+i" or just "i", depending on HasBaseReg. 3237 break; 3238 case 1: 3239 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3240 return false; 3241 // Otherwise we have r+r or r+i. 3242 break; 3243 case 2: 3244 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3245 return false; 3246 // Allow 2*r as r+r. 3247 break; 3248 } 3249 3250 return true; 3251 } 3252 3253 /// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication 3254 /// with the multiplicative inverse of the constant. 3255 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, 3256 SelectionDAG &DAG) const { 3257 ConstantSDNode *C = cast<ConstantSDNode>(Op2); 3258 APInt d = C->getAPIntValue(); 3259 assert(d != 0 && "Division by zero!"); 3260 3261 // Shift the value upfront if it is even, so the LSB is one. 3262 unsigned ShAmt = d.countTrailingZeros(); 3263 if (ShAmt) { 3264 // TODO: For UDIV use SRL instead of SRA. 3265 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); 3266 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt); 3267 d = d.ashr(ShAmt); 3268 } 3269 3270 // Calculate the multiplicative inverse, using Newton's method. 3271 APInt t, xn = d; 3272 while ((t = d*xn) != 1) 3273 xn *= APInt(d.getBitWidth(), 2) - t; 3274 3275 Op2 = DAG.getConstant(xn, Op1.getValueType()); 3276 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2); 3277 } 3278 3279 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3280 /// return a DAG expression to select that will generate the same value by 3281 /// multiplying by a magic number. See: 3282 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3283 SDValue TargetLowering:: 3284 BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 3285 std::vector<SDNode*>* Created) const { 3286 EVT VT = N->getValueType(0); 3287 DebugLoc dl= N->getDebugLoc(); 3288 3289 // Check to see if we can do this. 3290 // FIXME: We should be more aggressive here. 3291 if (!isTypeLegal(VT)) 3292 return SDValue(); 3293 3294 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3295 APInt::ms magics = d.magic(); 3296 3297 // Multiply the numerator (operand 0) by the magic value 3298 // FIXME: We should support doing a MUL in a wider type 3299 SDValue Q; 3300 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : 3301 isOperationLegalOrCustom(ISD::MULHS, VT)) 3302 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 3303 DAG.getConstant(magics.m, VT)); 3304 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : 3305 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 3306 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 3307 N->getOperand(0), 3308 DAG.getConstant(magics.m, VT)).getNode(), 1); 3309 else 3310 return SDValue(); // No mulhs or equvialent 3311 // If d > 0 and m < 0, add the numerator 3312 if (d.isStrictlyPositive() && magics.m.isNegative()) { 3313 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 3314 if (Created) 3315 Created->push_back(Q.getNode()); 3316 } 3317 // If d < 0 and m > 0, subtract the numerator. 3318 if (d.isNegative() && magics.m.isStrictlyPositive()) { 3319 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3320 if (Created) 3321 Created->push_back(Q.getNode()); 3322 } 3323 // Shift right algebraic if shift value is nonzero 3324 if (magics.s > 0) { 3325 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 3326 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3327 if (Created) 3328 Created->push_back(Q.getNode()); 3329 } 3330 // Extract the sign bit and add it to the quotient 3331 SDValue T = 3332 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 3333 getShiftAmountTy(Q.getValueType()))); 3334 if (Created) 3335 Created->push_back(T.getNode()); 3336 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 3337 } 3338 3339 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3340 /// return a DAG expression to select that will generate the same value by 3341 /// multiplying by a magic number. See: 3342 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3343 SDValue TargetLowering:: 3344 BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 3345 std::vector<SDNode*>* Created) const { 3346 EVT VT = N->getValueType(0); 3347 DebugLoc dl = N->getDebugLoc(); 3348 3349 // Check to see if we can do this. 3350 // FIXME: We should be more aggressive here. 3351 if (!isTypeLegal(VT)) 3352 return SDValue(); 3353 3354 // FIXME: We should use a narrower constant when the upper 3355 // bits are known to be zero. 3356 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3357 APInt::mu magics = N1C.magicu(); 3358 3359 SDValue Q = N->getOperand(0); 3360 3361 // If the divisor is even, we can avoid using the expensive fixup by shifting 3362 // the divided value upfront. 3363 if (magics.a != 0 && !N1C[0]) { 3364 unsigned Shift = N1C.countTrailingZeros(); 3365 Q = DAG.getNode(ISD::SRL, dl, VT, Q, 3366 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType()))); 3367 if (Created) 3368 Created->push_back(Q.getNode()); 3369 3370 // Get magic number for the shifted divisor. 3371 magics = N1C.lshr(Shift).magicu(Shift); 3372 assert(magics.a == 0 && "Should use cheap fixup now"); 3373 } 3374 3375 // Multiply the numerator (operand 0) by the magic value 3376 // FIXME: We should support doing a MUL in a wider type 3377 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : 3378 isOperationLegalOrCustom(ISD::MULHU, VT)) 3379 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); 3380 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : 3381 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 3382 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, 3383 DAG.getConstant(magics.m, VT)).getNode(), 1); 3384 else 3385 return SDValue(); // No mulhu or equvialent 3386 if (Created) 3387 Created->push_back(Q.getNode()); 3388 3389 if (magics.a == 0) { 3390 assert(magics.s < N1C.getBitWidth() && 3391 "We shouldn't generate an undefined shift!"); 3392 return DAG.getNode(ISD::SRL, dl, VT, Q, 3393 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3394 } else { 3395 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3396 if (Created) 3397 Created->push_back(NPQ.getNode()); 3398 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 3399 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType()))); 3400 if (Created) 3401 Created->push_back(NPQ.getNode()); 3402 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 3403 if (Created) 3404 Created->push_back(NPQ.getNode()); 3405 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 3406 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); 3407 } 3408 } 3409
