| /external/valgrind/main/memcheck/tests/ |
| partiallydefinedeq.c | 14 *hack = 0x80808080;
63 // because the constant 0x80808080 is placed in a constant pool
69 // level we have the 0x80808080 either in the literal pool (3 errors)
|
| /external/libvpx/vp8/common/arm/neon/ |
| loopfiltersimplehorizontaledge_neon.asm | 111 DCD 0x80808080, 0x80808080, 0x80808080, 0x80808080
|
| loopfiltersimpleverticaledge_neon.asm | 152 DCD 0x80808080, 0x80808080, 0x80808080, 0x80808080
|
| loopfilter_neon.asm | 405 DCD 0x80808080, 0x80808080, 0x80808080, 0x80808080
|
| mbloopfilter_neon.asm | 513 DCD 0x80808080, 0x80808080, 0x80808080, 0x80808080
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_Average_4x_Align_unsafe_s.s | 75 LDR r0x80808080, =0x80808080
117 LDR r0x80808080, =0x80808080
172 LDR r0x80808080, =0x80808080
|
| armVCM4P10_InterpolateLuma_DiagCopy_unsafe_s.s | 45 MASK EQU 0x80808080 ;// Mask is used to implement (a+b+1)/2
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_Average_4x_Align_unsafe_s.s | 75 LDR r0x80808080, =0x80808080
117 LDR r0x80808080, =0x80808080
172 LDR r0x80808080, =0x80808080
|
| armVCM4P10_InterpolateLuma_DiagCopy_unsafe_s.s | 45 MASK EQU 0x80808080 ;// Mask is used to implement (a+b+1)/2
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_Average_4x_Align_unsafe_s.S | 17 LDR r7, =0x80808080
49 LDR r7, =0x80808080
93 LDR r7, =0x80808080
|
| /frameworks/av/media/libstagefright/codecs/avc/enc/src/ |
| sad_mb_offset.h | 34 x9 = 0x80808080; /* const. */
134 x9 = 0x80808080; /* const. */
226 x9 = 0x80808080; /* const. */
|
| sad_inline.h | 81 x9 = 0x80808080; /* const. */
256 x9 = 0x80808080; /* const. */
394 x9 = 0x80808080; /* const. */
|
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| sad_mb_offset.h | 39 x9 = 0x80808080; /* const. */
139 x9 = 0x80808080; /* const. */
235 x9 = 0x80808080; /* const. */
|
| sad_inline.h | 86 x9 = 0x80808080; /* const. */
261 x9 = 0x80808080; /* const. */
450 x9 = 0x80808080; /* const. */
|
| fastcodemb.cpp | 537 UInt mask, sgn_msk = 0x80808080;
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm11_asm/ |
| h264bsd_interpolate_ver_quarter.s | 196 LDR tmpa, = 0x80808080
247 LDR tmpa, = 0x80808080
297 LDR tmpa, = 0x80808080
346 LDR tmpa, = 0x80808080
|
| h264bsd_interpolate_hor_quarter.s | 206 LDR tmp2, = 0x80808080
252 LDR tmp2, = 0x80808080
|
| h264bsd_interpolate_hor_ver_quarter.s | 295 ;// EOR a, a, 0x80808080
359 LDR tmpa, = 0x80808080
410 LDR tmpa, = 0x80808080
460 LDR tmpa, = 0x80808080
509 LDR tmpa, = 0x80808080
|
| /external/openssl/crypto/aes/ |
| aes_x86core.c | 600 m = tp1 & 0x80808080;
603 m = tp2 & 0x80808080;
606 m = tp4 & 0x80808080;
697 r1 = r0 & 0x80808080;
763 r1 = r0 & 0x80808080;
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 117 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
119 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
656 CurDAG->getConstant(0x80808080, MVT::i32),
658 CurDAG->getConstant(0x80808080, MVT::i32),
664 CurDAG->getConstant(0x80808080, MVT::i32),
666 CurDAG->getConstant(0x80808080, MVT::i32),
672 CurDAG->getConstant(0x80808080, MVT::i32),
674 CurDAG->getConstant(0x80808080, MVT::i32),
[all...] |
| /external/openssl/crypto/aes/asm/ |
| aes-x86_64.pl | 443 and \$0x80808080,$acc
470 and \$0x80808080,$acc0
471 and \$0x80808080,$acc1
495 and \$0x80808080,$acc0
496 and \$0x80808080,$acc1
1508 and \$0x80808080,$acc
1518 and \$0x80808080,$acc
1529 and \$0x80808080,$acc
[all...] |
| aes-mips.pl | 1095 my ($m,$x80808080,$x7f7f7f7f,$x1b1b1b1b)=($at,$t0,$t1,$t2);
1158 lui $x80808080,0x8080
1160 or $x80808080,0x8080
1164 nor $x7f7f7f7f,$zero,$x80808080
1168 and $m,$tp1,$x80808080
1176 and $m,$tp2,$x80808080
1184 and $m,$tp4,$x80808080
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
| omxVCM4P2_MCReconBlock_s.s | 46 ;// $mask some register set to 0x80808080
379 LDR mask, =0x80808080
410 LDR mask, =0x80808080
|
| /external/libvpx/vp8/encoder/arm/armv6/ |
| vp8_variance_halfpixvar16x16_h_armv6.asm | 173 DCD 0x80808080
|
| vp8_variance_halfpixvar16x16_v_armv6.asm | 175 DCD 0x80808080
|
