1 /* 2 * (c) Copyright 2007-2008 ARM Limited. All Rights Reserved. 3 * 4 */ 5 6 .eabi_attribute 24, 1 7 .eabi_attribute 25, 1 8 9 .arm 10 .fpu neon 11 .text 12 13 .global armVCM4P10_Average_4x4_Align0_unsafe 14 .func armVCM4P10_Average_4x4_Align0_unsafe 15 armVCM4P10_Average_4x4_Align0_unsafe: 16 PUSH {r4-r6,lr} 17 LDR r7, =0x80808080 18 LDR r12,[r2,#0] 19 LDR r10,[r0],r1 20 LDR lr,[r2,r3] 21 LDR r11,[r0],r1 22 MVN r12,r12 23 MVN lr,lr 24 UHSUB8 r5,r10,r12 25 UHSUB8 r4,r11,lr 26 EOR r5,r5,r7 27 STR r5,[r2],r3 28 EOR r4,r4,r7 29 STR r4,[r2],r3 30 LDR r10,[r0],r1 31 LDR r12,[r2,#0] 32 LDR r11,[r0],r1 33 LDR lr,[r2,r3] 34 MVN r12,r12 35 UHSUB8 r5,r10,r12 36 MVN lr,lr 37 UHSUB8 r4,r11,lr 38 EOR r5,r5,r7 39 STR r5,[r2],r3 40 EOR r4,r4,r7 41 STR r4,[r2],r3 42 POP {r4-r6,pc} 43 .endfunc 44 45 .global armVCM4P10_Average_4x4_Align2_unsafe 46 .func armVCM4P10_Average_4x4_Align2_unsafe 47 armVCM4P10_Average_4x4_Align2_unsafe: 48 PUSH {r4-r6,lr} 49 LDR r7, =0x80808080 50 LDR r4,[r0,#4] 51 LDR r10,[r0],r1 52 LDR r12,[r2,#0] 53 LDR lr,[r2,r3] 54 LDR r5,[r0,#4] 55 LDR r11,[r0],r1 56 MVN r12,r12 57 MVN lr,lr 58 LSR r10,r10,#16 59 ORR r10,r10,r4,LSL #16 60 LSR r11,r11,#16 61 ORR r11,r11,r5,LSL #16 62 UHSUB8 r5,r10,r12 63 UHSUB8 r4,r11,lr 64 EOR r5,r5,r7 65 STR r5,[r2],r3 66 EOR r4,r4,r7 67 STR r4,[r2],r3 68 LDR r4,[r0,#4] 69 LDR r10,[r0],r1 70 LDR r12,[r2,#0] 71 LDR lr,[r2,r3] 72 LDR r5,[r0,#4] 73 LDR r11,[r0],r1 74 MVN r12,r12 75 MVN lr,lr 76 LSR r10,r10,#16 77 ORR r10,r10,r4,LSL #16 78 LSR r11,r11,#16 79 ORR r11,r11,r5,LSL #16 80 UHSUB8 r5,r10,r12 81 UHSUB8 r4,r11,lr 82 EOR r5,r5,r7 83 STR r5,[r2],r3 84 EOR r4,r4,r7 85 STR r4,[r2],r3 86 POP {r4-r6,pc} 87 .endfunc 88 89 .global armVCM4P10_Average_4x4_Align3_unsafe 90 .func armVCM4P10_Average_4x4_Align3_unsafe 91 armVCM4P10_Average_4x4_Align3_unsafe: 92 PUSH {r4-r6,lr} 93 LDR r7, =0x80808080 94 LDR r4,[r0,#4] 95 LDR r10,[r0],r1 96 LDR r12,[r2,#0] 97 LDR lr,[r2,r3] 98 LDR r5,[r0,#4] 99 LDR r11,[r0],r1 100 MVN r12,r12 101 MVN lr,lr 102 LSR r10,r10,#24 103 ORR r10,r10,r4,LSL #8 104 LSR r11,r11,#24 105 ORR r11,r11,r5,LSL #8 106 UHSUB8 r5,r10,r12 107 UHSUB8 r4,r11,lr 108 EOR r5,r5,r7 109 STR r5,[r2],r3 110 EOR r4,r4,r7 111 STR r4,[r2],r3 112 LDR r4,[r0,#4] 113 LDR r10,[r0],r1 114 LDR r12,[r2,#0] 115 LDR lr,[r2,r3] 116 LDR r5,[r0,#4] 117 LDR r11,[r0],r1 118 MVN r12,r12 119 MVN lr,lr 120 LSR r10,r10,#24 121 ORR r10,r10,r4,LSL #8 122 LSR r11,r11,#24 123 ORR r11,r11,r5,LSL #8 124 UHSUB8 r5,r10,r12 125 UHSUB8 r4,r11,lr 126 EOR r5,r5,r7 127 STR r5,[r2],r3 128 EOR r4,r4,r7 129 STR r4,[r2],r3 130 POP {r4-r6,pc} 131 .endfunc 132 133 .end 134 135
