| /external/llvm/unittests/Support/ |
| ValueHandleTest.cpp | 68 Value *BV = BitcastV.get();
70 EXPECT_EQ(BV < CV, BitcastWVH < ConstantWVH);
71 EXPECT_EQ(BV <= CV, BitcastWVH <= ConstantWVH);
72 EXPECT_EQ(BV > CV, BitcastWVH > ConstantWVH);
73 EXPECT_EQ(BV >= CV, BitcastWVH >= ConstantWVH);
75 EXPECT_EQ(BV < CV, BitcastV.get() < ConstantWVH);
76 EXPECT_EQ(BV <= CV, BitcastV.get() <= ConstantWVH);
77 EXPECT_EQ(BV > CV, BitcastV.get() > ConstantWVH);
78 EXPECT_EQ(BV >= CV, BitcastV.get() >= ConstantWVH);
80 EXPECT_EQ(BV < CV, BitcastWVH < ConstantV)
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| RangeConstraintManager.cpp | 107 void IntersectInRange(BasicValueFactory &BV, Factory &F,
131 newRanges = F.add(newRanges, Range(BV.getValue(Lower),
132 BV.getValue(Upper)));
135 newRanges = F.add(newRanges, Range(BV.getValue(Lower), i->To()));
138 newRanges = F.add(newRanges, Range(i->From(), BV.getValue(Upper)));
154 RangeSet Intersect(BasicValueFactory &BV, Factory &F,
161 IntersectInRange(BV, F, Lower, Upper, newRanges, i, e);
166 IntersectInRange(BV, F, BV.getMinValue(Upper), Upper, newRanges, i, e);
167 IntersectInRange(BV, F, Lower, BV.getMaxValue(Lower), newRanges, i, e)
[all...] |
| MemRegion.cpp | [all...] |
| /external/llvm/include/llvm/ADT/ |
| SmallBitVector.h | 98 void switchToLarge(BitVector *BV) {
99 X = reinterpret_cast<uintptr_t>(BV);
254 BitVector *BV = new BitVector(N, t);
257 (*BV)[i] = (OldBits >> i) & 1;
258 switchToLarge(BV);
267 BitVector *BV = new BitVector(SmallSize);
270 BV->set(i);
271 BV->reserve(N);
272 switchToLarge(BV);
|
| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 153 /// Add Reg and all its sub-registers to BV.
154 void addRegWithSubRegs(BitVector &BV, unsigned Reg);
|
| /external/clang/lib/Analysis/ |
| AnalysisDeclContext.cpp | 396 DeclVec *BV = (DeclVec*) A.Allocate<DeclVec>();
397 new (BV) DeclVec(BC, 10);
400 FindBlockDeclRefExprsVals F(*BV, BC);
403 Vec = BV;
404 return BV;
|
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.cpp | 515 BitVector BV(TRI->getNumRegs(), false);
534 BV |= RCBV;
537 BV &= RCBV;
543 return BV;
580 BitVector BV = GetRenameRegisters(Reg);
581 RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
584 DEBUG(for (int r = BV.find_first(); r != -1; r = BV.find_next(r))
666 BitVector BV = RenameRegisterMap[Reg];
667 if (!BV.test(NewReg))
[all...] |
| MachineFunction.cpp | 465 BitVector BV(TRI->getNumRegs());
470 return BV;
473 BV.set(*CSR);
477 return BV;
483 BV.reset(I->getReg());
485 return BV;
|
| RegisterScavenging.cpp | 115 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
116 BV.set(Reg);
118 BV.set(*R);
|
| /external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| SymbolManager.h | 480 BasicValueFactory &BV;
484 SymbolManager(ASTContext &ctx, BasicValueFactory &bv,
487 BPAlloc(bpalloc), BV(bv), Ctx(ctx) {}
553 BasicValueFactory &getBasicVals() { return BV; }
|
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | [all...] |
| CodeGenRegisters.cpp | [all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| BBVectorize.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 680 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
686 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
714 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
