/external/llvm/lib/Target/ARM/ |
ARMInstrInfo.cpp | 35 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 41 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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ARMAsmPrinter.cpp | [all...] |
ARMMCInstLower.cpp | 78 MCOp = MCOperand::CreateImm(MO.getImm());
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Thumb1InstrInfo.cpp | 33 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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/external/llvm/lib/Target/Hexagon/ |
HexagonMCInstLower.cpp | 62 MCO = MCOperand::CreateImm(*Val.bitcastToAPInt().getRawData()); 66 MCO = MCOperand::CreateImm(MO.getImm());
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/external/llvm/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | 650 I = MI.insert(I, MCOperand::CreateImm(CC)); 660 I = MI.insert(I, MCOperand::CreateImm(CC)); [all...] |
/external/llvm/lib/Target/Mips/Disassembler/ |
MipsDisassembler.cpp | 432 Inst.addOperand(MCOperand::CreateImm(Offset)); 447 Inst.addOperand(MCOperand::CreateImm(Offset)); 469 Inst.addOperand(MCOperand::CreateImm(CondCode)); 501 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 511 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 521 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 530 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn))); 541 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 550 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
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/external/llvm/lib/Target/Mips/ |
MipsMCInstLower.cpp | 161 CreateMCInst(MCInsts[0], Mips::LUi, ATReg, MCOperand::CreateImm(Hi)); 166 CreateMCInst(Sw, Mips::SW, GPReg, BaseReg, MCOperand::CreateImm(Offset)); 181 return MCOperand::CreateImm(MO.getImm() + offset); 274 Instr3.addOperand(MCOperand::CreateImm(0x8)); 275 Instr3.addOperand(MCOperand::CreateImm(0x18)); 303 Instr2.addOperand(MCOperand::CreateImm(8));
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/external/llvm/lib/Target/MBlaze/Disassembler/ |
MBlazeDisassembler.cpp | 576 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); 581 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); 589 instr.addOperand(MCOperand::CreateImm(insn&0x7FFF)); 601 instr.addOperand(MCOperand::CreateImm(getIMM(insn))); 606 instr.addOperand(MCOperand::CreateImm(insn&0x1F)); 622 instr.addOperand(MCOperand::CreateImm(getIMM(insn))); 636 instr.addOperand(MCOperand::CreateImm(getIMM(insn))); 646 instr.addOperand(MCOperand::CreateImm(getIMM(insn))); 654 instr.addOperand(MCOperand::CreateImm(getSHT(insn))); 668 instr.addOperand(MCOperand::CreateImm(getFSL(insn))) [all...] |
/external/llvm/lib/Target/MBlaze/ |
MBlazeMCInstLower.cpp | 130 MCOp = MCOperand::CreateImm(MO.getImm()); 158 MCOp = MCOperand::CreateImm(Val);
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MBlazeInstrInfo.cpp | 146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); 165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
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/external/llvm/lib/Target/X86/ |
X86InstrBuilder.h | 71 MO.push_back(MachineOperand::CreateImm(Scale)); 78 MO.push_back(MachineOperand::CreateImm(Disp));
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/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | [all...] |
/external/llvm/lib/Target/MBlaze/AsmParser/ |
MBlazeAsmParser.cpp | 178 Inst.addOperand(MCOperand::CreateImm(0)); 180 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 236 static MBlazeOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 449 return MBlazeOperand::CreateImm(EVal, S, E);
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/external/llvm/lib/Target/MSP430/ |
MSP430MCInstLower.cpp | 126 MCOp = MCOperand::CreateImm(MO.getImm());
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MSP430InstrInfo.cpp | 234 Cond.push_back(MachineOperand::CreateImm(BranchCode));
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/external/llvm/include/llvm/MC/ |
MCInst.h | 117 static MCOperand CreateImm(int64_t Val) {
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/external/llvm/lib/Target/X86/Disassembler/ |
X86Disassembler.cpp | 418 mcInst.addOperand(MCOperand::CreateImm(immediate)); 518 scaleAmount = MCOperand::CreateImm(insn.sibScale); 579 scaleAmount = MCOperand::CreateImm(1); 582 displacement = MCOperand::CreateImm(insn.displacement);
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/external/llvm/lib/Target/XCore/ |
XCoreInstrInfo.cpp | 222 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 244 Cond.push_back(MachineOperand::CreateImm(BranchCode));
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/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | 348 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 522 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 529 MI->addOperand(MachineOperand::CreateImm(SubIdx)); [all...] |
/external/llvm/lib/Target/CellSPU/ |
SPUInstrInfo.cpp | 246 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); 267 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
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/external/llvm/lib/Target/PTX/ |
PTXInstrInfo.cpp | 170 Pred.push_back(MachineOperand::CreateImm(PTXPredicate::None)); 337 MI->addOperand(MachineOperand::CreateImm(PTXPredicate::None));
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/external/llvm/lib/Target/X86/AsmParser/ |
X86AsmParser.cpp | 344 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 384 Inst.addOperand(MCOperand::CreateImm(getMemScale())); 394 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 413 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){ 732 return X86Operand::CreateImm(Val, Start, End); 779 return X86Operand::CreateImm(Val, Start, End); [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCMCInstLower.cpp | 149 MCOp = MCOperand::CreateImm(MO.getImm());
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/external/llvm/include/llvm/CodeGen/ |
MachineInstrBuilder.h | 77 MI->addOperand(MachineOperand::CreateImm(Val));
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