1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "MCTargetDesc/ARMAddressingModes.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "llvm/MC/EDInstInfo.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 using namespace llvm; 29 30 typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32 namespace { 33 /// ARMDisassembler - ARM disassembler for all ARM platforms. 34 class ARMDisassembler : public MCDisassembler { 35 public: 36 /// Constructor - Initializes the disassembler. 37 /// 38 ARMDisassembler(const MCSubtargetInfo &STI) : 39 MCDisassembler(STI) { 40 } 41 42 ~ARMDisassembler() { 43 } 44 45 /// getInstruction - See MCDisassembler. 46 DecodeStatus getInstruction(MCInst &instr, 47 uint64_t &size, 48 const MemoryObject ®ion, 49 uint64_t address, 50 raw_ostream &vStream, 51 raw_ostream &cStream) const; 52 53 /// getEDInfo - See MCDisassembler. 54 const EDInstInfo *getEDInfo() const; 55 private: 56 }; 57 58 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 59 class ThumbDisassembler : public MCDisassembler { 60 public: 61 /// Constructor - Initializes the disassembler. 62 /// 63 ThumbDisassembler(const MCSubtargetInfo &STI) : 64 MCDisassembler(STI) { 65 } 66 67 ~ThumbDisassembler() { 68 } 69 70 /// getInstruction - See MCDisassembler. 71 DecodeStatus getInstruction(MCInst &instr, 72 uint64_t &size, 73 const MemoryObject ®ion, 74 uint64_t address, 75 raw_ostream &vStream, 76 raw_ostream &cStream) const; 77 78 /// getEDInfo - See MCDisassembler. 79 const EDInstInfo *getEDInfo() const; 80 private: 81 mutable std::vector<unsigned> ITBlock; 82 DecodeStatus AddThumbPredicate(MCInst&) const; 83 void UpdateThumbVFPPredicate(MCInst&) const; 84 }; 85 } 86 87 static bool Check(DecodeStatus &Out, DecodeStatus In) { 88 switch (In) { 89 case MCDisassembler::Success: 90 // Out stays the same. 91 return true; 92 case MCDisassembler::SoftFail: 93 Out = In; 94 return true; 95 case MCDisassembler::Fail: 96 Out = In; 97 return false; 98 } 99 llvm_unreachable("Invalid DecodeStatus!"); 100 } 101 102 103 // Forward declare these because the autogenerated code will reference them. 104 // Definitions are further down. 105 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 106 uint64_t Address, const void *Decoder); 107 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 108 unsigned RegNo, uint64_t Address, 109 const void *Decoder); 110 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 121 uint64_t Address, const void *Decoder); 122 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 127 uint64_t Address, const void *Decoder); 128 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, const void *Decoder); 130 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 131 unsigned RegNo, uint64_t Address, 132 const void *Decoder); 133 134 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 147 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 148 uint64_t Address, const void *Decoder); 149 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 150 uint64_t Address, const void *Decoder); 151 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 152 unsigned Insn, 153 uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 158 uint64_t Address, const void *Decoder); 159 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 162 uint64_t Address, const void *Decoder); 163 164 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 165 unsigned Insn, 166 uint64_t Adddress, 167 const void *Decoder); 168 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 261 uint64_t Address, const void *Decoder); 262 263 264 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 325 uint64_t Address, const void *Decoder); 326 327 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 330 uint64_t Address, const void *Decoder); 331 #include "ARMGenDisassemblerTables.inc" 332 #include "ARMGenInstrInfo.inc" 333 #include "ARMGenEDInfo.inc" 334 335 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 336 return new ARMDisassembler(STI); 337 } 338 339 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 340 return new ThumbDisassembler(STI); 341 } 342 343 const EDInstInfo *ARMDisassembler::getEDInfo() const { 344 return instInfoARM; 345 } 346 347 const EDInstInfo *ThumbDisassembler::getEDInfo() const { 348 return instInfoARM; 349 } 350 351 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 352 const MemoryObject &Region, 353 uint64_t Address, 354 raw_ostream &os, 355 raw_ostream &cs) const { 356 CommentStream = &cs; 357 358 uint8_t bytes[4]; 359 360 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 361 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 362 363 // We want to read exactly 4 bytes of data. 364 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 365 Size = 0; 366 return MCDisassembler::Fail; 367 } 368 369 // Encoded as a small-endian 32-bit word in the stream. 370 uint32_t insn = (bytes[3] << 24) | 371 (bytes[2] << 16) | 372 (bytes[1] << 8) | 373 (bytes[0] << 0); 374 375 // Calling the auto-generated decoder function. 376 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 377 if (result != MCDisassembler::Fail) { 378 Size = 4; 379 return result; 380 } 381 382 // VFP and NEON instructions, similarly, are shared between ARM 383 // and Thumb modes. 384 MI.clear(); 385 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 386 if (result != MCDisassembler::Fail) { 387 Size = 4; 388 return result; 389 } 390 391 MI.clear(); 392 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 393 if (result != MCDisassembler::Fail) { 394 Size = 4; 395 // Add a fake predicate operand, because we share these instruction 396 // definitions with Thumb2 where these instructions are predicable. 397 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 398 return MCDisassembler::Fail; 399 return result; 400 } 401 402 MI.clear(); 403 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 404 if (result != MCDisassembler::Fail) { 405 Size = 4; 406 // Add a fake predicate operand, because we share these instruction 407 // definitions with Thumb2 where these instructions are predicable. 408 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 409 return MCDisassembler::Fail; 410 return result; 411 } 412 413 MI.clear(); 414 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 415 if (result != MCDisassembler::Fail) { 416 Size = 4; 417 // Add a fake predicate operand, because we share these instruction 418 // definitions with Thumb2 where these instructions are predicable. 419 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 420 return MCDisassembler::Fail; 421 return result; 422 } 423 424 MI.clear(); 425 426 Size = 0; 427 return MCDisassembler::Fail; 428 } 429 430 namespace llvm { 431 extern const MCInstrDesc ARMInsts[]; 432 } 433 434 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 435 /// immediate Value in the MCInst. The immediate Value has had any PC 436 /// adjustment made by the caller. If the instruction is a branch instruction 437 /// then isBranch is true, else false. If the getOpInfo() function was set as 438 /// part of the setupForSymbolicDisassembly() call then that function is called 439 /// to get any symbolic information at the Address for this instruction. If 440 /// that returns non-zero then the symbolic information it returns is used to 441 /// create an MCExpr and that is added as an operand to the MCInst. If 442 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 443 /// Value is done and if a symbol is found an MCExpr is created with that, else 444 /// an MCExpr with Value is created. This function returns true if it adds an 445 /// operand to the MCInst and false otherwise. 446 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 447 bool isBranch, uint64_t InstSize, 448 MCInst &MI, const void *Decoder) { 449 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 450 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 451 struct LLVMOpInfo1 SymbolicOp; 452 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 453 SymbolicOp.Value = Value; 454 void *DisInfo = Dis->getDisInfoBlock(); 455 456 if (!getOpInfo || 457 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 458 // Clear SymbolicOp.Value from above and also all other fields. 459 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 460 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 461 if (!SymbolLookUp) 462 return false; 463 uint64_t ReferenceType; 464 if (isBranch) 465 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 466 else 467 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 468 const char *ReferenceName; 469 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 470 &ReferenceName); 471 if (Name) { 472 SymbolicOp.AddSymbol.Name = Name; 473 SymbolicOp.AddSymbol.Present = true; 474 } 475 // For branches always create an MCExpr so it gets printed as hex address. 476 else if (isBranch) { 477 SymbolicOp.Value = Value; 478 } 479 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 480 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 481 if (!Name && !isBranch) 482 return false; 483 } 484 485 MCContext *Ctx = Dis->getMCContext(); 486 const MCExpr *Add = NULL; 487 if (SymbolicOp.AddSymbol.Present) { 488 if (SymbolicOp.AddSymbol.Name) { 489 StringRef Name(SymbolicOp.AddSymbol.Name); 490 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 491 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 492 } else { 493 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 494 } 495 } 496 497 const MCExpr *Sub = NULL; 498 if (SymbolicOp.SubtractSymbol.Present) { 499 if (SymbolicOp.SubtractSymbol.Name) { 500 StringRef Name(SymbolicOp.SubtractSymbol.Name); 501 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 502 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 503 } else { 504 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 505 } 506 } 507 508 const MCExpr *Off = NULL; 509 if (SymbolicOp.Value != 0) 510 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 511 512 const MCExpr *Expr; 513 if (Sub) { 514 const MCExpr *LHS; 515 if (Add) 516 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 517 else 518 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 519 if (Off != 0) 520 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 521 else 522 Expr = LHS; 523 } else if (Add) { 524 if (Off != 0) 525 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 526 else 527 Expr = Add; 528 } else { 529 if (Off != 0) 530 Expr = Off; 531 else 532 Expr = MCConstantExpr::Create(0, *Ctx); 533 } 534 535 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 536 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 537 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 538 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 539 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 540 MI.addOperand(MCOperand::CreateExpr(Expr)); 541 else 542 llvm_unreachable("bad SymbolicOp.VariantKind"); 543 544 return true; 545 } 546 547 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 548 /// referenced by a load instruction with the base register that is the Pc. 549 /// These can often be values in a literal pool near the Address of the 550 /// instruction. The Address of the instruction and its immediate Value are 551 /// used as a possible literal pool entry. The SymbolLookUp call back will 552 /// return the name of a symbol referenced by the the literal pool's entry if 553 /// the referenced address is that of a symbol. Or it will return a pointer to 554 /// a literal 'C' string if the referenced address of the literal pool's entry 555 /// is an address into a section with 'C' string literals. 556 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 557 const void *Decoder) { 558 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 559 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 560 if (SymbolLookUp) { 561 void *DisInfo = Dis->getDisInfoBlock(); 562 uint64_t ReferenceType; 563 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 564 const char *ReferenceName; 565 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 566 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 567 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 568 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 569 } 570 } 571 572 // Thumb1 instructions don't have explicit S bits. Rather, they 573 // implicitly set CPSR. Since it's not represented in the encoding, the 574 // auto-generated decoder won't inject the CPSR operand. We need to fix 575 // that as a post-pass. 576 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 577 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 578 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 579 MCInst::iterator I = MI.begin(); 580 for (unsigned i = 0; i < NumOps; ++i, ++I) { 581 if (I == MI.end()) break; 582 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 583 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 584 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 585 return; 586 } 587 } 588 589 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 590 } 591 592 // Most Thumb instructions don't have explicit predicates in the 593 // encoding, but rather get their predicates from IT context. We need 594 // to fix up the predicate operands using this context information as a 595 // post-pass. 596 MCDisassembler::DecodeStatus 597 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 598 MCDisassembler::DecodeStatus S = Success; 599 600 // A few instructions actually have predicates encoded in them. Don't 601 // try to overwrite it if we're seeing one of those. 602 switch (MI.getOpcode()) { 603 case ARM::tBcc: 604 case ARM::t2Bcc: 605 case ARM::tCBZ: 606 case ARM::tCBNZ: 607 case ARM::tCPS: 608 case ARM::t2CPS3p: 609 case ARM::t2CPS2p: 610 case ARM::t2CPS1p: 611 case ARM::tMOVSr: 612 case ARM::tSETEND: 613 // Some instructions (mostly conditional branches) are not 614 // allowed in IT blocks. 615 if (!ITBlock.empty()) 616 S = SoftFail; 617 else 618 return Success; 619 break; 620 case ARM::tB: 621 case ARM::t2B: 622 case ARM::t2TBB: 623 case ARM::t2TBH: 624 // Some instructions (mostly unconditional branches) can 625 // only appears at the end of, or outside of, an IT. 626 if (ITBlock.size() > 1) 627 S = SoftFail; 628 break; 629 default: 630 break; 631 } 632 633 // If we're in an IT block, base the predicate on that. Otherwise, 634 // assume a predicate of AL. 635 unsigned CC; 636 if (!ITBlock.empty()) { 637 CC = ITBlock.back(); 638 if (CC == 0xF) 639 CC = ARMCC::AL; 640 ITBlock.pop_back(); 641 } else 642 CC = ARMCC::AL; 643 644 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 645 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 646 MCInst::iterator I = MI.begin(); 647 for (unsigned i = 0; i < NumOps; ++i, ++I) { 648 if (I == MI.end()) break; 649 if (OpInfo[i].isPredicate()) { 650 I = MI.insert(I, MCOperand::CreateImm(CC)); 651 ++I; 652 if (CC == ARMCC::AL) 653 MI.insert(I, MCOperand::CreateReg(0)); 654 else 655 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 656 return S; 657 } 658 } 659 660 I = MI.insert(I, MCOperand::CreateImm(CC)); 661 ++I; 662 if (CC == ARMCC::AL) 663 MI.insert(I, MCOperand::CreateReg(0)); 664 else 665 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 666 667 return S; 668 } 669 670 // Thumb VFP instructions are a special case. Because we share their 671 // encodings between ARM and Thumb modes, and they are predicable in ARM 672 // mode, the auto-generated decoder will give them an (incorrect) 673 // predicate operand. We need to rewrite these operands based on the IT 674 // context as a post-pass. 675 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 676 unsigned CC; 677 if (!ITBlock.empty()) { 678 CC = ITBlock.back(); 679 ITBlock.pop_back(); 680 } else 681 CC = ARMCC::AL; 682 683 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 684 MCInst::iterator I = MI.begin(); 685 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 686 for (unsigned i = 0; i < NumOps; ++i, ++I) { 687 if (OpInfo[i].isPredicate() ) { 688 I->setImm(CC); 689 ++I; 690 if (CC == ARMCC::AL) 691 I->setReg(0); 692 else 693 I->setReg(ARM::CPSR); 694 return; 695 } 696 } 697 } 698 699 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 700 const MemoryObject &Region, 701 uint64_t Address, 702 raw_ostream &os, 703 raw_ostream &cs) const { 704 CommentStream = &cs; 705 706 uint8_t bytes[4]; 707 708 assert((STI.getFeatureBits() & ARM::ModeThumb) && 709 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 710 711 // We want to read exactly 2 bytes of data. 712 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 713 Size = 0; 714 return MCDisassembler::Fail; 715 } 716 717 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 718 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 719 if (result != MCDisassembler::Fail) { 720 Size = 2; 721 Check(result, AddThumbPredicate(MI)); 722 return result; 723 } 724 725 MI.clear(); 726 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 727 if (result) { 728 Size = 2; 729 bool InITBlock = !ITBlock.empty(); 730 Check(result, AddThumbPredicate(MI)); 731 AddThumb1SBit(MI, InITBlock); 732 return result; 733 } 734 735 MI.clear(); 736 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 737 if (result != MCDisassembler::Fail) { 738 Size = 2; 739 740 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 741 // the Thumb predicate. 742 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 743 result = MCDisassembler::SoftFail; 744 745 Check(result, AddThumbPredicate(MI)); 746 747 // If we find an IT instruction, we need to parse its condition 748 // code and mask operands so that we can apply them correctly 749 // to the subsequent instructions. 750 if (MI.getOpcode() == ARM::t2IT) { 751 752 // (3 - the number of trailing zeros) is the number of then / else. 753 unsigned firstcond = MI.getOperand(0).getImm(); 754 unsigned Mask = MI.getOperand(1).getImm(); 755 unsigned CondBit0 = Mask >> 4 & 1; 756 unsigned NumTZ = CountTrailingZeros_32(Mask); 757 assert(NumTZ <= 3 && "Invalid IT mask!"); 758 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 759 bool T = ((Mask >> Pos) & 1) == CondBit0; 760 if (T) 761 ITBlock.insert(ITBlock.begin(), firstcond); 762 else 763 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 764 } 765 766 ITBlock.push_back(firstcond); 767 } 768 769 return result; 770 } 771 772 // We want to read exactly 4 bytes of data. 773 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 774 Size = 0; 775 return MCDisassembler::Fail; 776 } 777 778 uint32_t insn32 = (bytes[3] << 8) | 779 (bytes[2] << 0) | 780 (bytes[1] << 24) | 781 (bytes[0] << 16); 782 MI.clear(); 783 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 784 if (result != MCDisassembler::Fail) { 785 Size = 4; 786 bool InITBlock = ITBlock.size(); 787 Check(result, AddThumbPredicate(MI)); 788 AddThumb1SBit(MI, InITBlock); 789 return result; 790 } 791 792 MI.clear(); 793 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 794 if (result != MCDisassembler::Fail) { 795 Size = 4; 796 Check(result, AddThumbPredicate(MI)); 797 return result; 798 } 799 800 MI.clear(); 801 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 802 if (result != MCDisassembler::Fail) { 803 Size = 4; 804 UpdateThumbVFPPredicate(MI); 805 return result; 806 } 807 808 MI.clear(); 809 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 810 if (result != MCDisassembler::Fail) { 811 Size = 4; 812 Check(result, AddThumbPredicate(MI)); 813 return result; 814 } 815 816 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 817 MI.clear(); 818 uint32_t NEONLdStInsn = insn32; 819 NEONLdStInsn &= 0xF0FFFFFF; 820 NEONLdStInsn |= 0x04000000; 821 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 822 if (result != MCDisassembler::Fail) { 823 Size = 4; 824 Check(result, AddThumbPredicate(MI)); 825 return result; 826 } 827 } 828 829 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 830 MI.clear(); 831 uint32_t NEONDataInsn = insn32; 832 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 833 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 834 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 835 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 836 if (result != MCDisassembler::Fail) { 837 Size = 4; 838 Check(result, AddThumbPredicate(MI)); 839 return result; 840 } 841 } 842 843 Size = 0; 844 return MCDisassembler::Fail; 845 } 846 847 848 extern "C" void LLVMInitializeARMDisassembler() { 849 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 850 createARMDisassembler); 851 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 852 createThumbDisassembler); 853 } 854 855 static const uint16_t GPRDecoderTable[] = { 856 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 857 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 858 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 859 ARM::R12, ARM::SP, ARM::LR, ARM::PC 860 }; 861 862 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 863 uint64_t Address, const void *Decoder) { 864 if (RegNo > 15) 865 return MCDisassembler::Fail; 866 867 unsigned Register = GPRDecoderTable[RegNo]; 868 Inst.addOperand(MCOperand::CreateReg(Register)); 869 return MCDisassembler::Success; 870 } 871 872 static DecodeStatus 873 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 874 uint64_t Address, const void *Decoder) { 875 DecodeStatus S = MCDisassembler::Success; 876 877 if (RegNo == 15) 878 S = MCDisassembler::SoftFail; 879 880 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 881 882 return S; 883 } 884 885 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 886 uint64_t Address, const void *Decoder) { 887 if (RegNo > 7) 888 return MCDisassembler::Fail; 889 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 890 } 891 892 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 893 uint64_t Address, const void *Decoder) { 894 unsigned Register = 0; 895 switch (RegNo) { 896 case 0: 897 Register = ARM::R0; 898 break; 899 case 1: 900 Register = ARM::R1; 901 break; 902 case 2: 903 Register = ARM::R2; 904 break; 905 case 3: 906 Register = ARM::R3; 907 break; 908 case 9: 909 Register = ARM::R9; 910 break; 911 case 12: 912 Register = ARM::R12; 913 break; 914 default: 915 return MCDisassembler::Fail; 916 } 917 918 Inst.addOperand(MCOperand::CreateReg(Register)); 919 return MCDisassembler::Success; 920 } 921 922 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 923 uint64_t Address, const void *Decoder) { 924 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 925 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 926 } 927 928 static const uint16_t SPRDecoderTable[] = { 929 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 930 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 931 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 932 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 933 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 934 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 935 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 936 ARM::S28, ARM::S29, ARM::S30, ARM::S31 937 }; 938 939 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 940 uint64_t Address, const void *Decoder) { 941 if (RegNo > 31) 942 return MCDisassembler::Fail; 943 944 unsigned Register = SPRDecoderTable[RegNo]; 945 Inst.addOperand(MCOperand::CreateReg(Register)); 946 return MCDisassembler::Success; 947 } 948 949 static const uint16_t DPRDecoderTable[] = { 950 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 951 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 952 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 953 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 954 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 955 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 956 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 957 ARM::D28, ARM::D29, ARM::D30, ARM::D31 958 }; 959 960 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 961 uint64_t Address, const void *Decoder) { 962 if (RegNo > 31) 963 return MCDisassembler::Fail; 964 965 unsigned Register = DPRDecoderTable[RegNo]; 966 Inst.addOperand(MCOperand::CreateReg(Register)); 967 return MCDisassembler::Success; 968 } 969 970 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 971 uint64_t Address, const void *Decoder) { 972 if (RegNo > 7) 973 return MCDisassembler::Fail; 974 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 975 } 976 977 static DecodeStatus 978 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 979 uint64_t Address, const void *Decoder) { 980 if (RegNo > 15) 981 return MCDisassembler::Fail; 982 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 983 } 984 985 static const uint16_t QPRDecoderTable[] = { 986 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 987 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 988 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 989 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 990 }; 991 992 993 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 994 uint64_t Address, const void *Decoder) { 995 if (RegNo > 31) 996 return MCDisassembler::Fail; 997 RegNo >>= 1; 998 999 unsigned Register = QPRDecoderTable[RegNo]; 1000 Inst.addOperand(MCOperand::CreateReg(Register)); 1001 return MCDisassembler::Success; 1002 } 1003 1004 static const uint16_t DPairDecoderTable[] = { 1005 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1006 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1007 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1008 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1009 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1010 ARM::Q15 1011 }; 1012 1013 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1014 uint64_t Address, const void *Decoder) { 1015 if (RegNo > 30) 1016 return MCDisassembler::Fail; 1017 1018 unsigned Register = DPairDecoderTable[RegNo]; 1019 Inst.addOperand(MCOperand::CreateReg(Register)); 1020 return MCDisassembler::Success; 1021 } 1022 1023 static const uint16_t DPairSpacedDecoderTable[] = { 1024 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1025 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1026 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1027 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1028 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1029 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1030 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1031 ARM::D28_D30, ARM::D29_D31 1032 }; 1033 1034 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1035 unsigned RegNo, 1036 uint64_t Address, 1037 const void *Decoder) { 1038 if (RegNo > 29) 1039 return MCDisassembler::Fail; 1040 1041 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1042 Inst.addOperand(MCOperand::CreateReg(Register)); 1043 return MCDisassembler::Success; 1044 } 1045 1046 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1047 uint64_t Address, const void *Decoder) { 1048 if (Val == 0xF) return MCDisassembler::Fail; 1049 // AL predicate is not allowed on Thumb1 branches. 1050 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1051 return MCDisassembler::Fail; 1052 Inst.addOperand(MCOperand::CreateImm(Val)); 1053 if (Val == ARMCC::AL) { 1054 Inst.addOperand(MCOperand::CreateReg(0)); 1055 } else 1056 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1057 return MCDisassembler::Success; 1058 } 1059 1060 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1061 uint64_t Address, const void *Decoder) { 1062 if (Val) 1063 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1064 else 1065 Inst.addOperand(MCOperand::CreateReg(0)); 1066 return MCDisassembler::Success; 1067 } 1068 1069 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1070 uint64_t Address, const void *Decoder) { 1071 uint32_t imm = Val & 0xFF; 1072 uint32_t rot = (Val & 0xF00) >> 7; 1073 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1074 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1075 return MCDisassembler::Success; 1076 } 1077 1078 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1079 uint64_t Address, const void *Decoder) { 1080 DecodeStatus S = MCDisassembler::Success; 1081 1082 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1083 unsigned type = fieldFromInstruction32(Val, 5, 2); 1084 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1085 1086 // Register-immediate 1087 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1088 return MCDisassembler::Fail; 1089 1090 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1091 switch (type) { 1092 case 0: 1093 Shift = ARM_AM::lsl; 1094 break; 1095 case 1: 1096 Shift = ARM_AM::lsr; 1097 break; 1098 case 2: 1099 Shift = ARM_AM::asr; 1100 break; 1101 case 3: 1102 Shift = ARM_AM::ror; 1103 break; 1104 } 1105 1106 if (Shift == ARM_AM::ror && imm == 0) 1107 Shift = ARM_AM::rrx; 1108 1109 unsigned Op = Shift | (imm << 3); 1110 Inst.addOperand(MCOperand::CreateImm(Op)); 1111 1112 return S; 1113 } 1114 1115 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1116 uint64_t Address, const void *Decoder) { 1117 DecodeStatus S = MCDisassembler::Success; 1118 1119 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1120 unsigned type = fieldFromInstruction32(Val, 5, 2); 1121 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1122 1123 // Register-register 1124 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1125 return MCDisassembler::Fail; 1126 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1127 return MCDisassembler::Fail; 1128 1129 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1130 switch (type) { 1131 case 0: 1132 Shift = ARM_AM::lsl; 1133 break; 1134 case 1: 1135 Shift = ARM_AM::lsr; 1136 break; 1137 case 2: 1138 Shift = ARM_AM::asr; 1139 break; 1140 case 3: 1141 Shift = ARM_AM::ror; 1142 break; 1143 } 1144 1145 Inst.addOperand(MCOperand::CreateImm(Shift)); 1146 1147 return S; 1148 } 1149 1150 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1151 uint64_t Address, const void *Decoder) { 1152 DecodeStatus S = MCDisassembler::Success; 1153 1154 bool writebackLoad = false; 1155 unsigned writebackReg = 0; 1156 switch (Inst.getOpcode()) { 1157 default: 1158 break; 1159 case ARM::LDMIA_UPD: 1160 case ARM::LDMDB_UPD: 1161 case ARM::LDMIB_UPD: 1162 case ARM::LDMDA_UPD: 1163 case ARM::t2LDMIA_UPD: 1164 case ARM::t2LDMDB_UPD: 1165 writebackLoad = true; 1166 writebackReg = Inst.getOperand(0).getReg(); 1167 break; 1168 } 1169 1170 // Empty register lists are not allowed. 1171 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1172 for (unsigned i = 0; i < 16; ++i) { 1173 if (Val & (1 << i)) { 1174 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1175 return MCDisassembler::Fail; 1176 // Writeback not allowed if Rn is in the target list. 1177 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1178 Check(S, MCDisassembler::SoftFail); 1179 } 1180 } 1181 1182 return S; 1183 } 1184 1185 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1186 uint64_t Address, const void *Decoder) { 1187 DecodeStatus S = MCDisassembler::Success; 1188 1189 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1190 unsigned regs = Val & 0xFF; 1191 1192 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1193 return MCDisassembler::Fail; 1194 for (unsigned i = 0; i < (regs - 1); ++i) { 1195 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1196 return MCDisassembler::Fail; 1197 } 1198 1199 return S; 1200 } 1201 1202 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1203 uint64_t Address, const void *Decoder) { 1204 DecodeStatus S = MCDisassembler::Success; 1205 1206 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1207 unsigned regs = (Val & 0xFF) / 2; 1208 1209 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1210 return MCDisassembler::Fail; 1211 for (unsigned i = 0; i < (regs - 1); ++i) { 1212 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1213 return MCDisassembler::Fail; 1214 } 1215 1216 return S; 1217 } 1218 1219 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1220 uint64_t Address, const void *Decoder) { 1221 // This operand encodes a mask of contiguous zeros between a specified MSB 1222 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1223 // the mask of all bits LSB-and-lower, and then xor them to create 1224 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1225 // create the final mask. 1226 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1227 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1228 1229 DecodeStatus S = MCDisassembler::Success; 1230 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1231 1232 uint32_t msb_mask = 0xFFFFFFFF; 1233 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1234 uint32_t lsb_mask = (1U << lsb) - 1; 1235 1236 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1237 return S; 1238 } 1239 1240 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1241 uint64_t Address, const void *Decoder) { 1242 DecodeStatus S = MCDisassembler::Success; 1243 1244 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1245 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1246 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1247 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1248 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1249 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1250 1251 switch (Inst.getOpcode()) { 1252 case ARM::LDC_OFFSET: 1253 case ARM::LDC_PRE: 1254 case ARM::LDC_POST: 1255 case ARM::LDC_OPTION: 1256 case ARM::LDCL_OFFSET: 1257 case ARM::LDCL_PRE: 1258 case ARM::LDCL_POST: 1259 case ARM::LDCL_OPTION: 1260 case ARM::STC_OFFSET: 1261 case ARM::STC_PRE: 1262 case ARM::STC_POST: 1263 case ARM::STC_OPTION: 1264 case ARM::STCL_OFFSET: 1265 case ARM::STCL_PRE: 1266 case ARM::STCL_POST: 1267 case ARM::STCL_OPTION: 1268 case ARM::t2LDC_OFFSET: 1269 case ARM::t2LDC_PRE: 1270 case ARM::t2LDC_POST: 1271 case ARM::t2LDC_OPTION: 1272 case ARM::t2LDCL_OFFSET: 1273 case ARM::t2LDCL_PRE: 1274 case ARM::t2LDCL_POST: 1275 case ARM::t2LDCL_OPTION: 1276 case ARM::t2STC_OFFSET: 1277 case ARM::t2STC_PRE: 1278 case ARM::t2STC_POST: 1279 case ARM::t2STC_OPTION: 1280 case ARM::t2STCL_OFFSET: 1281 case ARM::t2STCL_PRE: 1282 case ARM::t2STCL_POST: 1283 case ARM::t2STCL_OPTION: 1284 if (coproc == 0xA || coproc == 0xB) 1285 return MCDisassembler::Fail; 1286 break; 1287 default: 1288 break; 1289 } 1290 1291 Inst.addOperand(MCOperand::CreateImm(coproc)); 1292 Inst.addOperand(MCOperand::CreateImm(CRd)); 1293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1294 return MCDisassembler::Fail; 1295 1296 switch (Inst.getOpcode()) { 1297 case ARM::t2LDC2_OFFSET: 1298 case ARM::t2LDC2L_OFFSET: 1299 case ARM::t2LDC2_PRE: 1300 case ARM::t2LDC2L_PRE: 1301 case ARM::t2STC2_OFFSET: 1302 case ARM::t2STC2L_OFFSET: 1303 case ARM::t2STC2_PRE: 1304 case ARM::t2STC2L_PRE: 1305 case ARM::LDC2_OFFSET: 1306 case ARM::LDC2L_OFFSET: 1307 case ARM::LDC2_PRE: 1308 case ARM::LDC2L_PRE: 1309 case ARM::STC2_OFFSET: 1310 case ARM::STC2L_OFFSET: 1311 case ARM::STC2_PRE: 1312 case ARM::STC2L_PRE: 1313 case ARM::t2LDC_OFFSET: 1314 case ARM::t2LDCL_OFFSET: 1315 case ARM::t2LDC_PRE: 1316 case ARM::t2LDCL_PRE: 1317 case ARM::t2STC_OFFSET: 1318 case ARM::t2STCL_OFFSET: 1319 case ARM::t2STC_PRE: 1320 case ARM::t2STCL_PRE: 1321 case ARM::LDC_OFFSET: 1322 case ARM::LDCL_OFFSET: 1323 case ARM::LDC_PRE: 1324 case ARM::LDCL_PRE: 1325 case ARM::STC_OFFSET: 1326 case ARM::STCL_OFFSET: 1327 case ARM::STC_PRE: 1328 case ARM::STCL_PRE: 1329 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1330 Inst.addOperand(MCOperand::CreateImm(imm)); 1331 break; 1332 case ARM::t2LDC2_POST: 1333 case ARM::t2LDC2L_POST: 1334 case ARM::t2STC2_POST: 1335 case ARM::t2STC2L_POST: 1336 case ARM::LDC2_POST: 1337 case ARM::LDC2L_POST: 1338 case ARM::STC2_POST: 1339 case ARM::STC2L_POST: 1340 case ARM::t2LDC_POST: 1341 case ARM::t2LDCL_POST: 1342 case ARM::t2STC_POST: 1343 case ARM::t2STCL_POST: 1344 case ARM::LDC_POST: 1345 case ARM::LDCL_POST: 1346 case ARM::STC_POST: 1347 case ARM::STCL_POST: 1348 imm |= U << 8; 1349 // fall through. 1350 default: 1351 // The 'option' variant doesn't encode 'U' in the immediate since 1352 // the immediate is unsigned [0,255]. 1353 Inst.addOperand(MCOperand::CreateImm(imm)); 1354 break; 1355 } 1356 1357 switch (Inst.getOpcode()) { 1358 case ARM::LDC_OFFSET: 1359 case ARM::LDC_PRE: 1360 case ARM::LDC_POST: 1361 case ARM::LDC_OPTION: 1362 case ARM::LDCL_OFFSET: 1363 case ARM::LDCL_PRE: 1364 case ARM::LDCL_POST: 1365 case ARM::LDCL_OPTION: 1366 case ARM::STC_OFFSET: 1367 case ARM::STC_PRE: 1368 case ARM::STC_POST: 1369 case ARM::STC_OPTION: 1370 case ARM::STCL_OFFSET: 1371 case ARM::STCL_PRE: 1372 case ARM::STCL_POST: 1373 case ARM::STCL_OPTION: 1374 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1375 return MCDisassembler::Fail; 1376 break; 1377 default: 1378 break; 1379 } 1380 1381 return S; 1382 } 1383 1384 static DecodeStatus 1385 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1386 uint64_t Address, const void *Decoder) { 1387 DecodeStatus S = MCDisassembler::Success; 1388 1389 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1390 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1391 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1392 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1393 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1394 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1395 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1396 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1397 1398 // On stores, the writeback operand precedes Rt. 1399 switch (Inst.getOpcode()) { 1400 case ARM::STR_POST_IMM: 1401 case ARM::STR_POST_REG: 1402 case ARM::STRB_POST_IMM: 1403 case ARM::STRB_POST_REG: 1404 case ARM::STRT_POST_REG: 1405 case ARM::STRT_POST_IMM: 1406 case ARM::STRBT_POST_REG: 1407 case ARM::STRBT_POST_IMM: 1408 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1409 return MCDisassembler::Fail; 1410 break; 1411 default: 1412 break; 1413 } 1414 1415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1416 return MCDisassembler::Fail; 1417 1418 // On loads, the writeback operand comes after Rt. 1419 switch (Inst.getOpcode()) { 1420 case ARM::LDR_POST_IMM: 1421 case ARM::LDR_POST_REG: 1422 case ARM::LDRB_POST_IMM: 1423 case ARM::LDRB_POST_REG: 1424 case ARM::LDRBT_POST_REG: 1425 case ARM::LDRBT_POST_IMM: 1426 case ARM::LDRT_POST_REG: 1427 case ARM::LDRT_POST_IMM: 1428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1429 return MCDisassembler::Fail; 1430 break; 1431 default: 1432 break; 1433 } 1434 1435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1436 return MCDisassembler::Fail; 1437 1438 ARM_AM::AddrOpc Op = ARM_AM::add; 1439 if (!fieldFromInstruction32(Insn, 23, 1)) 1440 Op = ARM_AM::sub; 1441 1442 bool writeback = (P == 0) || (W == 1); 1443 unsigned idx_mode = 0; 1444 if (P && writeback) 1445 idx_mode = ARMII::IndexModePre; 1446 else if (!P && writeback) 1447 idx_mode = ARMII::IndexModePost; 1448 1449 if (writeback && (Rn == 15 || Rn == Rt)) 1450 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1451 1452 if (reg) { 1453 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1454 return MCDisassembler::Fail; 1455 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1456 switch( fieldFromInstruction32(Insn, 5, 2)) { 1457 case 0: 1458 Opc = ARM_AM::lsl; 1459 break; 1460 case 1: 1461 Opc = ARM_AM::lsr; 1462 break; 1463 case 2: 1464 Opc = ARM_AM::asr; 1465 break; 1466 case 3: 1467 Opc = ARM_AM::ror; 1468 break; 1469 default: 1470 return MCDisassembler::Fail; 1471 } 1472 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1473 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1474 1475 Inst.addOperand(MCOperand::CreateImm(imm)); 1476 } else { 1477 Inst.addOperand(MCOperand::CreateReg(0)); 1478 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1479 Inst.addOperand(MCOperand::CreateImm(tmp)); 1480 } 1481 1482 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1483 return MCDisassembler::Fail; 1484 1485 return S; 1486 } 1487 1488 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1489 uint64_t Address, const void *Decoder) { 1490 DecodeStatus S = MCDisassembler::Success; 1491 1492 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1493 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1494 unsigned type = fieldFromInstruction32(Val, 5, 2); 1495 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1496 unsigned U = fieldFromInstruction32(Val, 12, 1); 1497 1498 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1499 switch (type) { 1500 case 0: 1501 ShOp = ARM_AM::lsl; 1502 break; 1503 case 1: 1504 ShOp = ARM_AM::lsr; 1505 break; 1506 case 2: 1507 ShOp = ARM_AM::asr; 1508 break; 1509 case 3: 1510 ShOp = ARM_AM::ror; 1511 break; 1512 } 1513 1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1515 return MCDisassembler::Fail; 1516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1517 return MCDisassembler::Fail; 1518 unsigned shift; 1519 if (U) 1520 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1521 else 1522 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1523 Inst.addOperand(MCOperand::CreateImm(shift)); 1524 1525 return S; 1526 } 1527 1528 static DecodeStatus 1529 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1530 uint64_t Address, const void *Decoder) { 1531 DecodeStatus S = MCDisassembler::Success; 1532 1533 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1534 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1535 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1536 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1537 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1538 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1539 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1540 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1541 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1542 unsigned Rt2 = Rt + 1; 1543 1544 bool writeback = (W == 1) | (P == 0); 1545 1546 // For {LD,ST}RD, Rt must be even, else undefined. 1547 switch (Inst.getOpcode()) { 1548 case ARM::STRD: 1549 case ARM::STRD_PRE: 1550 case ARM::STRD_POST: 1551 case ARM::LDRD: 1552 case ARM::LDRD_PRE: 1553 case ARM::LDRD_POST: 1554 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1555 break; 1556 default: 1557 break; 1558 } 1559 switch (Inst.getOpcode()) { 1560 case ARM::STRD: 1561 case ARM::STRD_PRE: 1562 case ARM::STRD_POST: 1563 if (P == 0 && W == 1) 1564 S = MCDisassembler::SoftFail; 1565 1566 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1567 S = MCDisassembler::SoftFail; 1568 if (type && Rm == 15) 1569 S = MCDisassembler::SoftFail; 1570 if (Rt2 == 15) 1571 S = MCDisassembler::SoftFail; 1572 if (!type && fieldFromInstruction32(Insn, 8, 4)) 1573 S = MCDisassembler::SoftFail; 1574 break; 1575 case ARM::STRH: 1576 case ARM::STRH_PRE: 1577 case ARM::STRH_POST: 1578 if (Rt == 15) 1579 S = MCDisassembler::SoftFail; 1580 if (writeback && (Rn == 15 || Rn == Rt)) 1581 S = MCDisassembler::SoftFail; 1582 if (!type && Rm == 15) 1583 S = MCDisassembler::SoftFail; 1584 break; 1585 case ARM::LDRD: 1586 case ARM::LDRD_PRE: 1587 case ARM::LDRD_POST: 1588 if (type && Rn == 15){ 1589 if (Rt2 == 15) 1590 S = MCDisassembler::SoftFail; 1591 break; 1592 } 1593 if (P == 0 && W == 1) 1594 S = MCDisassembler::SoftFail; 1595 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1596 S = MCDisassembler::SoftFail; 1597 if (!type && writeback && Rn == 15) 1598 S = MCDisassembler::SoftFail; 1599 if (writeback && (Rn == Rt || Rn == Rt2)) 1600 S = MCDisassembler::SoftFail; 1601 break; 1602 case ARM::LDRH: 1603 case ARM::LDRH_PRE: 1604 case ARM::LDRH_POST: 1605 if (type && Rn == 15){ 1606 if (Rt == 15) 1607 S = MCDisassembler::SoftFail; 1608 break; 1609 } 1610 if (Rt == 15) 1611 S = MCDisassembler::SoftFail; 1612 if (!type && Rm == 15) 1613 S = MCDisassembler::SoftFail; 1614 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1615 S = MCDisassembler::SoftFail; 1616 break; 1617 case ARM::LDRSH: 1618 case ARM::LDRSH_PRE: 1619 case ARM::LDRSH_POST: 1620 case ARM::LDRSB: 1621 case ARM::LDRSB_PRE: 1622 case ARM::LDRSB_POST: 1623 if (type && Rn == 15){ 1624 if (Rt == 15) 1625 S = MCDisassembler::SoftFail; 1626 break; 1627 } 1628 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1629 S = MCDisassembler::SoftFail; 1630 if (!type && (Rt == 15 || Rm == 15)) 1631 S = MCDisassembler::SoftFail; 1632 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1633 S = MCDisassembler::SoftFail; 1634 break; 1635 default: 1636 break; 1637 } 1638 1639 if (writeback) { // Writeback 1640 if (P) 1641 U |= ARMII::IndexModePre << 9; 1642 else 1643 U |= ARMII::IndexModePost << 9; 1644 1645 // On stores, the writeback operand precedes Rt. 1646 switch (Inst.getOpcode()) { 1647 case ARM::STRD: 1648 case ARM::STRD_PRE: 1649 case ARM::STRD_POST: 1650 case ARM::STRH: 1651 case ARM::STRH_PRE: 1652 case ARM::STRH_POST: 1653 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1654 return MCDisassembler::Fail; 1655 break; 1656 default: 1657 break; 1658 } 1659 } 1660 1661 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1662 return MCDisassembler::Fail; 1663 switch (Inst.getOpcode()) { 1664 case ARM::STRD: 1665 case ARM::STRD_PRE: 1666 case ARM::STRD_POST: 1667 case ARM::LDRD: 1668 case ARM::LDRD_PRE: 1669 case ARM::LDRD_POST: 1670 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1671 return MCDisassembler::Fail; 1672 break; 1673 default: 1674 break; 1675 } 1676 1677 if (writeback) { 1678 // On loads, the writeback operand comes after Rt. 1679 switch (Inst.getOpcode()) { 1680 case ARM::LDRD: 1681 case ARM::LDRD_PRE: 1682 case ARM::LDRD_POST: 1683 case ARM::LDRH: 1684 case ARM::LDRH_PRE: 1685 case ARM::LDRH_POST: 1686 case ARM::LDRSH: 1687 case ARM::LDRSH_PRE: 1688 case ARM::LDRSH_POST: 1689 case ARM::LDRSB: 1690 case ARM::LDRSB_PRE: 1691 case ARM::LDRSB_POST: 1692 case ARM::LDRHTr: 1693 case ARM::LDRSBTr: 1694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1695 return MCDisassembler::Fail; 1696 break; 1697 default: 1698 break; 1699 } 1700 } 1701 1702 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1703 return MCDisassembler::Fail; 1704 1705 if (type) { 1706 Inst.addOperand(MCOperand::CreateReg(0)); 1707 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1708 } else { 1709 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1710 return MCDisassembler::Fail; 1711 Inst.addOperand(MCOperand::CreateImm(U)); 1712 } 1713 1714 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1715 return MCDisassembler::Fail; 1716 1717 return S; 1718 } 1719 1720 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1721 uint64_t Address, const void *Decoder) { 1722 DecodeStatus S = MCDisassembler::Success; 1723 1724 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1725 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1726 1727 switch (mode) { 1728 case 0: 1729 mode = ARM_AM::da; 1730 break; 1731 case 1: 1732 mode = ARM_AM::ia; 1733 break; 1734 case 2: 1735 mode = ARM_AM::db; 1736 break; 1737 case 3: 1738 mode = ARM_AM::ib; 1739 break; 1740 } 1741 1742 Inst.addOperand(MCOperand::CreateImm(mode)); 1743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1744 return MCDisassembler::Fail; 1745 1746 return S; 1747 } 1748 1749 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1750 unsigned Insn, 1751 uint64_t Address, const void *Decoder) { 1752 DecodeStatus S = MCDisassembler::Success; 1753 1754 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1755 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1756 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1757 1758 if (pred == 0xF) { 1759 switch (Inst.getOpcode()) { 1760 case ARM::LDMDA: 1761 Inst.setOpcode(ARM::RFEDA); 1762 break; 1763 case ARM::LDMDA_UPD: 1764 Inst.setOpcode(ARM::RFEDA_UPD); 1765 break; 1766 case ARM::LDMDB: 1767 Inst.setOpcode(ARM::RFEDB); 1768 break; 1769 case ARM::LDMDB_UPD: 1770 Inst.setOpcode(ARM::RFEDB_UPD); 1771 break; 1772 case ARM::LDMIA: 1773 Inst.setOpcode(ARM::RFEIA); 1774 break; 1775 case ARM::LDMIA_UPD: 1776 Inst.setOpcode(ARM::RFEIA_UPD); 1777 break; 1778 case ARM::LDMIB: 1779 Inst.setOpcode(ARM::RFEIB); 1780 break; 1781 case ARM::LDMIB_UPD: 1782 Inst.setOpcode(ARM::RFEIB_UPD); 1783 break; 1784 case ARM::STMDA: 1785 Inst.setOpcode(ARM::SRSDA); 1786 break; 1787 case ARM::STMDA_UPD: 1788 Inst.setOpcode(ARM::SRSDA_UPD); 1789 break; 1790 case ARM::STMDB: 1791 Inst.setOpcode(ARM::SRSDB); 1792 break; 1793 case ARM::STMDB_UPD: 1794 Inst.setOpcode(ARM::SRSDB_UPD); 1795 break; 1796 case ARM::STMIA: 1797 Inst.setOpcode(ARM::SRSIA); 1798 break; 1799 case ARM::STMIA_UPD: 1800 Inst.setOpcode(ARM::SRSIA_UPD); 1801 break; 1802 case ARM::STMIB: 1803 Inst.setOpcode(ARM::SRSIB); 1804 break; 1805 case ARM::STMIB_UPD: 1806 Inst.setOpcode(ARM::SRSIB_UPD); 1807 break; 1808 default: 1809 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1810 } 1811 1812 // For stores (which become SRS's, the only operand is the mode. 1813 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1814 Inst.addOperand( 1815 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1816 return S; 1817 } 1818 1819 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1820 } 1821 1822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1823 return MCDisassembler::Fail; 1824 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1825 return MCDisassembler::Fail; // Tied 1826 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1827 return MCDisassembler::Fail; 1828 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1829 return MCDisassembler::Fail; 1830 1831 return S; 1832 } 1833 1834 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1835 uint64_t Address, const void *Decoder) { 1836 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1837 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1838 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1839 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1840 1841 DecodeStatus S = MCDisassembler::Success; 1842 1843 // imod == '01' --> UNPREDICTABLE 1844 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1845 // return failure here. The '01' imod value is unprintable, so there's 1846 // nothing useful we could do even if we returned UNPREDICTABLE. 1847 1848 if (imod == 1) return MCDisassembler::Fail; 1849 1850 if (imod && M) { 1851 Inst.setOpcode(ARM::CPS3p); 1852 Inst.addOperand(MCOperand::CreateImm(imod)); 1853 Inst.addOperand(MCOperand::CreateImm(iflags)); 1854 Inst.addOperand(MCOperand::CreateImm(mode)); 1855 } else if (imod && !M) { 1856 Inst.setOpcode(ARM::CPS2p); 1857 Inst.addOperand(MCOperand::CreateImm(imod)); 1858 Inst.addOperand(MCOperand::CreateImm(iflags)); 1859 if (mode) S = MCDisassembler::SoftFail; 1860 } else if (!imod && M) { 1861 Inst.setOpcode(ARM::CPS1p); 1862 Inst.addOperand(MCOperand::CreateImm(mode)); 1863 if (iflags) S = MCDisassembler::SoftFail; 1864 } else { 1865 // imod == '00' && M == '0' --> UNPREDICTABLE 1866 Inst.setOpcode(ARM::CPS1p); 1867 Inst.addOperand(MCOperand::CreateImm(mode)); 1868 S = MCDisassembler::SoftFail; 1869 } 1870 1871 return S; 1872 } 1873 1874 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1875 uint64_t Address, const void *Decoder) { 1876 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1877 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1878 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1879 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1880 1881 DecodeStatus S = MCDisassembler::Success; 1882 1883 // imod == '01' --> UNPREDICTABLE 1884 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1885 // return failure here. The '01' imod value is unprintable, so there's 1886 // nothing useful we could do even if we returned UNPREDICTABLE. 1887 1888 if (imod == 1) return MCDisassembler::Fail; 1889 1890 if (imod && M) { 1891 Inst.setOpcode(ARM::t2CPS3p); 1892 Inst.addOperand(MCOperand::CreateImm(imod)); 1893 Inst.addOperand(MCOperand::CreateImm(iflags)); 1894 Inst.addOperand(MCOperand::CreateImm(mode)); 1895 } else if (imod && !M) { 1896 Inst.setOpcode(ARM::t2CPS2p); 1897 Inst.addOperand(MCOperand::CreateImm(imod)); 1898 Inst.addOperand(MCOperand::CreateImm(iflags)); 1899 if (mode) S = MCDisassembler::SoftFail; 1900 } else if (!imod && M) { 1901 Inst.setOpcode(ARM::t2CPS1p); 1902 Inst.addOperand(MCOperand::CreateImm(mode)); 1903 if (iflags) S = MCDisassembler::SoftFail; 1904 } else { 1905 // imod == '00' && M == '0' --> UNPREDICTABLE 1906 Inst.setOpcode(ARM::t2CPS1p); 1907 Inst.addOperand(MCOperand::CreateImm(mode)); 1908 S = MCDisassembler::SoftFail; 1909 } 1910 1911 return S; 1912 } 1913 1914 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1915 uint64_t Address, const void *Decoder) { 1916 DecodeStatus S = MCDisassembler::Success; 1917 1918 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1919 unsigned imm = 0; 1920 1921 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1922 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1923 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1924 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1925 1926 if (Inst.getOpcode() == ARM::t2MOVTi16) 1927 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1928 return MCDisassembler::Fail; 1929 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1930 return MCDisassembler::Fail; 1931 1932 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1933 Inst.addOperand(MCOperand::CreateImm(imm)); 1934 1935 return S; 1936 } 1937 1938 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1939 uint64_t Address, const void *Decoder) { 1940 DecodeStatus S = MCDisassembler::Success; 1941 1942 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1943 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1944 unsigned imm = 0; 1945 1946 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1947 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1948 1949 if (Inst.getOpcode() == ARM::MOVTi16) 1950 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1951 return MCDisassembler::Fail; 1952 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1953 return MCDisassembler::Fail; 1954 1955 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1956 Inst.addOperand(MCOperand::CreateImm(imm)); 1957 1958 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1959 return MCDisassembler::Fail; 1960 1961 return S; 1962 } 1963 1964 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 1965 uint64_t Address, const void *Decoder) { 1966 DecodeStatus S = MCDisassembler::Success; 1967 1968 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1969 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1970 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1971 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1972 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1973 1974 if (pred == 0xF) 1975 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1976 1977 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1978 return MCDisassembler::Fail; 1979 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1980 return MCDisassembler::Fail; 1981 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1982 return MCDisassembler::Fail; 1983 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1984 return MCDisassembler::Fail; 1985 1986 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1987 return MCDisassembler::Fail; 1988 1989 return S; 1990 } 1991 1992 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 1993 uint64_t Address, const void *Decoder) { 1994 DecodeStatus S = MCDisassembler::Success; 1995 1996 unsigned add = fieldFromInstruction32(Val, 12, 1); 1997 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1998 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1999 2000 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2001 return MCDisassembler::Fail; 2002 2003 if (!add) imm *= -1; 2004 if (imm == 0 && !add) imm = INT32_MIN; 2005 Inst.addOperand(MCOperand::CreateImm(imm)); 2006 if (Rn == 15) 2007 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2008 2009 return S; 2010 } 2011 2012 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2013 uint64_t Address, const void *Decoder) { 2014 DecodeStatus S = MCDisassembler::Success; 2015 2016 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2017 unsigned U = fieldFromInstruction32(Val, 8, 1); 2018 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2019 2020 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2021 return MCDisassembler::Fail; 2022 2023 if (U) 2024 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2025 else 2026 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2027 2028 return S; 2029 } 2030 2031 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2032 uint64_t Address, const void *Decoder) { 2033 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2034 } 2035 2036 static DecodeStatus 2037 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2038 uint64_t Address, const void *Decoder) { 2039 DecodeStatus S = MCDisassembler::Success; 2040 unsigned imm = (fieldFromInstruction32(Insn, 0, 11) << 0) | 2041 (fieldFromInstruction32(Insn, 11, 1) << 18) | 2042 (fieldFromInstruction32(Insn, 13, 1) << 17) | 2043 (fieldFromInstruction32(Insn, 16, 6) << 11) | 2044 (fieldFromInstruction32(Insn, 26, 1) << 19); 2045 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4, 2046 true, 4, Inst, Decoder)) 2047 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1))); 2048 return S; 2049 } 2050 2051 static DecodeStatus 2052 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2053 uint64_t Address, const void *Decoder) { 2054 DecodeStatus S = MCDisassembler::Success; 2055 2056 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2057 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 2058 2059 if (pred == 0xF) { 2060 Inst.setOpcode(ARM::BLXi); 2061 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 2062 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2063 true, 4, Inst, Decoder)) 2064 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2065 return S; 2066 } 2067 2068 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2069 true, 4, Inst, Decoder)) 2070 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2071 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2072 return MCDisassembler::Fail; 2073 2074 return S; 2075 } 2076 2077 2078 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2079 uint64_t Address, const void *Decoder) { 2080 DecodeStatus S = MCDisassembler::Success; 2081 2082 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 2083 unsigned align = fieldFromInstruction32(Val, 4, 2); 2084 2085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2086 return MCDisassembler::Fail; 2087 if (!align) 2088 Inst.addOperand(MCOperand::CreateImm(0)); 2089 else 2090 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2091 2092 return S; 2093 } 2094 2095 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2096 uint64_t Address, const void *Decoder) { 2097 DecodeStatus S = MCDisassembler::Success; 2098 2099 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2100 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2101 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2102 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2103 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2104 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2105 2106 // First output register 2107 switch (Inst.getOpcode()) { 2108 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2109 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2110 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2111 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2112 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2113 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2114 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2115 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2116 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2117 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2118 return MCDisassembler::Fail; 2119 break; 2120 case ARM::VLD2b16: 2121 case ARM::VLD2b32: 2122 case ARM::VLD2b8: 2123 case ARM::VLD2b16wb_fixed: 2124 case ARM::VLD2b16wb_register: 2125 case ARM::VLD2b32wb_fixed: 2126 case ARM::VLD2b32wb_register: 2127 case ARM::VLD2b8wb_fixed: 2128 case ARM::VLD2b8wb_register: 2129 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2130 return MCDisassembler::Fail; 2131 break; 2132 default: 2133 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2134 return MCDisassembler::Fail; 2135 } 2136 2137 // Second output register 2138 switch (Inst.getOpcode()) { 2139 case ARM::VLD3d8: 2140 case ARM::VLD3d16: 2141 case ARM::VLD3d32: 2142 case ARM::VLD3d8_UPD: 2143 case ARM::VLD3d16_UPD: 2144 case ARM::VLD3d32_UPD: 2145 case ARM::VLD4d8: 2146 case ARM::VLD4d16: 2147 case ARM::VLD4d32: 2148 case ARM::VLD4d8_UPD: 2149 case ARM::VLD4d16_UPD: 2150 case ARM::VLD4d32_UPD: 2151 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2152 return MCDisassembler::Fail; 2153 break; 2154 case ARM::VLD3q8: 2155 case ARM::VLD3q16: 2156 case ARM::VLD3q32: 2157 case ARM::VLD3q8_UPD: 2158 case ARM::VLD3q16_UPD: 2159 case ARM::VLD3q32_UPD: 2160 case ARM::VLD4q8: 2161 case ARM::VLD4q16: 2162 case ARM::VLD4q32: 2163 case ARM::VLD4q8_UPD: 2164 case ARM::VLD4q16_UPD: 2165 case ARM::VLD4q32_UPD: 2166 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2167 return MCDisassembler::Fail; 2168 default: 2169 break; 2170 } 2171 2172 // Third output register 2173 switch(Inst.getOpcode()) { 2174 case ARM::VLD3d8: 2175 case ARM::VLD3d16: 2176 case ARM::VLD3d32: 2177 case ARM::VLD3d8_UPD: 2178 case ARM::VLD3d16_UPD: 2179 case ARM::VLD3d32_UPD: 2180 case ARM::VLD4d8: 2181 case ARM::VLD4d16: 2182 case ARM::VLD4d32: 2183 case ARM::VLD4d8_UPD: 2184 case ARM::VLD4d16_UPD: 2185 case ARM::VLD4d32_UPD: 2186 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2187 return MCDisassembler::Fail; 2188 break; 2189 case ARM::VLD3q8: 2190 case ARM::VLD3q16: 2191 case ARM::VLD3q32: 2192 case ARM::VLD3q8_UPD: 2193 case ARM::VLD3q16_UPD: 2194 case ARM::VLD3q32_UPD: 2195 case ARM::VLD4q8: 2196 case ARM::VLD4q16: 2197 case ARM::VLD4q32: 2198 case ARM::VLD4q8_UPD: 2199 case ARM::VLD4q16_UPD: 2200 case ARM::VLD4q32_UPD: 2201 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2202 return MCDisassembler::Fail; 2203 break; 2204 default: 2205 break; 2206 } 2207 2208 // Fourth output register 2209 switch (Inst.getOpcode()) { 2210 case ARM::VLD4d8: 2211 case ARM::VLD4d16: 2212 case ARM::VLD4d32: 2213 case ARM::VLD4d8_UPD: 2214 case ARM::VLD4d16_UPD: 2215 case ARM::VLD4d32_UPD: 2216 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2217 return MCDisassembler::Fail; 2218 break; 2219 case ARM::VLD4q8: 2220 case ARM::VLD4q16: 2221 case ARM::VLD4q32: 2222 case ARM::VLD4q8_UPD: 2223 case ARM::VLD4q16_UPD: 2224 case ARM::VLD4q32_UPD: 2225 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2226 return MCDisassembler::Fail; 2227 break; 2228 default: 2229 break; 2230 } 2231 2232 // Writeback operand 2233 switch (Inst.getOpcode()) { 2234 case ARM::VLD1d8wb_fixed: 2235 case ARM::VLD1d16wb_fixed: 2236 case ARM::VLD1d32wb_fixed: 2237 case ARM::VLD1d64wb_fixed: 2238 case ARM::VLD1d8wb_register: 2239 case ARM::VLD1d16wb_register: 2240 case ARM::VLD1d32wb_register: 2241 case ARM::VLD1d64wb_register: 2242 case ARM::VLD1q8wb_fixed: 2243 case ARM::VLD1q16wb_fixed: 2244 case ARM::VLD1q32wb_fixed: 2245 case ARM::VLD1q64wb_fixed: 2246 case ARM::VLD1q8wb_register: 2247 case ARM::VLD1q16wb_register: 2248 case ARM::VLD1q32wb_register: 2249 case ARM::VLD1q64wb_register: 2250 case ARM::VLD1d8Twb_fixed: 2251 case ARM::VLD1d8Twb_register: 2252 case ARM::VLD1d16Twb_fixed: 2253 case ARM::VLD1d16Twb_register: 2254 case ARM::VLD1d32Twb_fixed: 2255 case ARM::VLD1d32Twb_register: 2256 case ARM::VLD1d64Twb_fixed: 2257 case ARM::VLD1d64Twb_register: 2258 case ARM::VLD1d8Qwb_fixed: 2259 case ARM::VLD1d8Qwb_register: 2260 case ARM::VLD1d16Qwb_fixed: 2261 case ARM::VLD1d16Qwb_register: 2262 case ARM::VLD1d32Qwb_fixed: 2263 case ARM::VLD1d32Qwb_register: 2264 case ARM::VLD1d64Qwb_fixed: 2265 case ARM::VLD1d64Qwb_register: 2266 case ARM::VLD2d8wb_fixed: 2267 case ARM::VLD2d16wb_fixed: 2268 case ARM::VLD2d32wb_fixed: 2269 case ARM::VLD2q8wb_fixed: 2270 case ARM::VLD2q16wb_fixed: 2271 case ARM::VLD2q32wb_fixed: 2272 case ARM::VLD2d8wb_register: 2273 case ARM::VLD2d16wb_register: 2274 case ARM::VLD2d32wb_register: 2275 case ARM::VLD2q8wb_register: 2276 case ARM::VLD2q16wb_register: 2277 case ARM::VLD2q32wb_register: 2278 case ARM::VLD2b8wb_fixed: 2279 case ARM::VLD2b16wb_fixed: 2280 case ARM::VLD2b32wb_fixed: 2281 case ARM::VLD2b8wb_register: 2282 case ARM::VLD2b16wb_register: 2283 case ARM::VLD2b32wb_register: 2284 Inst.addOperand(MCOperand::CreateImm(0)); 2285 break; 2286 case ARM::VLD3d8_UPD: 2287 case ARM::VLD3d16_UPD: 2288 case ARM::VLD3d32_UPD: 2289 case ARM::VLD3q8_UPD: 2290 case ARM::VLD3q16_UPD: 2291 case ARM::VLD3q32_UPD: 2292 case ARM::VLD4d8_UPD: 2293 case ARM::VLD4d16_UPD: 2294 case ARM::VLD4d32_UPD: 2295 case ARM::VLD4q8_UPD: 2296 case ARM::VLD4q16_UPD: 2297 case ARM::VLD4q32_UPD: 2298 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2299 return MCDisassembler::Fail; 2300 break; 2301 default: 2302 break; 2303 } 2304 2305 // AddrMode6 Base (register+alignment) 2306 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2307 return MCDisassembler::Fail; 2308 2309 // AddrMode6 Offset (register) 2310 switch (Inst.getOpcode()) { 2311 default: 2312 // The below have been updated to have explicit am6offset split 2313 // between fixed and register offset. For those instructions not 2314 // yet updated, we need to add an additional reg0 operand for the 2315 // fixed variant. 2316 // 2317 // The fixed offset encodes as Rm == 0xd, so we check for that. 2318 if (Rm == 0xd) { 2319 Inst.addOperand(MCOperand::CreateReg(0)); 2320 break; 2321 } 2322 // Fall through to handle the register offset variant. 2323 case ARM::VLD1d8wb_fixed: 2324 case ARM::VLD1d16wb_fixed: 2325 case ARM::VLD1d32wb_fixed: 2326 case ARM::VLD1d64wb_fixed: 2327 case ARM::VLD1d8Twb_fixed: 2328 case ARM::VLD1d16Twb_fixed: 2329 case ARM::VLD1d32Twb_fixed: 2330 case ARM::VLD1d64Twb_fixed: 2331 case ARM::VLD1d8Qwb_fixed: 2332 case ARM::VLD1d16Qwb_fixed: 2333 case ARM::VLD1d32Qwb_fixed: 2334 case ARM::VLD1d64Qwb_fixed: 2335 case ARM::VLD1d8wb_register: 2336 case ARM::VLD1d16wb_register: 2337 case ARM::VLD1d32wb_register: 2338 case ARM::VLD1d64wb_register: 2339 case ARM::VLD1q8wb_fixed: 2340 case ARM::VLD1q16wb_fixed: 2341 case ARM::VLD1q32wb_fixed: 2342 case ARM::VLD1q64wb_fixed: 2343 case ARM::VLD1q8wb_register: 2344 case ARM::VLD1q16wb_register: 2345 case ARM::VLD1q32wb_register: 2346 case ARM::VLD1q64wb_register: 2347 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2348 // variant encodes Rm == 0xf. Anything else is a register offset post- 2349 // increment and we need to add the register operand to the instruction. 2350 if (Rm != 0xD && Rm != 0xF && 2351 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2352 return MCDisassembler::Fail; 2353 break; 2354 case ARM::VLD2d8wb_fixed: 2355 case ARM::VLD2d16wb_fixed: 2356 case ARM::VLD2d32wb_fixed: 2357 case ARM::VLD2b8wb_fixed: 2358 case ARM::VLD2b16wb_fixed: 2359 case ARM::VLD2b32wb_fixed: 2360 case ARM::VLD2q8wb_fixed: 2361 case ARM::VLD2q16wb_fixed: 2362 case ARM::VLD2q32wb_fixed: 2363 break; 2364 } 2365 2366 return S; 2367 } 2368 2369 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2370 uint64_t Address, const void *Decoder) { 2371 DecodeStatus S = MCDisassembler::Success; 2372 2373 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2374 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2375 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2376 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2377 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2378 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2379 2380 // Writeback Operand 2381 switch (Inst.getOpcode()) { 2382 case ARM::VST1d8wb_fixed: 2383 case ARM::VST1d16wb_fixed: 2384 case ARM::VST1d32wb_fixed: 2385 case ARM::VST1d64wb_fixed: 2386 case ARM::VST1d8wb_register: 2387 case ARM::VST1d16wb_register: 2388 case ARM::VST1d32wb_register: 2389 case ARM::VST1d64wb_register: 2390 case ARM::VST1q8wb_fixed: 2391 case ARM::VST1q16wb_fixed: 2392 case ARM::VST1q32wb_fixed: 2393 case ARM::VST1q64wb_fixed: 2394 case ARM::VST1q8wb_register: 2395 case ARM::VST1q16wb_register: 2396 case ARM::VST1q32wb_register: 2397 case ARM::VST1q64wb_register: 2398 case ARM::VST1d8Twb_fixed: 2399 case ARM::VST1d16Twb_fixed: 2400 case ARM::VST1d32Twb_fixed: 2401 case ARM::VST1d64Twb_fixed: 2402 case ARM::VST1d8Twb_register: 2403 case ARM::VST1d16Twb_register: 2404 case ARM::VST1d32Twb_register: 2405 case ARM::VST1d64Twb_register: 2406 case ARM::VST1d8Qwb_fixed: 2407 case ARM::VST1d16Qwb_fixed: 2408 case ARM::VST1d32Qwb_fixed: 2409 case ARM::VST1d64Qwb_fixed: 2410 case ARM::VST1d8Qwb_register: 2411 case ARM::VST1d16Qwb_register: 2412 case ARM::VST1d32Qwb_register: 2413 case ARM::VST1d64Qwb_register: 2414 case ARM::VST2d8wb_fixed: 2415 case ARM::VST2d16wb_fixed: 2416 case ARM::VST2d32wb_fixed: 2417 case ARM::VST2d8wb_register: 2418 case ARM::VST2d16wb_register: 2419 case ARM::VST2d32wb_register: 2420 case ARM::VST2q8wb_fixed: 2421 case ARM::VST2q16wb_fixed: 2422 case ARM::VST2q32wb_fixed: 2423 case ARM::VST2q8wb_register: 2424 case ARM::VST2q16wb_register: 2425 case ARM::VST2q32wb_register: 2426 case ARM::VST2b8wb_fixed: 2427 case ARM::VST2b16wb_fixed: 2428 case ARM::VST2b32wb_fixed: 2429 case ARM::VST2b8wb_register: 2430 case ARM::VST2b16wb_register: 2431 case ARM::VST2b32wb_register: 2432 if (Rm == 0xF) 2433 return MCDisassembler::Fail; 2434 Inst.addOperand(MCOperand::CreateImm(0)); 2435 break; 2436 case ARM::VST3d8_UPD: 2437 case ARM::VST3d16_UPD: 2438 case ARM::VST3d32_UPD: 2439 case ARM::VST3q8_UPD: 2440 case ARM::VST3q16_UPD: 2441 case ARM::VST3q32_UPD: 2442 case ARM::VST4d8_UPD: 2443 case ARM::VST4d16_UPD: 2444 case ARM::VST4d32_UPD: 2445 case ARM::VST4q8_UPD: 2446 case ARM::VST4q16_UPD: 2447 case ARM::VST4q32_UPD: 2448 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2449 return MCDisassembler::Fail; 2450 break; 2451 default: 2452 break; 2453 } 2454 2455 // AddrMode6 Base (register+alignment) 2456 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2457 return MCDisassembler::Fail; 2458 2459 // AddrMode6 Offset (register) 2460 switch (Inst.getOpcode()) { 2461 default: 2462 if (Rm == 0xD) 2463 Inst.addOperand(MCOperand::CreateReg(0)); 2464 else if (Rm != 0xF) { 2465 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2466 return MCDisassembler::Fail; 2467 } 2468 break; 2469 case ARM::VST1d8wb_fixed: 2470 case ARM::VST1d16wb_fixed: 2471 case ARM::VST1d32wb_fixed: 2472 case ARM::VST1d64wb_fixed: 2473 case ARM::VST1q8wb_fixed: 2474 case ARM::VST1q16wb_fixed: 2475 case ARM::VST1q32wb_fixed: 2476 case ARM::VST1q64wb_fixed: 2477 case ARM::VST1d8Twb_fixed: 2478 case ARM::VST1d16Twb_fixed: 2479 case ARM::VST1d32Twb_fixed: 2480 case ARM::VST1d64Twb_fixed: 2481 case ARM::VST1d8Qwb_fixed: 2482 case ARM::VST1d16Qwb_fixed: 2483 case ARM::VST1d32Qwb_fixed: 2484 case ARM::VST1d64Qwb_fixed: 2485 case ARM::VST2d8wb_fixed: 2486 case ARM::VST2d16wb_fixed: 2487 case ARM::VST2d32wb_fixed: 2488 case ARM::VST2q8wb_fixed: 2489 case ARM::VST2q16wb_fixed: 2490 case ARM::VST2q32wb_fixed: 2491 case ARM::VST2b8wb_fixed: 2492 case ARM::VST2b16wb_fixed: 2493 case ARM::VST2b32wb_fixed: 2494 break; 2495 } 2496 2497 2498 // First input register 2499 switch (Inst.getOpcode()) { 2500 case ARM::VST1q16: 2501 case ARM::VST1q32: 2502 case ARM::VST1q64: 2503 case ARM::VST1q8: 2504 case ARM::VST1q16wb_fixed: 2505 case ARM::VST1q16wb_register: 2506 case ARM::VST1q32wb_fixed: 2507 case ARM::VST1q32wb_register: 2508 case ARM::VST1q64wb_fixed: 2509 case ARM::VST1q64wb_register: 2510 case ARM::VST1q8wb_fixed: 2511 case ARM::VST1q8wb_register: 2512 case ARM::VST2d16: 2513 case ARM::VST2d32: 2514 case ARM::VST2d8: 2515 case ARM::VST2d16wb_fixed: 2516 case ARM::VST2d16wb_register: 2517 case ARM::VST2d32wb_fixed: 2518 case ARM::VST2d32wb_register: 2519 case ARM::VST2d8wb_fixed: 2520 case ARM::VST2d8wb_register: 2521 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2522 return MCDisassembler::Fail; 2523 break; 2524 case ARM::VST2b16: 2525 case ARM::VST2b32: 2526 case ARM::VST2b8: 2527 case ARM::VST2b16wb_fixed: 2528 case ARM::VST2b16wb_register: 2529 case ARM::VST2b32wb_fixed: 2530 case ARM::VST2b32wb_register: 2531 case ARM::VST2b8wb_fixed: 2532 case ARM::VST2b8wb_register: 2533 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2534 return MCDisassembler::Fail; 2535 break; 2536 default: 2537 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2538 return MCDisassembler::Fail; 2539 } 2540 2541 // Second input register 2542 switch (Inst.getOpcode()) { 2543 case ARM::VST3d8: 2544 case ARM::VST3d16: 2545 case ARM::VST3d32: 2546 case ARM::VST3d8_UPD: 2547 case ARM::VST3d16_UPD: 2548 case ARM::VST3d32_UPD: 2549 case ARM::VST4d8: 2550 case ARM::VST4d16: 2551 case ARM::VST4d32: 2552 case ARM::VST4d8_UPD: 2553 case ARM::VST4d16_UPD: 2554 case ARM::VST4d32_UPD: 2555 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2556 return MCDisassembler::Fail; 2557 break; 2558 case ARM::VST3q8: 2559 case ARM::VST3q16: 2560 case ARM::VST3q32: 2561 case ARM::VST3q8_UPD: 2562 case ARM::VST3q16_UPD: 2563 case ARM::VST3q32_UPD: 2564 case ARM::VST4q8: 2565 case ARM::VST4q16: 2566 case ARM::VST4q32: 2567 case ARM::VST4q8_UPD: 2568 case ARM::VST4q16_UPD: 2569 case ARM::VST4q32_UPD: 2570 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2571 return MCDisassembler::Fail; 2572 break; 2573 default: 2574 break; 2575 } 2576 2577 // Third input register 2578 switch (Inst.getOpcode()) { 2579 case ARM::VST3d8: 2580 case ARM::VST3d16: 2581 case ARM::VST3d32: 2582 case ARM::VST3d8_UPD: 2583 case ARM::VST3d16_UPD: 2584 case ARM::VST3d32_UPD: 2585 case ARM::VST4d8: 2586 case ARM::VST4d16: 2587 case ARM::VST4d32: 2588 case ARM::VST4d8_UPD: 2589 case ARM::VST4d16_UPD: 2590 case ARM::VST4d32_UPD: 2591 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2592 return MCDisassembler::Fail; 2593 break; 2594 case ARM::VST3q8: 2595 case ARM::VST3q16: 2596 case ARM::VST3q32: 2597 case ARM::VST3q8_UPD: 2598 case ARM::VST3q16_UPD: 2599 case ARM::VST3q32_UPD: 2600 case ARM::VST4q8: 2601 case ARM::VST4q16: 2602 case ARM::VST4q32: 2603 case ARM::VST4q8_UPD: 2604 case ARM::VST4q16_UPD: 2605 case ARM::VST4q32_UPD: 2606 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2607 return MCDisassembler::Fail; 2608 break; 2609 default: 2610 break; 2611 } 2612 2613 // Fourth input register 2614 switch (Inst.getOpcode()) { 2615 case ARM::VST4d8: 2616 case ARM::VST4d16: 2617 case ARM::VST4d32: 2618 case ARM::VST4d8_UPD: 2619 case ARM::VST4d16_UPD: 2620 case ARM::VST4d32_UPD: 2621 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2622 return MCDisassembler::Fail; 2623 break; 2624 case ARM::VST4q8: 2625 case ARM::VST4q16: 2626 case ARM::VST4q32: 2627 case ARM::VST4q8_UPD: 2628 case ARM::VST4q16_UPD: 2629 case ARM::VST4q32_UPD: 2630 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2631 return MCDisassembler::Fail; 2632 break; 2633 default: 2634 break; 2635 } 2636 2637 return S; 2638 } 2639 2640 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2641 uint64_t Address, const void *Decoder) { 2642 DecodeStatus S = MCDisassembler::Success; 2643 2644 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2645 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2646 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2647 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2648 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2649 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2650 2651 align *= (1 << size); 2652 2653 switch (Inst.getOpcode()) { 2654 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2655 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2656 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2657 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2658 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2659 return MCDisassembler::Fail; 2660 break; 2661 default: 2662 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2663 return MCDisassembler::Fail; 2664 break; 2665 } 2666 if (Rm != 0xF) { 2667 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2668 return MCDisassembler::Fail; 2669 } 2670 2671 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2672 return MCDisassembler::Fail; 2673 Inst.addOperand(MCOperand::CreateImm(align)); 2674 2675 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2676 // variant encodes Rm == 0xf. Anything else is a register offset post- 2677 // increment and we need to add the register operand to the instruction. 2678 if (Rm != 0xD && Rm != 0xF && 2679 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2680 return MCDisassembler::Fail; 2681 2682 return S; 2683 } 2684 2685 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2686 uint64_t Address, const void *Decoder) { 2687 DecodeStatus S = MCDisassembler::Success; 2688 2689 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2690 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2691 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2692 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2693 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2694 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2695 align *= 2*size; 2696 2697 switch (Inst.getOpcode()) { 2698 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2699 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2700 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2701 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2702 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2703 return MCDisassembler::Fail; 2704 break; 2705 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2706 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2707 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2708 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2709 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2710 return MCDisassembler::Fail; 2711 break; 2712 default: 2713 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2714 return MCDisassembler::Fail; 2715 break; 2716 } 2717 2718 if (Rm != 0xF) 2719 Inst.addOperand(MCOperand::CreateImm(0)); 2720 2721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2722 return MCDisassembler::Fail; 2723 Inst.addOperand(MCOperand::CreateImm(align)); 2724 2725 if (Rm != 0xD && Rm != 0xF) { 2726 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2727 return MCDisassembler::Fail; 2728 } 2729 2730 return S; 2731 } 2732 2733 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2734 uint64_t Address, const void *Decoder) { 2735 DecodeStatus S = MCDisassembler::Success; 2736 2737 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2738 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2739 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2740 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2741 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2742 2743 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2744 return MCDisassembler::Fail; 2745 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2746 return MCDisassembler::Fail; 2747 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2748 return MCDisassembler::Fail; 2749 if (Rm != 0xF) { 2750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2751 return MCDisassembler::Fail; 2752 } 2753 2754 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2755 return MCDisassembler::Fail; 2756 Inst.addOperand(MCOperand::CreateImm(0)); 2757 2758 if (Rm == 0xD) 2759 Inst.addOperand(MCOperand::CreateReg(0)); 2760 else if (Rm != 0xF) { 2761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2762 return MCDisassembler::Fail; 2763 } 2764 2765 return S; 2766 } 2767 2768 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2769 uint64_t Address, const void *Decoder) { 2770 DecodeStatus S = MCDisassembler::Success; 2771 2772 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2773 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2774 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2775 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2776 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2777 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2778 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2779 2780 if (size == 0x3) { 2781 size = 4; 2782 align = 16; 2783 } else { 2784 if (size == 2) { 2785 size = 1 << size; 2786 align *= 8; 2787 } else { 2788 size = 1 << size; 2789 align *= 4*size; 2790 } 2791 } 2792 2793 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2794 return MCDisassembler::Fail; 2795 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2796 return MCDisassembler::Fail; 2797 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2798 return MCDisassembler::Fail; 2799 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2800 return MCDisassembler::Fail; 2801 if (Rm != 0xF) { 2802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2803 return MCDisassembler::Fail; 2804 } 2805 2806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2807 return MCDisassembler::Fail; 2808 Inst.addOperand(MCOperand::CreateImm(align)); 2809 2810 if (Rm == 0xD) 2811 Inst.addOperand(MCOperand::CreateReg(0)); 2812 else if (Rm != 0xF) { 2813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2814 return MCDisassembler::Fail; 2815 } 2816 2817 return S; 2818 } 2819 2820 static DecodeStatus 2821 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2822 uint64_t Address, const void *Decoder) { 2823 DecodeStatus S = MCDisassembler::Success; 2824 2825 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2826 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2827 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2828 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2829 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2830 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2831 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2832 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2833 2834 if (Q) { 2835 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2836 return MCDisassembler::Fail; 2837 } else { 2838 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2839 return MCDisassembler::Fail; 2840 } 2841 2842 Inst.addOperand(MCOperand::CreateImm(imm)); 2843 2844 switch (Inst.getOpcode()) { 2845 case ARM::VORRiv4i16: 2846 case ARM::VORRiv2i32: 2847 case ARM::VBICiv4i16: 2848 case ARM::VBICiv2i32: 2849 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2850 return MCDisassembler::Fail; 2851 break; 2852 case ARM::VORRiv8i16: 2853 case ARM::VORRiv4i32: 2854 case ARM::VBICiv8i16: 2855 case ARM::VBICiv4i32: 2856 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2857 return MCDisassembler::Fail; 2858 break; 2859 default: 2860 break; 2861 } 2862 2863 return S; 2864 } 2865 2866 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2867 uint64_t Address, const void *Decoder) { 2868 DecodeStatus S = MCDisassembler::Success; 2869 2870 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2871 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2872 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2873 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2874 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2875 2876 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2877 return MCDisassembler::Fail; 2878 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2879 return MCDisassembler::Fail; 2880 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2881 2882 return S; 2883 } 2884 2885 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2886 uint64_t Address, const void *Decoder) { 2887 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2888 return MCDisassembler::Success; 2889 } 2890 2891 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2892 uint64_t Address, const void *Decoder) { 2893 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2894 return MCDisassembler::Success; 2895 } 2896 2897 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2898 uint64_t Address, const void *Decoder) { 2899 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2900 return MCDisassembler::Success; 2901 } 2902 2903 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2904 uint64_t Address, const void *Decoder) { 2905 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2906 return MCDisassembler::Success; 2907 } 2908 2909 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2910 uint64_t Address, const void *Decoder) { 2911 DecodeStatus S = MCDisassembler::Success; 2912 2913 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2914 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2915 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2916 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2917 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2918 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2919 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2920 2921 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2922 return MCDisassembler::Fail; 2923 if (op) { 2924 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2925 return MCDisassembler::Fail; // Writeback 2926 } 2927 2928 switch (Inst.getOpcode()) { 2929 case ARM::VTBL2: 2930 case ARM::VTBX2: 2931 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 2932 return MCDisassembler::Fail; 2933 break; 2934 default: 2935 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 2936 return MCDisassembler::Fail; 2937 } 2938 2939 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2940 return MCDisassembler::Fail; 2941 2942 return S; 2943 } 2944 2945 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 2946 uint64_t Address, const void *Decoder) { 2947 DecodeStatus S = MCDisassembler::Success; 2948 2949 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2950 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2951 2952 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2953 return MCDisassembler::Fail; 2954 2955 switch(Inst.getOpcode()) { 2956 default: 2957 return MCDisassembler::Fail; 2958 case ARM::tADR: 2959 break; // tADR does not explicitly represent the PC as an operand. 2960 case ARM::tADDrSPi: 2961 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2962 break; 2963 } 2964 2965 Inst.addOperand(MCOperand::CreateImm(imm)); 2966 return S; 2967 } 2968 2969 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 2970 uint64_t Address, const void *Decoder) { 2971 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 2972 true, 2, Inst, Decoder)) 2973 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2974 return MCDisassembler::Success; 2975 } 2976 2977 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 2978 uint64_t Address, const void *Decoder) { 2979 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 2980 true, 4, Inst, Decoder)) 2981 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2982 return MCDisassembler::Success; 2983 } 2984 2985 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 2986 uint64_t Address, const void *Decoder) { 2987 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4, 2988 true, 2, Inst, Decoder)) 2989 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2990 return MCDisassembler::Success; 2991 } 2992 2993 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 2994 uint64_t Address, const void *Decoder) { 2995 DecodeStatus S = MCDisassembler::Success; 2996 2997 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2998 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2999 3000 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3001 return MCDisassembler::Fail; 3002 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3003 return MCDisassembler::Fail; 3004 3005 return S; 3006 } 3007 3008 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3009 uint64_t Address, const void *Decoder) { 3010 DecodeStatus S = MCDisassembler::Success; 3011 3012 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 3013 unsigned imm = fieldFromInstruction32(Val, 3, 5); 3014 3015 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3016 return MCDisassembler::Fail; 3017 Inst.addOperand(MCOperand::CreateImm(imm)); 3018 3019 return S; 3020 } 3021 3022 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3023 uint64_t Address, const void *Decoder) { 3024 unsigned imm = Val << 2; 3025 3026 Inst.addOperand(MCOperand::CreateImm(imm)); 3027 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3028 3029 return MCDisassembler::Success; 3030 } 3031 3032 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3033 uint64_t Address, const void *Decoder) { 3034 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3035 Inst.addOperand(MCOperand::CreateImm(Val)); 3036 3037 return MCDisassembler::Success; 3038 } 3039 3040 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3041 uint64_t Address, const void *Decoder) { 3042 DecodeStatus S = MCDisassembler::Success; 3043 3044 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 3045 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 3046 unsigned imm = fieldFromInstruction32(Val, 0, 2); 3047 3048 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3049 return MCDisassembler::Fail; 3050 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3051 return MCDisassembler::Fail; 3052 Inst.addOperand(MCOperand::CreateImm(imm)); 3053 3054 return S; 3055 } 3056 3057 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3058 uint64_t Address, const void *Decoder) { 3059 DecodeStatus S = MCDisassembler::Success; 3060 3061 switch (Inst.getOpcode()) { 3062 case ARM::t2PLDs: 3063 case ARM::t2PLDWs: 3064 case ARM::t2PLIs: 3065 break; 3066 default: { 3067 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3068 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3069 return MCDisassembler::Fail; 3070 } 3071 } 3072 3073 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3074 if (Rn == 0xF) { 3075 switch (Inst.getOpcode()) { 3076 case ARM::t2LDRBs: 3077 Inst.setOpcode(ARM::t2LDRBpci); 3078 break; 3079 case ARM::t2LDRHs: 3080 Inst.setOpcode(ARM::t2LDRHpci); 3081 break; 3082 case ARM::t2LDRSHs: 3083 Inst.setOpcode(ARM::t2LDRSHpci); 3084 break; 3085 case ARM::t2LDRSBs: 3086 Inst.setOpcode(ARM::t2LDRSBpci); 3087 break; 3088 case ARM::t2PLDs: 3089 Inst.setOpcode(ARM::t2PLDi12); 3090 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3091 break; 3092 default: 3093 return MCDisassembler::Fail; 3094 } 3095 3096 int imm = fieldFromInstruction32(Insn, 0, 12); 3097 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 3098 Inst.addOperand(MCOperand::CreateImm(imm)); 3099 3100 return S; 3101 } 3102 3103 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 3104 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 3105 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 3106 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3107 return MCDisassembler::Fail; 3108 3109 return S; 3110 } 3111 3112 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3113 uint64_t Address, const void *Decoder) { 3114 int imm = Val & 0xFF; 3115 if (!(Val & 0x100)) imm *= -1; 3116 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 3117 3118 return MCDisassembler::Success; 3119 } 3120 3121 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3122 uint64_t Address, const void *Decoder) { 3123 DecodeStatus S = MCDisassembler::Success; 3124 3125 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3126 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3127 3128 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3129 return MCDisassembler::Fail; 3130 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3131 return MCDisassembler::Fail; 3132 3133 return S; 3134 } 3135 3136 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3137 uint64_t Address, const void *Decoder) { 3138 DecodeStatus S = MCDisassembler::Success; 3139 3140 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 3141 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3142 3143 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3144 return MCDisassembler::Fail; 3145 3146 Inst.addOperand(MCOperand::CreateImm(imm)); 3147 3148 return S; 3149 } 3150 3151 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3152 uint64_t Address, const void *Decoder) { 3153 int imm = Val & 0xFF; 3154 if (Val == 0) 3155 imm = INT32_MIN; 3156 else if (!(Val & 0x100)) 3157 imm *= -1; 3158 Inst.addOperand(MCOperand::CreateImm(imm)); 3159 3160 return MCDisassembler::Success; 3161 } 3162 3163 3164 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3165 uint64_t Address, const void *Decoder) { 3166 DecodeStatus S = MCDisassembler::Success; 3167 3168 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3169 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3170 3171 // Some instructions always use an additive offset. 3172 switch (Inst.getOpcode()) { 3173 case ARM::t2LDRT: 3174 case ARM::t2LDRBT: 3175 case ARM::t2LDRHT: 3176 case ARM::t2LDRSBT: 3177 case ARM::t2LDRSHT: 3178 case ARM::t2STRT: 3179 case ARM::t2STRBT: 3180 case ARM::t2STRHT: 3181 imm |= 0x100; 3182 break; 3183 default: 3184 break; 3185 } 3186 3187 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3188 return MCDisassembler::Fail; 3189 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3190 return MCDisassembler::Fail; 3191 3192 return S; 3193 } 3194 3195 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3196 uint64_t Address, const void *Decoder) { 3197 DecodeStatus S = MCDisassembler::Success; 3198 3199 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3200 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3201 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3202 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 3203 addr |= Rn << 9; 3204 unsigned load = fieldFromInstruction32(Insn, 20, 1); 3205 3206 if (!load) { 3207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3208 return MCDisassembler::Fail; 3209 } 3210 3211 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3212 return MCDisassembler::Fail; 3213 3214 if (load) { 3215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3216 return MCDisassembler::Fail; 3217 } 3218 3219 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3220 return MCDisassembler::Fail; 3221 3222 return S; 3223 } 3224 3225 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3226 uint64_t Address, const void *Decoder) { 3227 DecodeStatus S = MCDisassembler::Success; 3228 3229 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 3230 unsigned imm = fieldFromInstruction32(Val, 0, 12); 3231 3232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3233 return MCDisassembler::Fail; 3234 Inst.addOperand(MCOperand::CreateImm(imm)); 3235 3236 return S; 3237 } 3238 3239 3240 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3241 uint64_t Address, const void *Decoder) { 3242 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 3243 3244 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3245 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3246 Inst.addOperand(MCOperand::CreateImm(imm)); 3247 3248 return MCDisassembler::Success; 3249 } 3250 3251 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3252 uint64_t Address, const void *Decoder) { 3253 DecodeStatus S = MCDisassembler::Success; 3254 3255 if (Inst.getOpcode() == ARM::tADDrSP) { 3256 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3257 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3258 3259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3260 return MCDisassembler::Fail; 3261 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3262 return MCDisassembler::Fail; 3263 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3264 } else if (Inst.getOpcode() == ARM::tADDspr) { 3265 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3266 3267 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3268 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3270 return MCDisassembler::Fail; 3271 } 3272 3273 return S; 3274 } 3275 3276 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3277 uint64_t Address, const void *Decoder) { 3278 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3279 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3280 3281 Inst.addOperand(MCOperand::CreateImm(imod)); 3282 Inst.addOperand(MCOperand::CreateImm(flags)); 3283 3284 return MCDisassembler::Success; 3285 } 3286 3287 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3288 uint64_t Address, const void *Decoder) { 3289 DecodeStatus S = MCDisassembler::Success; 3290 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3291 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3292 3293 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3294 return MCDisassembler::Fail; 3295 Inst.addOperand(MCOperand::CreateImm(add)); 3296 3297 return S; 3298 } 3299 3300 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3301 uint64_t Address, const void *Decoder) { 3302 if (!tryAddingSymbolicOperand(Address, 3303 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3304 true, 4, Inst, Decoder)) 3305 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3306 return MCDisassembler::Success; 3307 } 3308 3309 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3310 uint64_t Address, const void *Decoder) { 3311 if (Val == 0xA || Val == 0xB) 3312 return MCDisassembler::Fail; 3313 3314 Inst.addOperand(MCOperand::CreateImm(Val)); 3315 return MCDisassembler::Success; 3316 } 3317 3318 static DecodeStatus 3319 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3320 uint64_t Address, const void *Decoder) { 3321 DecodeStatus S = MCDisassembler::Success; 3322 3323 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3324 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3325 3326 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3328 return MCDisassembler::Fail; 3329 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3330 return MCDisassembler::Fail; 3331 return S; 3332 } 3333 3334 static DecodeStatus 3335 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3336 uint64_t Address, const void *Decoder) { 3337 DecodeStatus S = MCDisassembler::Success; 3338 3339 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3340 if (pred == 0xE || pred == 0xF) { 3341 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3342 switch (opc) { 3343 default: 3344 return MCDisassembler::Fail; 3345 case 0xf3bf8f4: 3346 Inst.setOpcode(ARM::t2DSB); 3347 break; 3348 case 0xf3bf8f5: 3349 Inst.setOpcode(ARM::t2DMB); 3350 break; 3351 case 0xf3bf8f6: 3352 Inst.setOpcode(ARM::t2ISB); 3353 break; 3354 } 3355 3356 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3357 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3358 } 3359 3360 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3361 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3362 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3363 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3364 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3365 3366 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3367 return MCDisassembler::Fail; 3368 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3369 return MCDisassembler::Fail; 3370 3371 return S; 3372 } 3373 3374 // Decode a shifted immediate operand. These basically consist 3375 // of an 8-bit value, and a 4-bit directive that specifies either 3376 // a splat operation or a rotation. 3377 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3378 uint64_t Address, const void *Decoder) { 3379 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3380 if (ctrl == 0) { 3381 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3382 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3383 switch (byte) { 3384 case 0: 3385 Inst.addOperand(MCOperand::CreateImm(imm)); 3386 break; 3387 case 1: 3388 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3389 break; 3390 case 2: 3391 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3392 break; 3393 case 3: 3394 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3395 (imm << 8) | imm)); 3396 break; 3397 } 3398 } else { 3399 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3400 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3401 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3402 Inst.addOperand(MCOperand::CreateImm(imm)); 3403 } 3404 3405 return MCDisassembler::Success; 3406 } 3407 3408 static DecodeStatus 3409 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3410 uint64_t Address, const void *Decoder){ 3411 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<8>(Val<<1) + 4, 3412 true, 2, Inst, Decoder)) 3413 Inst.addOperand(MCOperand::CreateImm(SignExtend32<8>(Val << 1))); 3414 return MCDisassembler::Success; 3415 } 3416 3417 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3418 uint64_t Address, const void *Decoder){ 3419 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 3420 true, 4, Inst, Decoder)) 3421 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3422 return MCDisassembler::Success; 3423 } 3424 3425 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3426 uint64_t Address, const void *Decoder) { 3427 switch (Val) { 3428 default: 3429 return MCDisassembler::Fail; 3430 case 0xF: // SY 3431 case 0xE: // ST 3432 case 0xB: // ISH 3433 case 0xA: // ISHST 3434 case 0x7: // NSH 3435 case 0x6: // NSHST 3436 case 0x3: // OSH 3437 case 0x2: // OSHST 3438 break; 3439 } 3440 3441 Inst.addOperand(MCOperand::CreateImm(Val)); 3442 return MCDisassembler::Success; 3443 } 3444 3445 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3446 uint64_t Address, const void *Decoder) { 3447 if (!Val) return MCDisassembler::Fail; 3448 Inst.addOperand(MCOperand::CreateImm(Val)); 3449 return MCDisassembler::Success; 3450 } 3451 3452 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3453 uint64_t Address, const void *Decoder) { 3454 DecodeStatus S = MCDisassembler::Success; 3455 3456 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3457 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3458 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3459 3460 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3461 3462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3463 return MCDisassembler::Fail; 3464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3465 return MCDisassembler::Fail; 3466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3467 return MCDisassembler::Fail; 3468 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3469 return MCDisassembler::Fail; 3470 3471 return S; 3472 } 3473 3474 3475 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3476 uint64_t Address, const void *Decoder){ 3477 DecodeStatus S = MCDisassembler::Success; 3478 3479 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3480 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3481 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3482 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3483 3484 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3485 return MCDisassembler::Fail; 3486 3487 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3488 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3489 3490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3491 return MCDisassembler::Fail; 3492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3493 return MCDisassembler::Fail; 3494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3495 return MCDisassembler::Fail; 3496 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3497 return MCDisassembler::Fail; 3498 3499 return S; 3500 } 3501 3502 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3503 uint64_t Address, const void *Decoder) { 3504 DecodeStatus S = MCDisassembler::Success; 3505 3506 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3507 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3508 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3509 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3510 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3511 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3512 3513 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3514 3515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3516 return MCDisassembler::Fail; 3517 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3518 return MCDisassembler::Fail; 3519 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3520 return MCDisassembler::Fail; 3521 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3522 return MCDisassembler::Fail; 3523 3524 return S; 3525 } 3526 3527 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3528 uint64_t Address, const void *Decoder) { 3529 DecodeStatus S = MCDisassembler::Success; 3530 3531 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3532 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3533 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3534 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3535 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3536 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3537 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3538 3539 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3540 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3541 3542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3543 return MCDisassembler::Fail; 3544 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3545 return MCDisassembler::Fail; 3546 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3547 return MCDisassembler::Fail; 3548 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3549 return MCDisassembler::Fail; 3550 3551 return S; 3552 } 3553 3554 3555 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3556 uint64_t Address, const void *Decoder) { 3557 DecodeStatus S = MCDisassembler::Success; 3558 3559 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3560 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3561 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3562 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3563 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3564 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3565 3566 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3567 3568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3569 return MCDisassembler::Fail; 3570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3571 return MCDisassembler::Fail; 3572 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3573 return MCDisassembler::Fail; 3574 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3575 return MCDisassembler::Fail; 3576 3577 return S; 3578 } 3579 3580 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3581 uint64_t Address, const void *Decoder) { 3582 DecodeStatus S = MCDisassembler::Success; 3583 3584 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3585 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3586 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3587 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3588 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3589 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3590 3591 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3592 3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3594 return MCDisassembler::Fail; 3595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3596 return MCDisassembler::Fail; 3597 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3598 return MCDisassembler::Fail; 3599 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3600 return MCDisassembler::Fail; 3601 3602 return S; 3603 } 3604 3605 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3606 uint64_t Address, const void *Decoder) { 3607 DecodeStatus S = MCDisassembler::Success; 3608 3609 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3610 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3611 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3612 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3613 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3614 3615 unsigned align = 0; 3616 unsigned index = 0; 3617 switch (size) { 3618 default: 3619 return MCDisassembler::Fail; 3620 case 0: 3621 if (fieldFromInstruction32(Insn, 4, 1)) 3622 return MCDisassembler::Fail; // UNDEFINED 3623 index = fieldFromInstruction32(Insn, 5, 3); 3624 break; 3625 case 1: 3626 if (fieldFromInstruction32(Insn, 5, 1)) 3627 return MCDisassembler::Fail; // UNDEFINED 3628 index = fieldFromInstruction32(Insn, 6, 2); 3629 if (fieldFromInstruction32(Insn, 4, 1)) 3630 align = 2; 3631 break; 3632 case 2: 3633 if (fieldFromInstruction32(Insn, 6, 1)) 3634 return MCDisassembler::Fail; // UNDEFINED 3635 index = fieldFromInstruction32(Insn, 7, 1); 3636 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3637 align = 4; 3638 } 3639 3640 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3641 return MCDisassembler::Fail; 3642 if (Rm != 0xF) { // Writeback 3643 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3644 return MCDisassembler::Fail; 3645 } 3646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3647 return MCDisassembler::Fail; 3648 Inst.addOperand(MCOperand::CreateImm(align)); 3649 if (Rm != 0xF) { 3650 if (Rm != 0xD) { 3651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3652 return MCDisassembler::Fail; 3653 } else 3654 Inst.addOperand(MCOperand::CreateReg(0)); 3655 } 3656 3657 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3658 return MCDisassembler::Fail; 3659 Inst.addOperand(MCOperand::CreateImm(index)); 3660 3661 return S; 3662 } 3663 3664 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3665 uint64_t Address, const void *Decoder) { 3666 DecodeStatus S = MCDisassembler::Success; 3667 3668 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3669 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3670 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3671 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3672 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3673 3674 unsigned align = 0; 3675 unsigned index = 0; 3676 switch (size) { 3677 default: 3678 return MCDisassembler::Fail; 3679 case 0: 3680 if (fieldFromInstruction32(Insn, 4, 1)) 3681 return MCDisassembler::Fail; // UNDEFINED 3682 index = fieldFromInstruction32(Insn, 5, 3); 3683 break; 3684 case 1: 3685 if (fieldFromInstruction32(Insn, 5, 1)) 3686 return MCDisassembler::Fail; // UNDEFINED 3687 index = fieldFromInstruction32(Insn, 6, 2); 3688 if (fieldFromInstruction32(Insn, 4, 1)) 3689 align = 2; 3690 break; 3691 case 2: 3692 if (fieldFromInstruction32(Insn, 6, 1)) 3693 return MCDisassembler::Fail; // UNDEFINED 3694 index = fieldFromInstruction32(Insn, 7, 1); 3695 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3696 align = 4; 3697 } 3698 3699 if (Rm != 0xF) { // Writeback 3700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3701 return MCDisassembler::Fail; 3702 } 3703 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3704 return MCDisassembler::Fail; 3705 Inst.addOperand(MCOperand::CreateImm(align)); 3706 if (Rm != 0xF) { 3707 if (Rm != 0xD) { 3708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3709 return MCDisassembler::Fail; 3710 } else 3711 Inst.addOperand(MCOperand::CreateReg(0)); 3712 } 3713 3714 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3715 return MCDisassembler::Fail; 3716 Inst.addOperand(MCOperand::CreateImm(index)); 3717 3718 return S; 3719 } 3720 3721 3722 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3723 uint64_t Address, const void *Decoder) { 3724 DecodeStatus S = MCDisassembler::Success; 3725 3726 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3727 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3728 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3729 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3730 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3731 3732 unsigned align = 0; 3733 unsigned index = 0; 3734 unsigned inc = 1; 3735 switch (size) { 3736 default: 3737 return MCDisassembler::Fail; 3738 case 0: 3739 index = fieldFromInstruction32(Insn, 5, 3); 3740 if (fieldFromInstruction32(Insn, 4, 1)) 3741 align = 2; 3742 break; 3743 case 1: 3744 index = fieldFromInstruction32(Insn, 6, 2); 3745 if (fieldFromInstruction32(Insn, 4, 1)) 3746 align = 4; 3747 if (fieldFromInstruction32(Insn, 5, 1)) 3748 inc = 2; 3749 break; 3750 case 2: 3751 if (fieldFromInstruction32(Insn, 5, 1)) 3752 return MCDisassembler::Fail; // UNDEFINED 3753 index = fieldFromInstruction32(Insn, 7, 1); 3754 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3755 align = 8; 3756 if (fieldFromInstruction32(Insn, 6, 1)) 3757 inc = 2; 3758 break; 3759 } 3760 3761 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3762 return MCDisassembler::Fail; 3763 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3764 return MCDisassembler::Fail; 3765 if (Rm != 0xF) { // Writeback 3766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3767 return MCDisassembler::Fail; 3768 } 3769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3770 return MCDisassembler::Fail; 3771 Inst.addOperand(MCOperand::CreateImm(align)); 3772 if (Rm != 0xF) { 3773 if (Rm != 0xD) { 3774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3775 return MCDisassembler::Fail; 3776 } else 3777 Inst.addOperand(MCOperand::CreateReg(0)); 3778 } 3779 3780 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3781 return MCDisassembler::Fail; 3782 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3783 return MCDisassembler::Fail; 3784 Inst.addOperand(MCOperand::CreateImm(index)); 3785 3786 return S; 3787 } 3788 3789 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3790 uint64_t Address, const void *Decoder) { 3791 DecodeStatus S = MCDisassembler::Success; 3792 3793 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3794 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3795 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3796 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3797 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3798 3799 unsigned align = 0; 3800 unsigned index = 0; 3801 unsigned inc = 1; 3802 switch (size) { 3803 default: 3804 return MCDisassembler::Fail; 3805 case 0: 3806 index = fieldFromInstruction32(Insn, 5, 3); 3807 if (fieldFromInstruction32(Insn, 4, 1)) 3808 align = 2; 3809 break; 3810 case 1: 3811 index = fieldFromInstruction32(Insn, 6, 2); 3812 if (fieldFromInstruction32(Insn, 4, 1)) 3813 align = 4; 3814 if (fieldFromInstruction32(Insn, 5, 1)) 3815 inc = 2; 3816 break; 3817 case 2: 3818 if (fieldFromInstruction32(Insn, 5, 1)) 3819 return MCDisassembler::Fail; // UNDEFINED 3820 index = fieldFromInstruction32(Insn, 7, 1); 3821 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3822 align = 8; 3823 if (fieldFromInstruction32(Insn, 6, 1)) 3824 inc = 2; 3825 break; 3826 } 3827 3828 if (Rm != 0xF) { // Writeback 3829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3830 return MCDisassembler::Fail; 3831 } 3832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3833 return MCDisassembler::Fail; 3834 Inst.addOperand(MCOperand::CreateImm(align)); 3835 if (Rm != 0xF) { 3836 if (Rm != 0xD) { 3837 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3838 return MCDisassembler::Fail; 3839 } else 3840 Inst.addOperand(MCOperand::CreateReg(0)); 3841 } 3842 3843 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3844 return MCDisassembler::Fail; 3845 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3846 return MCDisassembler::Fail; 3847 Inst.addOperand(MCOperand::CreateImm(index)); 3848 3849 return S; 3850 } 3851 3852 3853 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3854 uint64_t Address, const void *Decoder) { 3855 DecodeStatus S = MCDisassembler::Success; 3856 3857 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3858 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3859 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3860 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3861 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3862 3863 unsigned align = 0; 3864 unsigned index = 0; 3865 unsigned inc = 1; 3866 switch (size) { 3867 default: 3868 return MCDisassembler::Fail; 3869 case 0: 3870 if (fieldFromInstruction32(Insn, 4, 1)) 3871 return MCDisassembler::Fail; // UNDEFINED 3872 index = fieldFromInstruction32(Insn, 5, 3); 3873 break; 3874 case 1: 3875 if (fieldFromInstruction32(Insn, 4, 1)) 3876 return MCDisassembler::Fail; // UNDEFINED 3877 index = fieldFromInstruction32(Insn, 6, 2); 3878 if (fieldFromInstruction32(Insn, 5, 1)) 3879 inc = 2; 3880 break; 3881 case 2: 3882 if (fieldFromInstruction32(Insn, 4, 2)) 3883 return MCDisassembler::Fail; // UNDEFINED 3884 index = fieldFromInstruction32(Insn, 7, 1); 3885 if (fieldFromInstruction32(Insn, 6, 1)) 3886 inc = 2; 3887 break; 3888 } 3889 3890 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3891 return MCDisassembler::Fail; 3892 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3893 return MCDisassembler::Fail; 3894 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3895 return MCDisassembler::Fail; 3896 3897 if (Rm != 0xF) { // Writeback 3898 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3899 return MCDisassembler::Fail; 3900 } 3901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3902 return MCDisassembler::Fail; 3903 Inst.addOperand(MCOperand::CreateImm(align)); 3904 if (Rm != 0xF) { 3905 if (Rm != 0xD) { 3906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3907 return MCDisassembler::Fail; 3908 } else 3909 Inst.addOperand(MCOperand::CreateReg(0)); 3910 } 3911 3912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3913 return MCDisassembler::Fail; 3914 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3915 return MCDisassembler::Fail; 3916 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3917 return MCDisassembler::Fail; 3918 Inst.addOperand(MCOperand::CreateImm(index)); 3919 3920 return S; 3921 } 3922 3923 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 3924 uint64_t Address, const void *Decoder) { 3925 DecodeStatus S = MCDisassembler::Success; 3926 3927 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3928 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3929 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3930 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3931 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3932 3933 unsigned align = 0; 3934 unsigned index = 0; 3935 unsigned inc = 1; 3936 switch (size) { 3937 default: 3938 return MCDisassembler::Fail; 3939 case 0: 3940 if (fieldFromInstruction32(Insn, 4, 1)) 3941 return MCDisassembler::Fail; // UNDEFINED 3942 index = fieldFromInstruction32(Insn, 5, 3); 3943 break; 3944 case 1: 3945 if (fieldFromInstruction32(Insn, 4, 1)) 3946 return MCDisassembler::Fail; // UNDEFINED 3947 index = fieldFromInstruction32(Insn, 6, 2); 3948 if (fieldFromInstruction32(Insn, 5, 1)) 3949 inc = 2; 3950 break; 3951 case 2: 3952 if (fieldFromInstruction32(Insn, 4, 2)) 3953 return MCDisassembler::Fail; // UNDEFINED 3954 index = fieldFromInstruction32(Insn, 7, 1); 3955 if (fieldFromInstruction32(Insn, 6, 1)) 3956 inc = 2; 3957 break; 3958 } 3959 3960 if (Rm != 0xF) { // Writeback 3961 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3962 return MCDisassembler::Fail; 3963 } 3964 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3965 return MCDisassembler::Fail; 3966 Inst.addOperand(MCOperand::CreateImm(align)); 3967 if (Rm != 0xF) { 3968 if (Rm != 0xD) { 3969 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3970 return MCDisassembler::Fail; 3971 } else 3972 Inst.addOperand(MCOperand::CreateReg(0)); 3973 } 3974 3975 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3976 return MCDisassembler::Fail; 3977 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3978 return MCDisassembler::Fail; 3979 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3980 return MCDisassembler::Fail; 3981 Inst.addOperand(MCOperand::CreateImm(index)); 3982 3983 return S; 3984 } 3985 3986 3987 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 3988 uint64_t Address, const void *Decoder) { 3989 DecodeStatus S = MCDisassembler::Success; 3990 3991 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3992 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3993 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3994 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3995 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3996 3997 unsigned align = 0; 3998 unsigned index = 0; 3999 unsigned inc = 1; 4000 switch (size) { 4001 default: 4002 return MCDisassembler::Fail; 4003 case 0: 4004 if (fieldFromInstruction32(Insn, 4, 1)) 4005 align = 4; 4006 index = fieldFromInstruction32(Insn, 5, 3); 4007 break; 4008 case 1: 4009 if (fieldFromInstruction32(Insn, 4, 1)) 4010 align = 8; 4011 index = fieldFromInstruction32(Insn, 6, 2); 4012 if (fieldFromInstruction32(Insn, 5, 1)) 4013 inc = 2; 4014 break; 4015 case 2: 4016 if (fieldFromInstruction32(Insn, 4, 2)) 4017 align = 4 << fieldFromInstruction32(Insn, 4, 2); 4018 index = fieldFromInstruction32(Insn, 7, 1); 4019 if (fieldFromInstruction32(Insn, 6, 1)) 4020 inc = 2; 4021 break; 4022 } 4023 4024 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4025 return MCDisassembler::Fail; 4026 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4027 return MCDisassembler::Fail; 4028 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4029 return MCDisassembler::Fail; 4030 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4031 return MCDisassembler::Fail; 4032 4033 if (Rm != 0xF) { // Writeback 4034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4035 return MCDisassembler::Fail; 4036 } 4037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4038 return MCDisassembler::Fail; 4039 Inst.addOperand(MCOperand::CreateImm(align)); 4040 if (Rm != 0xF) { 4041 if (Rm != 0xD) { 4042 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4043 return MCDisassembler::Fail; 4044 } else 4045 Inst.addOperand(MCOperand::CreateReg(0)); 4046 } 4047 4048 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4049 return MCDisassembler::Fail; 4050 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4051 return MCDisassembler::Fail; 4052 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4053 return MCDisassembler::Fail; 4054 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4055 return MCDisassembler::Fail; 4056 Inst.addOperand(MCOperand::CreateImm(index)); 4057 4058 return S; 4059 } 4060 4061 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4062 uint64_t Address, const void *Decoder) { 4063 DecodeStatus S = MCDisassembler::Success; 4064 4065 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4066 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4067 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 4068 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 4069 unsigned size = fieldFromInstruction32(Insn, 10, 2); 4070 4071 unsigned align = 0; 4072 unsigned index = 0; 4073 unsigned inc = 1; 4074 switch (size) { 4075 default: 4076 return MCDisassembler::Fail; 4077 case 0: 4078 if (fieldFromInstruction32(Insn, 4, 1)) 4079 align = 4; 4080 index = fieldFromInstruction32(Insn, 5, 3); 4081 break; 4082 case 1: 4083 if (fieldFromInstruction32(Insn, 4, 1)) 4084 align = 8; 4085 index = fieldFromInstruction32(Insn, 6, 2); 4086 if (fieldFromInstruction32(Insn, 5, 1)) 4087 inc = 2; 4088 break; 4089 case 2: 4090 if (fieldFromInstruction32(Insn, 4, 2)) 4091 align = 4 << fieldFromInstruction32(Insn, 4, 2); 4092 index = fieldFromInstruction32(Insn, 7, 1); 4093 if (fieldFromInstruction32(Insn, 6, 1)) 4094 inc = 2; 4095 break; 4096 } 4097 4098 if (Rm != 0xF) { // Writeback 4099 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4100 return MCDisassembler::Fail; 4101 } 4102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4103 return MCDisassembler::Fail; 4104 Inst.addOperand(MCOperand::CreateImm(align)); 4105 if (Rm != 0xF) { 4106 if (Rm != 0xD) { 4107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4108 return MCDisassembler::Fail; 4109 } else 4110 Inst.addOperand(MCOperand::CreateReg(0)); 4111 } 4112 4113 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4114 return MCDisassembler::Fail; 4115 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4116 return MCDisassembler::Fail; 4117 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4118 return MCDisassembler::Fail; 4119 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4120 return MCDisassembler::Fail; 4121 Inst.addOperand(MCOperand::CreateImm(index)); 4122 4123 return S; 4124 } 4125 4126 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4127 uint64_t Address, const void *Decoder) { 4128 DecodeStatus S = MCDisassembler::Success; 4129 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4130 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4131 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4132 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4133 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4134 4135 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4136 S = MCDisassembler::SoftFail; 4137 4138 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4139 return MCDisassembler::Fail; 4140 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4141 return MCDisassembler::Fail; 4142 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4143 return MCDisassembler::Fail; 4144 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4145 return MCDisassembler::Fail; 4146 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4147 return MCDisassembler::Fail; 4148 4149 return S; 4150 } 4151 4152 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4153 uint64_t Address, const void *Decoder) { 4154 DecodeStatus S = MCDisassembler::Success; 4155 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4156 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4157 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4158 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4159 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4160 4161 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4162 S = MCDisassembler::SoftFail; 4163 4164 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4165 return MCDisassembler::Fail; 4166 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4167 return MCDisassembler::Fail; 4168 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4169 return MCDisassembler::Fail; 4170 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4171 return MCDisassembler::Fail; 4172 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4173 return MCDisassembler::Fail; 4174 4175 return S; 4176 } 4177 4178 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4179 uint64_t Address, const void *Decoder) { 4180 DecodeStatus S = MCDisassembler::Success; 4181 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 4182 // The InstPrinter needs to have the low bit of the predicate in 4183 // the mask operand to be able to print it properly. 4184 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 4185 4186 if (pred == 0xF) { 4187 pred = 0xE; 4188 S = MCDisassembler::SoftFail; 4189 } 4190 4191 if ((mask & 0xF) == 0) { 4192 // Preserve the high bit of the mask, which is the low bit of 4193 // the predicate. 4194 mask &= 0x10; 4195 mask |= 0x8; 4196 S = MCDisassembler::SoftFail; 4197 } 4198 4199 Inst.addOperand(MCOperand::CreateImm(pred)); 4200 Inst.addOperand(MCOperand::CreateImm(mask)); 4201 return S; 4202 } 4203 4204 static DecodeStatus 4205 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4206 uint64_t Address, const void *Decoder) { 4207 DecodeStatus S = MCDisassembler::Success; 4208 4209 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4210 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4211 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4212 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4213 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4214 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4215 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4216 bool writeback = (W == 1) | (P == 0); 4217 4218 addr |= (U << 8) | (Rn << 9); 4219 4220 if (writeback && (Rn == Rt || Rn == Rt2)) 4221 Check(S, MCDisassembler::SoftFail); 4222 if (Rt == Rt2) 4223 Check(S, MCDisassembler::SoftFail); 4224 4225 // Rt 4226 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4227 return MCDisassembler::Fail; 4228 // Rt2 4229 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4230 return MCDisassembler::Fail; 4231 // Writeback operand 4232 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4233 return MCDisassembler::Fail; 4234 // addr 4235 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4236 return MCDisassembler::Fail; 4237 4238 return S; 4239 } 4240 4241 static DecodeStatus 4242 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4243 uint64_t Address, const void *Decoder) { 4244 DecodeStatus S = MCDisassembler::Success; 4245 4246 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4247 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4248 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4249 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4250 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4251 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4252 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4253 bool writeback = (W == 1) | (P == 0); 4254 4255 addr |= (U << 8) | (Rn << 9); 4256 4257 if (writeback && (Rn == Rt || Rn == Rt2)) 4258 Check(S, MCDisassembler::SoftFail); 4259 4260 // Writeback operand 4261 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4262 return MCDisassembler::Fail; 4263 // Rt 4264 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4265 return MCDisassembler::Fail; 4266 // Rt2 4267 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4268 return MCDisassembler::Fail; 4269 // addr 4270 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4271 return MCDisassembler::Fail; 4272 4273 return S; 4274 } 4275 4276 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4277 uint64_t Address, const void *Decoder) { 4278 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4279 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4280 if (sign1 != sign2) return MCDisassembler::Fail; 4281 4282 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4283 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4284 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4285 Val |= sign1 << 12; 4286 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4287 4288 return MCDisassembler::Success; 4289 } 4290 4291 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4292 uint64_t Address, 4293 const void *Decoder) { 4294 DecodeStatus S = MCDisassembler::Success; 4295 4296 // Shift of "asr #32" is not allowed in Thumb2 mode. 4297 if (Val == 0x20) S = MCDisassembler::SoftFail; 4298 Inst.addOperand(MCOperand::CreateImm(Val)); 4299 return S; 4300 } 4301 4302 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4303 uint64_t Address, const void *Decoder) { 4304 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4305 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4306 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4307 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4308 4309 if (pred == 0xF) 4310 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4311 4312 DecodeStatus S = MCDisassembler::Success; 4313 4314 if (Rt == Rn || Rn == Rt2) 4315 S = MCDisassembler::SoftFail; 4316 4317 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4318 return MCDisassembler::Fail; 4319 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4320 return MCDisassembler::Fail; 4321 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4322 return MCDisassembler::Fail; 4323 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4324 return MCDisassembler::Fail; 4325 4326 return S; 4327 } 4328 4329 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4330 uint64_t Address, const void *Decoder) { 4331 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4332 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4333 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4334 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4335 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4336 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4337 4338 DecodeStatus S = MCDisassembler::Success; 4339 4340 // VMOVv2f32 is ambiguous with these decodings. 4341 if (!(imm & 0x38) && cmode == 0xF) { 4342 Inst.setOpcode(ARM::VMOVv2f32); 4343 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4344 } 4345 4346 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4347 4348 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4349 return MCDisassembler::Fail; 4350 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4351 return MCDisassembler::Fail; 4352 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4353 4354 return S; 4355 } 4356 4357 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4358 uint64_t Address, const void *Decoder) { 4359 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4360 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4361 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4362 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4363 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4364 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4365 4366 DecodeStatus S = MCDisassembler::Success; 4367 4368 // VMOVv4f32 is ambiguous with these decodings. 4369 if (!(imm & 0x38) && cmode == 0xF) { 4370 Inst.setOpcode(ARM::VMOVv4f32); 4371 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4372 } 4373 4374 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4375 4376 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4377 return MCDisassembler::Fail; 4378 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4379 return MCDisassembler::Fail; 4380 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4381 4382 return S; 4383 } 4384 4385 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4386 uint64_t Address, const void *Decoder) { 4387 DecodeStatus S = MCDisassembler::Success; 4388 4389 unsigned Rn = fieldFromInstruction32(Val, 16, 4); 4390 unsigned Rt = fieldFromInstruction32(Val, 12, 4); 4391 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 4392 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4); 4393 unsigned Cond = fieldFromInstruction32(Val, 28, 4); 4394 4395 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt) 4396 S = MCDisassembler::SoftFail; 4397 4398 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4399 return MCDisassembler::Fail; 4400 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4401 return MCDisassembler::Fail; 4402 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4403 return MCDisassembler::Fail; 4404 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4405 return MCDisassembler::Fail; 4406 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4407 return MCDisassembler::Fail; 4408 4409 return S; 4410 } 4411 4412 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4413 uint64_t Address, const void *Decoder) { 4414 4415 DecodeStatus S = MCDisassembler::Success; 4416 4417 unsigned CRm = fieldFromInstruction32(Val, 0, 4); 4418 unsigned opc1 = fieldFromInstruction32(Val, 4, 4); 4419 unsigned cop = fieldFromInstruction32(Val, 8, 4); 4420 unsigned Rt = fieldFromInstruction32(Val, 12, 4); 4421 unsigned Rt2 = fieldFromInstruction32(Val, 16, 4); 4422 4423 if ((cop & ~0x1) == 0xa) 4424 return MCDisassembler::Fail; 4425 4426 if (Rt == Rt2) 4427 S = MCDisassembler::SoftFail; 4428 4429 Inst.addOperand(MCOperand::CreateImm(cop)); 4430 Inst.addOperand(MCOperand::CreateImm(opc1)); 4431 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4432 return MCDisassembler::Fail; 4433 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4434 return MCDisassembler::Fail; 4435 Inst.addOperand(MCOperand::CreateImm(CRm)); 4436 4437 return S; 4438 } 4439 4440
