/system/core/libpixelflinger/codeflinger/ |
ARMAssembler.cpp | 224 int Rd, int Rm, int Rs, int Rn) { 225 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; } 226 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn); 228 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm; 231 int Rd, int Rm, int Rs) { 232 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; } [all...] |
ARMAssemblerInterface.h | 74 static uint32_t reg_imm(int Rm, int type, uint32_t shift); 75 static uint32_t reg_rrx(int Rm); 76 static uint32_t reg_reg(int Rm, int type, int Rs); 80 // (immediate and Rm can be negative, which indicates U=0) 83 static uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0); 84 static uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0); 87 // (immediate and Rm can be negative, which indicates U=0) 90 static uint32_t reg_pre(int Rm, int W=0); 91 static uint32_t reg_post(int Rm); 120 int Rd, int Rm, int Rs, int Rn) = 0 [all...] |
ARMAssembler.h | 64 int Rd, int Rm, int Rs, int Rn); 66 int Rd, int Rm, int Rs); 68 int RdLo, int RdHi, int Rm, int Rs); 70 int RdLo, int RdHi, int Rm, int Rs); 72 int RdLo, int RdHi, int Rm, int Rs); 74 int RdLo, int RdHi, int Rm, int Rs); 106 virtual void SWP(int cc, int Rn, int Rd, int Rm); 107 virtual void SWPB(int cc, int Rn, int Rd, int Rm); 111 virtual void CLZ(int cc, int Rd, int Rm); 112 virtual void QADD(int cc, int Rd, int Rm, int Rn) [all...] |
ARMAssemblerProxy.h | 54 int Rd, int Rm, int Rs, int Rn); 56 int Rd, int Rm, int Rs); 58 int RdLo, int RdHi, int Rm, int Rs); 60 int RdLo, int RdHi, int Rm, int Rs); 62 int RdLo, int RdHi, int Rm, int Rs); 64 int RdLo, int RdHi, int Rm, int Rs); 96 virtual void SWP(int cc, int Rn, int Rd, int Rm); 97 virtual void SWPB(int cc, int Rn, int Rd, int Rm); 101 virtual void CLZ(int cc, int Rd, int Rm); 102 virtual void QADD(int cc, int Rd, int Rm, int Rn) [all...] |
ARMAssemblerProxy.cpp | 75 void ARMAssemblerProxy::MLA(int cc, int s, int Rd, int Rm, int Rs, int Rn) { 76 mTarget->MLA(cc, s, Rd, Rm, Rs, Rn); 78 void ARMAssemblerProxy::MUL(int cc, int s, int Rd, int Rm, int Rs) { 79 mTarget->MUL(cc, s, Rd, Rm, Rs); 82 int RdLo, int RdHi, int Rm, int Rs) { 83 mTarget->UMULL(cc, s, RdLo, RdHi, Rm, Rs); 86 int RdLo, int RdHi, int Rm, int Rs) { 87 mTarget->UMUAL(cc, s, RdLo, RdHi, Rm, Rs); 90 int RdLo, int RdHi, int Rm, int Rs) { 91 mTarget->SMULL(cc, s, RdLo, RdHi, Rm, Rs); [all...] |
ARMAssemblerInterface.cpp | 88 uint32_t ARMAssemblerInterface::reg_imm(int Rm, int type, uint32_t shift) 90 return ((shift&0x1F)<<7) | ((type&0x3)<<5) | (Rm&0xF); 93 uint32_t ARMAssemblerInterface::reg_rrx(int Rm) 95 return (ROR<<5) | (Rm&0xF); 98 uint32_t ARMAssemblerInterface::reg_reg(int Rm, int type, int Rs) 100 return ((Rs&0xF)<<8) | ((type&0x3)<<5) | (1<<4) | (Rm&0xF); 104 // LDR(B)/STR(B)/PLD (immediate and Rm can be negative, which indicate U=0) 123 uint32_t ARMAssemblerInterface::reg_scale_pre(int Rm, int type, 127 (((uint32_t(Rm)>>31)^1)<<23) | ((W&1)<<21) | 128 reg_imm(abs(Rm), type, shift) [all...] |
/cts/libs/vogar-expect/src/vogar/commands/ |
Rm.java | 22 * A rm command. 24 public final class Rm { 27 new Command("rm", "-f", file.getPath()).execute(); 31 new Command("rm", "-rf", directory.getPath()).execute();
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/external/llvm/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | [all...] |
/external/qemu/ |
trace.c | 894 int Rm = (insn & 15); 905 result += 2 + _interlock_use(Rm) + _interlock_use(Rs); 909 int Rm = (insn & 15); 920 result += 3 + _interlock_use(Rm) + _interlock_use(Rs); 924 int Rm = (insn & 15); 927 result = 2 + _interlock_use(Rm); 932 int Rm = (insn & 15); 936 result += _interlock_use(Rn) + _interlock_use(Rm); 955 int Rm = (insn & 15); 959 result += _interlock_use(Rn) + _interlock_use(Rm); [all...] |
i386-dis.c | 349 #define Rm { OP_R, m_mode } 1581 int rm; member in struct:__anon11218 [all...] |
arm-dis.c | 2070 const char *rm = arm_regnames [given & 0xf]; local 2285 int rm = ((given >> 0) & 0xf); local 2315 int rm = ((given >> 0) & 0xf); local 2390 int rm = ((given >> 0) & 0xf); local [all...] |
/external/qemu/distrib/sdl-1.2.12/src/video/ |
SDL_pixels.c | 143 int Rm=0,Gm=0,Bm=0; 152 Rm|=1<<i; 155 fprintf(stderr,"Rw=%d Rm=0x%02X\n",Rw,Rm); 189 r=(r<<format->Rloss)|((r*Rm)>>Rw);
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | 696 // [Rn, Rm] 697 // {5-3} = Rm 702 unsigned Rm = getARMRegisterNumbering(MO2.getReg()); 703 return (Rm << 3) | Rn; [all...] |
/external/v8/src/arm/ |
disasm-arm.cc | 214 int rm = instr->RmValue(); local 216 PrintRegister(rm); 219 // Special case for using rm only. 336 } else if (format[1] == 'm') { // 'rm: Rm register 693 Format(instr, "mul'cond's 'rn, 'rm, 'rs"); 696 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 699 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); 707 // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs> 708 Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs") [all...] |
/external/valgrind/main/none/tests/arm/ |
vfp.stdout.exp | [all...] |
v6intThumb.stdout.exp | 2 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC 3 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C 4 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N 5 cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 6 cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 7 cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V 8 cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 9 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC 10 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C 11 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N [all...] |