| /external/llvm/include/llvm/Analysis/ |
| ConstantsScanner.h | 28 unsigned OpIdx; // Operand index
33 assert(!InstI.atEnd() && OpIdx < InstI->getNumOperands() &&
35 return isa<Constant>(InstI->getOperand(OpIdx));
39 inline constant_iterator(const Function *F) : InstI(inst_begin(F)), OpIdx(0) {
47 : InstI(inst_end(F)), OpIdx(0) {
50 inline bool operator==(const _Self& x) const { return OpIdx == x.OpIdx &&
56 return cast<Constant>(InstI->getOperand(OpIdx));
61 ++OpIdx;
64 while (OpIdx < NumOperands && !isAtConstant())
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
114 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | 103 unsigned OpIdx);
156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
157 return getMachineOpValue(MI, MI.getOperand(OpIdx));
251 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
253 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
293 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
295 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
297 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
299 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
[all...] |
| ARMExpandPseudoInsts.cpp | 385 unsigned OpIdx = 0;
387 bool DstIsDead = MI.getOperand(OpIdx).isDead();
388 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
414 SrcOpIdx = OpIdx++;
417 MIB.addOperand(MI.getOperand(OpIdx++));
418 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ProcessImplicitDefs.h | 34 unsigned OpIdx,
|
| MachineInstr.h | 732 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
733 /// getOperand(OpIdx) does not belong to an inline asm operand group.
736 /// containing OpIdx.
741 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
744 /// operand OpIdx. For normal instructions, this is derived from the
751 getRegClassConstraint(unsigned OpIdx,
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeEmitterGen.cpp | 107 unsigned OpIdx;
108 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
110 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
111 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
118 OpIdx = NumberedOp++;
121 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
132 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
139 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
|
| CodeGenInstruction.cpp | 135 unsigned OpIdx;
136 if (hasOperandNamed(Name, OpIdx)) return OpIdx;
142 /// given name. If so, return true and set OpIdx to the index of the
144 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const {
148 OpIdx = i;
171 unsigned OpIdx = getOperandNamed(OpName);
175 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp &&
181 return std::make_pair(OpIdx, 0U);
185 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo
[all...] |
| CodeGenInstruction.h | 159 /// given name. If so, return true and set OpIdx to the index of the
161 bool hasOperandNamed(StringRef Name, unsigned &OpIdx) const;
|
| /external/llvm/lib/CodeGen/ |
| ProcessImplicitDefs.cpp | 50 unsigned Reg, unsigned OpIdx,
52 switch(OpIdx) {
267 unsigned OpIdx = Ops[j];
268 RMI->RemoveOperand(OpIdx-j);
|
| MachineInstr.cpp | 909 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
912 assert(OpIdx < getNumOperands() && "OpIdx out of range");
915 if (OpIdx < InlineAsm::MIOp_FirstOperand)
927 if (i + NumOps > OpIdx) {
[all...] |
| MachineLICM.cpp | 247 unsigned Reg, unsigned OpIdx,
780 unsigned Reg, unsigned OpIdx,
[all...] |
| RegisterCoalescer.cpp | 694 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
695 NewMI->getOperand(OpIdx).setIsKill();
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 108 unsigned OpIdx, SDep& dep) const;
|
| ScheduleDAGSDNodes.cpp | 587 unsigned OpIdx, SDep& dep) const{
595 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
598 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
599 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
|
| LegalizeVectorTypes.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeMCCodeEmitter.cpp | 51 unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const {
52 return getMachineOpValue(MI, MI.getOperand(OpIdx));
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
