/external/clang/test/SemaTemplate/ |
nested-name-spec-template.cpp | 5 template<typename T> struct Promote; 7 template<> struct Promote<short> { 11 template<> struct Promote<int> { 15 template<> struct Promote<float> { 19 Promote<short>::type *ret_intptr(int* ip) { return ip; } 20 Promote<int>::type *ret_intptr2(int* ip) { return ip; } 23 M::Promote<int>::type *ret_intptr3(int* ip) { return ip; } 24 M::template Promote<int>::type *ret_intptr4(int* ip) { return ip; } // expected-warning{{'template' keyword outside of a template}} 25 M::template Promote<int> pi; // expected-warning{{'template' keyword outside of a template}} 28 N::M::Promote<int>::type *ret_intptr5(int* ip) { return ip; [all...] |
/external/llvm/examples/OCaml-Kaleidoscope/Chapter7/ |
toy.ml | 33 (* Promote allocas to registers. *)
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/external/llvm/lib/Target/CellSPU/ |
SPUISelLowering.cpp | 112 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 113 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 114 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 301 setOperationAction(ISD::CTLZ , MVT::i8, Promote); 302 setOperationAction(ISD::CTLZ , MVT::i16, Promote); 331 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); 332 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); 333 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); 334 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); 349 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); [all...] |
/external/llvm/include/llvm/Target/ |
TargetLowering.h | 84 Promote, // This operation should be executed in a larger type. 252 /// it is already legal (return 'Legal') or we need to promote it to a larger 253 /// type (return 'Promote'), or we need to expand it into multiple registers 264 /// returns the larger type to promote to. For integer types that are larger 470 assert(Action != Promote && "Can't promote condition code!"); 482 /// getTypeToPromoteTo - If the action for this operation is to promote, this 483 /// method returns the ValueType to promote to. 485 assert(getOperationAction(Op, VT) == Promote && 501 "Didn't find type to promote to!") [all...] |
/external/llvm/lib/Target/MBlaze/ |
MBlazeISelLowering.cpp | 92 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 93 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 94 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 725 // Promote the value if needed. [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | 225 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 243 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 245 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 246 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 247 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 250 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 261 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 263 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 264 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 269 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 468 // Promote the value if needed. [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | 84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 231 // VAARG always uses double-word chunks, so promote anything smaller. 232 setOperationAction(ISD::VAARG, MVT::i1, Promote); 234 setOperationAction(ISD::VAARG, MVT::i8, Promote); 236 setOperationAction(ISD::VAARG, MVT::i16, Promote); 238 setOperationAction(ISD::VAARG, MVT::i32, Promote); 281 // We cannot do this with Promote because i64 is not a legal type. 320 // We promote all shuffles to v16i8. 321 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 324 // We promote all non-typed operations to v4i32 [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 233 case TargetLowering::Promote: 234 // "Promote" the operation by bitcasting 279 "Can't promote a vector with multiple results!");
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LegalizeDAG.cpp | 185 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 727 if (Action != TargetLowering::Promote) [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreISelLowering.cpp | 129 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 130 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | 117 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 118 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 119 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | 415 // Promote the value if needed. 699 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | 95 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 99 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 133 // Promote all bit-wise operations. 135 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote); 138 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote); 141 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote); 579 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); [all...] |