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    Searched refs:SuperReg (Results 1 - 5 of 5) sorted by null

  /external/llvm/lib/Target/Hexagon/
HexagonFrameLowering.cpp 238 const uint16_t* SuperReg = TRI->getSuperRegisters(Reg);
240 // Assume that there is exactly one superreg.
241 assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg");
248 "Expected exactly one superreg");
249 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]);
250 CanUseDblStore = (SuperRegNext[0] == SuperReg[0]);
255 TII.storeRegToStackSlot(MBB, MI, SuperReg[0], true,
257 MBB.addLiveIn(SuperReg[0])
    [all...]
  /external/llvm/lib/CodeGen/
AggressiveAntiDepBreaker.cpp 570 unsigned SuperReg = 0;
573 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
574 SuperReg = Reg;
590 // All group registers should be a subreg of SuperReg.
593 if (Reg == SuperReg) continue;
594 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
607 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
612 // Check each possible rename register for SuperReg in round-robin
621 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other)
    [all...]
CriticalAntiDepBreaker.cpp 297 unsigned SuperReg = *Super;
298 Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);
PostRASchedulerList.cpp 466 const unsigned SuperReg = MO.getReg();
467 for (const uint16_t *Subreg = TRI->getSubRegisters(SuperReg);
  /external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp     [all...]

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