| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 375 MIB.addMBB(TBB);
384 MIB.addMBB(TBB);
389 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
394 MIB.addMBB(TBB);
406 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
407 MIB2.addMBB(FBB);
412 MIB.addMBB(FBB);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 206 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
208 .addMBB(TargetBB);
240 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
254 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
|
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
209 BuildMI(&MBB, DL, get(MBlaze::BRID)).addMBB(FBB);
|
| MBlazeISelLowering.cpp | 306 .addMBB(finish);
311 .addReg(IVAL).addMBB(MBB)
312 .addReg(NDST).addMBB(loop);
317 .addReg(IAMT).addMBB(MBB)
318 .addReg(NAMT).addMBB(loop);
335 .addMBB(loop);
339 .addReg(IVAL).addMBB(MBB)
340 .addReg(NDST).addMBB(loop);
397 .addMBB(dneBB);
403 // .addReg(MI->getOperand(1).getReg()).addMBB(flsBB
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 287 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
292 .addMBB(TBB);
301 .addMBB(TBB);
302 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
|
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 272 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
278 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
283 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
|
| MSP430BranchSelector.cpp | 161 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
|
| MSP430ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.cpp | 282 .addMBB(TBB).addReg(Cond[0].getReg()).addImm(Cond[1].getImm());
284 .addMBB(FBB).addReg(PTX::NoRegister).addImm(PTXPredicate::None);
288 .addMBB(TBB).addReg(Cond[0].getReg()).addImm(Cond[1].getImm());
292 .addMBB(TBB).addReg(PTX::NoRegister).addImm(PTXPredicate::None);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCBranchSelector.cpp | 155 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
|
| PPCInstrInfo.cpp | 307 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
310 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
316 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
317 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
|
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 496 TII->get(Hexagon::LOOP0_r)).addMBB(LoopStart).addReg(CountReg);
502 TII->get(Hexagon::LOOP0_i)).addMBB(LoopStart).addImm(CountImm);
515 BuildMI(*LastMBB, LastI, dl, TII->get(Hexagon::ENDLOOP0)).addMBB(LoopStart);
642 .addMBB(MII->getOperand(0).getMBB());
|
| HexagonInstrInfo.cpp | 159 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
162 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
167 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
168 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 414 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
418 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
424 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
427 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 387 MIB.addMBB(TBB);
409 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
416 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
|
| MipsISelLowering.cpp | 826 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
829 .addReg(Mips::ZERO).addMBB(sinkMBB);
847 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
848 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
852 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
853 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 91 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
|
| /external/llvm/lib/CodeGen/ |
| MachineSSAUpdater.cpp | 192 MIB.addReg(PredValues[i].second).addMBB(PredValues[i].first);
|
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
