| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.cpp | 49 .addReg(DestReg, getDefRegState(true), SubIdx)
|
| ARMBaseInstrInfo.h | 314 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
|
| MLxExpansionPass.cpp | 233 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
|
| ARMLoadStoreOptimizer.cpp | 353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
780 .addReg(Base, getDefRegState(true)) // WB base register
933 .addReg(Base, getDefRegState(true)) // WB base register
936 .addReg(MO.getReg(), (isLd ? getDefRegState(true) :
[all...] |
| Thumb1FrameLowering.cpp | 358 MIB.addReg(Reg, getDefRegState(true));
|
| Thumb1RegisterInfo.cpp | 78 .addReg(DestReg, getDefRegState(true), SubIdx)
|
| ARMBaseRegisterInfo.cpp | 703 .addReg(DestReg, getDefRegState(true), SubIdx)
[all...] |
| ARMFrameLowering.cpp | 685 MIB.addReg(Regs[i], getDefRegState(true));
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 190 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 298 inline unsigned getDefRegState(bool B) {
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
[all...] |
| X86InstrInfo.cpp | [all...] |
