| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 37 Src1Name = getRegName(MI->getOperand(0).getReg());
38 Src2Name = getRegName(MI->getOperand(2).getReg());
39 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
42 DestName = getRegName(MI->getOperand(0).getReg());
43 Src1Name = getRegName(MI->getOperand(1).getReg());
44 Src2Name = getRegName(MI->getOperand(2).getReg());
45 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
49 Src2Name = getRegName(MI->getOperand(2).getReg());
50 Src1Name = getRegName(MI->getOperand(0).getReg());
54 Src2Name = getRegName(MI->getOperand(2).getReg())
[all...] |
| /external/llvm/unittests/Support/ |
| MDBuilderTest.cpp | 37 Value *Op = MD1->getOperand(0);
51 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(0)));
52 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(1)));
53 ConstantInt *C0 = cast<ConstantInt>(R1->getOperand(0));
54 ConstantInt *C1 = cast<ConstantInt>(R1->getOperand(1));
65 EXPECT_EQ(R0->getOperand(0), R0);
66 EXPECT_EQ(R1->getOperand(0), R1);
67 EXPECT_TRUE(R0->getNumOperands() == 1 || R0->getOperand(1) == 0);
68 EXPECT_TRUE(R1->getNumOperands() == 1 || R1->getOperand(1) == 0);
76 EXPECT_TRUE(isa<MDString>(R0->getOperand(0)))
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 101 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
102 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
116 Base = Addr.getOperand(0);
122 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper)
123 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
126 Base = Addr.getOperand(0).getOperand(0);
137 Base = Addr.getOperand(0);
143 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper)
144 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 58 const MCOperand &Dst = MI->getOperand(0);
59 const MCOperand &MO1 = MI->getOperand(1);
60 const MCOperand &MO2 = MI->getOperand(2);
61 const MCOperand &MO3 = MI->getOperand(3);
78 const MCOperand &Dst = MI->getOperand(0);
79 const MCOperand &MO1 = MI->getOperand(1);
80 const MCOperand &MO2 = MI->getOperand(2);
102 MI->getOperand(0).getReg() == ARM::SP &&
114 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
115 MI->getOperand(3).getImm() == -4)
[all...] |
| /external/llvm/lib/CodeGen/ |
| AntiDepBreaker.h | 64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
65 MI->getOperand(0).setReg(NewReg);
|
| /external/llvm/lib/VMCore/ |
| IntrinsicInst.cpp | 37 return CE->getOperand(0);
58 return MD->getOperand(0);
68 return cast<MDNode>(getArgOperand(0))->getOperand(0);
72 return cast<MDNode>(getArgOperand(0))->getOperand(0);
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUAsmPrinter.cpp | 64 const MachineOperand &MO = MI->getOperand(OpNo);
85 unsigned int value = MI->getOperand(OpNo).getImm();
93 char value = MI->getOperand(OpNo).getImm();
103 O << (short) MI->getOperand(OpNo).getImm();
109 O << (unsigned short)MI->getOperand(OpNo).getImm();
117 const MachineOperand &MO = MI->getOperand(OpNo);
125 unsigned int value = MI->getOperand(OpNo).getImm();
133 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
143 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
152 assert(MI->getOperand(OpNo).isImm() &
[all...] |
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 34 unsigned char SH = MI->getOperand(2).getImm();
35 unsigned char MB = MI->getOperand(3).getImm();
36 unsigned char ME = MI->getOperand(4).getImm();
57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
67 unsigned char SH = MI->getOperand(2).getImm();
68 unsigned char ME = MI->getOperand(3).getImm();
90 unsigned Code = MI->getOperand(OpNo).getImm();
114 char Value = MI->getOperand(OpNo).getImm();
121 unsigned char Value = MI->getOperand(OpNo).getImm()
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.h | 71 int value = MI->getOperand(OpNo).getImm();
77 int value = MI->getOperand(OpNo).getImm();
83 const MachineOperand &MO1 = MI->getOperand(OpNo);
84 const MachineOperand &MO2 = MI->getOperand(OpNo+1);
93 const MachineOperand &MO1 = MI->getOperand(OpNo);
94 const MachineOperand &MO2 = MI->getOperand(OpNo+1);
105 if (MI->getOperand(OpNo).isImm()) {
106 O << "$+" << MI->getOperand(OpNo).getImm()*4;
108 printOp(MI->getOperand(OpNo), O);
122 if (MI->getOperand(OpNo).isImm())
[all...] |
| HexagonSplitTFRCondSets.cpp | 87 int DestReg = MI->getOperand(0).getReg();
88 int SrcReg1 = MI->getOperand(2).getReg();
89 int SrcReg2 = MI->getOperand(3).getReg();
95 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
99 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
104 int DestReg = MI->getOperand(0).getReg();
105 int SrcReg1 = MI->getOperand(1).getReg();
106 int Immed1 = MI->getOperand(2).getImm();
107 int Immed2 = MI->getOperand(3).getImm();
|
| HexagonAsmPrinter.cpp | 77 const MachineOperand &MO = MI->getOperand(OpNo);
144 if (!MI->getOperand(OpNo).isReg() ||
146 !MI->getOperand(OpNo+1).isReg())
153 if (MI->getOperand(OpNo).isImm())
170 const MachineOperand &Base = MI->getOperand(OpNo);
171 const MachineOperand &Offset = MI->getOperand(OpNo+1);
219 const MachineOperand &MO1 = MI->getOperand(OpNo);
220 const MachineOperand &MO2 = MI->getOperand(OpNo+1);
230 const MachineOperand &MO = MI->getOperand(OpNo);
243 const MachineOperand &MO = MI->getOperand(OpNo)
[all...] |
| HexagonRegisterInfo.cpp | 143 while (!MI.getOperand(i).isFI()) {
148 int FrameIndex = MI.getOperand(i).getIndex();
168 MI.getOperand(i).ChangeToRegister(getStackRegister(), false, false, true);
169 MI.getOperand(i+1).ChangeToImmediate(FrameSize+Offset);
188 *getSubRegisters(MI.getOperand(0).getReg()) :
189 MI.getOperand(0).getReg();
204 MI.getOperand(i).ChangeToRegister(dstReg, false, false, true);
205 MI.getOperand(i+1).ChangeToImmediate(0);
229 MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
230 MI.getOperand(i+1).ChangeToImmediate(0)
[all...] |
| /external/llvm/lib/Target/Hexagon/InstPrinter/ |
| HexagonInstPrinter.cpp | 59 const MCOperand& MO = MI->getOperand(OpNo);
74 O << MI->getOperand(OpNo).getImm();
79 O << MI->getOperand(OpNo).getImm();
84 O << MI->getOperand(OpNo).getImm();
89 O << -MI->getOperand(OpNo).getImm();
99 const MCOperand& MO0 = MI->getOperand(OpNo);
100 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
108 const MCOperand& MO0 = MI->getOperand(OpNo);
109 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
116 const MCOperand& MO = MI->getOperand(OpNo)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 85 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
88 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
92 Base = Addr.getOperand(0);
98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
99 Base = Addr.getOperand(1);
100 Offset = Addr.getOperand(0).getOperand(0);
103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
104 Base = Addr.getOperand(0);
105 Offset = Addr.getOperand(1).getOperand(0)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineVectorOps.cpp | 38 isa<ConstantInt>(I->getOperand(2)))
44 (CheapToScalarize(BO->getOperand(0), isConstant) ||
45 CheapToScalarize(BO->getOperand(1), isConstant)))
49 (CheapToScalarize(CI->getOperand(0), isConstant) ||
50 CheapToScalarize(CI->getOperand(1), isConstant)))
71 if (!isa<ConstantInt>(III->getOperand(2)))
73 unsigned IIElt = cast<ConstantInt>(III->getOperand(2))->getZExtValue();
78 return III->getOperand(1);
82 return FindScalarElement(III->getOperand(0), EltNo);
86 unsigned LHSWidth = SVI->getOperand(0)->getType()->getVectorNumElements()
[all...] |
| InstCombineSelect.cpp | 32 LHS = ICI->getOperand(0);
33 RHS = ICI->getOperand(1);
36 if (SI->getTrueValue() == ICI->getOperand(0) &&
37 SI->getFalseValue() == ICI->getOperand(1)) {
52 if (SI->getTrueValue() == ICI->getOperand(1) &&
53 SI->getFalseValue() == ICI->getOperand(0)) {
130 if (TI->getOperand(0)->getType() != FI->getOperand(0)->getType())
137 Value *NewSI = Builder->CreateSelect(SI.getCondition(), TI->getOperand(0),
138 FI->getOperand(0), SI.getName()+".v")
[all...] |
| InstCombineCasts.cpp | 43 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) {
48 return I->getOperand(0);
55 return I->getOperand(0);
63 DecomposeSimpleLinearExpr(I->getOperand(0), SubScale, Offset);
112 DecomposeSimpleLinearExpr(AI.getOperand(0), ArraySizeScale, ArrayOffset);
180 Value *LHS = EvaluateInDifferentType(I->getOperand(0), Ty, isSigned);
181 Value *RHS = EvaluateInDifferentType(I->getOperand(1), Ty, isSigned);
191 if (I->getOperand(0)->getType() == Ty)
192 return I->getOperand(0);
196 Res = CastInst::CreateIntegerCast(I->getOperand(0), Ty
[all...] |
| InstCombineAndOrXor.cpp | 135 Value *X = Op->getOperand(0);
259 Value *ShVal = Op->getOperand(0);
349 !isa<ConstantInt>(LHSI->getOperand(1))) return 0;
351 ConstantInt *N = cast<ConstantInt>(LHSI->getOperand(1));
386 return Builder->CreateSub(LHSI->getOperand(0), RHS, "fold");
387 return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold");
505 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1)))
507 X = I->getOperand(0);
517 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1)))
519 X = I->getOperand(0)
[all...] |
| InstCombineShifts.cpp | 23 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType());
24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
92 if (MaskedValueIsZero(I->getOperand(0),
95 return CanEvaluateTruncated(I->getOperand(0), Ty);
112 return CanEvaluateShifted(I->getOperand(0), NumBits, isLeftShift, IC) &&
113 CanEvaluateShifted(I->getOperand(1), NumBits, isLeftShift, IC);
117 CI = dyn_cast<ConstantInt>(I->getOperand(1));
132 if (MaskedValueIsZero(I->getOperand(0)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 73 I->getOperand(0).getReg())
74 .addReg(Mips::V0).addReg(I->getOperand(1).getReg());
94 unsigned DstReg = I->getOperand(0).getReg();
95 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
109 unsigned DstReg = I->getOperand(0).getReg();
110 unsigned SrcReg = I->getOperand(1).getReg();
111 unsigned N = I->getOperand(2).getImm();
|
| /external/llvm/lib/MC/MCDisassembler/ |
| EDOperand.cpp | 142 result = Inst.Inst->getOperand(MCOpIndex).getImm();
146 unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg();
151 int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm();
166 unsigned baseReg = Inst.Inst->getOperand(MCOpIndex).getReg();
167 uint64_t scaleAmount = Inst.Inst->getOperand(MCOpIndex+1).getImm();
168 unsigned indexReg = Inst.Inst->getOperand(MCOpIndex+2).getReg();
169 int64_t displacement = Inst.Inst->getOperand(MCOpIndex+3).getImm();
173 unsigned segmentReg = Inst.Inst->getOperand(MCOpIndex+4).getReg();
213 if (!Inst.Inst->getOperand(MCOpIndex).isImm())
216 result = Inst.Inst->getOperand(MCOpIndex).getImm()
[all...] |
| /external/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm();
|
| /external/llvm/lib/Target/PTX/ |
| PTXMCInstLower.cpp | 27 const MachineOperand &MO = MI->getOperand(i);
|
| /external/llvm/include/llvm/Support/ |
| GetElementPtrTypeIterator.h | 59 return CT->getTypeAtIndex(getOperand());
66 Value *getOperand() const { return *OpIt; }
70 CurTy = CT->getTypeAtIndex(getOperand());
86 return gep_type_iterator::begin(GEP->getOperand(0)->getType(),
93 return gep_type_iterator::begin(GEP.getOperand(0)->getType(),
|
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 36 const MCOperand &Op = MI->getOperand(OpNo);
48 const MCOperand &Op = MI->getOperand(OpNo);
62 const MCOperand &Base = MI->getOperand(OpNo);
63 const MCOperand &Disp = MI->getOperand(OpNo+1);
90 unsigned CC = MI->getOperand(OpNo).getImm();
|
