| /external/llvm/lib/Target/Mips/ |
| MipsMachineFunction.cpp | 47 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
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| MipsISelDAGToDAG.cpp | 125 MachineRegisterInfo &RegInfo = MF.getRegInfo();
144 MF.getRegInfo().addLiveIn(Mips::T9_64);
166 MF.getRegInfo().addLiveIn(Mips::T9);
227 MachineRegisterInfo *MRI = &MF.getRegInfo();
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| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
31 VRM.getRegInfo().getRegAllocationHint(VirtReg);
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| PHIEliminationUtils.cpp | 36 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();
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| VirtRegMap.cpp | 51 MRI = &mf.getRegInfo();
65 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
93 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
213 const MachineRegisterInfo &MRI = MF->getRegInfo();
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| VirtRegMap.h | 85 MachineRegisterInfo &getRegInfo() const { return *MRI; }
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| PHIElimination.cpp | 112 MRI = &MF.getRegInfo();
231 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
232 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
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| CalcSpillWeights.cpp | 90 MachineRegisterInfo &mri = MF.getRegInfo();
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| OptimizePHIs.cpp | 64 MRI = &Fn.getRegInfo();
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| Spiller.cpp | 67 mri = &mf.getRegInfo();
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| MachineInstr.cpp | 110 AddRegOperandToRegInfo(&MF->getRegInfo());
174 AddRegOperandToRegInfo(&MF->getRegInfo());
596 /// getRegInfo - If this instruction is embedded into a MachineFunction,
599 MachineRegisterInfo *MachineInstr::getRegInfo() {
601 return &MBB->getParent()->getRegInfo();
633 MachineRegisterInfo *RegInfo = getRegInfo();
719 MachineRegisterInfo *RegInfo = getRegInfo();
[all...] |
| DeadMachineInstructionElim.cpp | 89 MRI = &MF.getRegInfo();
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| LocalStackSlotAllocation.cpp | 318 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
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| /dalvik/vm/compiler/codegen/ |
| RallocUtil.cpp | 83 static RegisterInfo *getRegInfo(CompilationUnit *cUnit, int reg)
107 RegisterInfo *info1 = getRegInfo(cUnit, reg1);
108 RegisterInfo *info2 = getRegInfo(cUnit, reg2);
126 RegisterInfo *info = getRegInfo(cUnit, reg);
439 RegisterInfo *p = getRegInfo(cUnit, reg);
469 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg);
485 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg);
496 RegisterInfo *infoLo = getRegInfo(cUnit, rl.lowReg);
497 RegisterInfo *infoHi = getRegInfo(cUnit, rl.highReg);
527 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg)
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXMFInfoExtract.cpp | 55 MachineRegisterInfo &MRI = MF.getRegInfo();
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| /external/llvm/lib/Target/CellSPU/ |
| SPUFrameLowering.cpp | 247 MF.getRegInfo().setPhysRegUnused(SPU::R0);
248 MF.getRegInfo().setPhysRegUnused(SPU::R1);
249 MF.getRegInfo().setPhysRegUnused(SPU::R2);
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| /external/llvm/include/llvm/CodeGen/ |
| LiveRangeEdit.h | 109 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
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| MachineFunction.h | 154 /// getRegInfo - Return information about the registers currently in use.
156 MachineRegisterInfo &getRegInfo() { return *RegInfo; }
157 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
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| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 392 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
597 MF.getRegInfo().isLiveIn(Reg))
[all...] |
| Thumb1FrameLowering.cpp | 243 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
316 MF.getRegInfo().isLiveIn(Reg))
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 230 MRI = &MF.getRegInfo();
483 MF->getRegInfo().getRegClass(TripCount->getReg());
484 unsigned CountReg = MF->getRegInfo().createVirtualRegister(RC);
489 CountReg = MF->getRegInfo().createVirtualRegister(RC);
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| /external/llvm/lib/Target/X86/ |
| X86VZeroUpper.cpp | 141 MachineRegisterInfo &MRI = MF.getRegInfo();
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| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 104 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
110 I = MF->getRegInfo().livein_begin(),
111 E = MF->getRegInfo().livein_end(); I != E; ++I) {
117 I = MF->getRegInfo().liveout_begin(),
118 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
730 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
731 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
743 MF.getRegInfo().setPhysRegUnused(LR);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 100 if (MF.getRegInfo().liveout_empty()) {
103 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
130 if (MF.getRegInfo().liveout_empty())
131 MF.getRegInfo().addLiveOut(SP::I0);
157 MachineRegisterInfo &RegInfo = MF.getRegInfo();
186 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
212 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
295 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
324 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 343 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
347 MF.getRegInfo().setPhysRegUnused(XCore::LR);
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