| /external/oprofile/events/mips/vr5432/ |
| events | 12 event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses (no I-cache misses)
13 event:0x9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses (no D-cache misses)
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| /dalvik/vm/ |
| AtomicCache.cpp | 130 pCache->misses++;
175 pCache->misses, pCache->fills,
178 (pCache->fail + pCache->hits + pCache->misses + pCache->fills),
|
| AtomicCache.h | 58 int misses; /* entry was for other keys */ member in struct:AtomicCache
|
| /external/bluetooth/glib/gio/inotify/ |
| inotify-kernel.h | 51 guint32 *misses);
|
| inotify-kernel.c | 324 guint32 *misses)
329 if (misses)
330 *misses = ik_move_misses;
|
| /external/oprofile/events/mips/rm7000/ |
| events | 12 event:0x08 counters:0,1 um:zero minimum:500 name:EXTERNAL_CACHE_MISSES : External Cache Misses
14 event:0x0a counters:0,1 um:zero minimum:500 name:SCACHE_MISSES : Secondary cache misses
15 event:0x0b counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
16 event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses
17 event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
18 event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
19 event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
20 event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
26 event:0x16 counters:0,1 um:zero minimum:500 name:CACHE_MISSES : Cache misses
|
| /frameworks/base/core/java/android/database/sqlite/ |
| SQLiteDebug.java | 133 /** statement cache stats: hits/misses/cachesize */
137 int hits, int misses, int cachesize) {
142 this.cache = hits + "/" + misses + "/" + cachesize;
|
| /external/oprofile/events/mips/rm9000/ |
| events | 13 event:0x0a counters:0,1 um:zero minimum:500 name:L2_CACHE_MISSES : L2 cache misses
14 event:0x0b counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Icache misses
15 event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Dcache misses
16 event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
17 event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
18 event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
19 event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
|
| /external/oprofile/events/mips/r12000/ |
| events | 13 event:0x9 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
14 event:0xa counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_SECONDARY_CACHE_MISSES : Secondary cache misses (instruction)
21 event:0x11 counters:0,1,2,3 um:zero minimum:500 name:PREFETCH_MISSES_IN_DCACHE : Primary data cache misses by prefetch instructions
27 event:0x17 counters:0,1,2,3 um:zero minimum:500 name:TLB_MISSES : TLB misses
29 event:0x19 counters:0,1,2,3 um:zero minimum:500 name:DCACHE_MISSES : Primary data cache misses
30 event:0x1a counters:0,1,2,3 um:zero minimum:500 name:SCACHE_MISSES : Secondary cache misses (data)
|
| /external/icu4c/i18n/ |
| csr2022.cpp | 37 int32_t misses = 0; local
68 misses += 1;
89 quality = (100*hits - 100*misses) / (hits + misses);
|
| /external/oprofile/events/i386/westmere/ |
| unit_masks | 64 0x01 any DTLB load misses
71 0x01 any DTLB misses
74 0x10 stlb_hit DTLB first level misses but second level hit
75 0x20 pde_miss DTLB misses casued by low part of address
116 0x02 miss L1D hardware prefetch misses
119 0x01 i_state L1 writebacks to L2 in I state (misses)
126 0x02 misses L1I instruction fetch misses
130 0x01 demand_i_state L2 data demand loads in I state (misses)
135 0x10 prefetch_i_state L2 data prefetches in the I state (misses)
[all...] |
| events | 15 event:0x08 counters:0,1,2,3 um:dtlb_load_misses minimum:200000 name:DTLB_LOAD_MISSES : DTLB load misses
35 event:0x49 counters:0,1,2,3 um:dtlb_misses minimum:200000 name:DTLB_MISSES : DTLB misses
37 event:0x4e counters:0,1 um:l1d_prefetch minimum:200000 name:L1D_PREFETCH : L1D hardware prefetch misses
|
| /external/oprofile/events/mips/r10000/ |
| events | 23 event:0x09 counters:0 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
25 event:0x0a counters:0 um:zero minimum:500 name:SCACHE_MISSES_INSTRUCTION : Secondary cache misses (instruction)
26 event:0x0a counters:1 um:zero minimum:500 name:SCACHE_MISSES_DATA : Secondary cache misses (data)
|
| /external/oprofile/events/i386/atom/ |
| unit_masks | 15 0x05 dtlb_miss_ld DTLB misses due to load operations
16 0x09 l0_dtlb_miss_ld L0_DTLB misses due to load operations
17 0x06 dtlb_miss_st DTLB misses due to store operations
44 0x02 misses Icache miss
47 0x02 misses ITLB misses
|
| /external/oprofile/events/mips/24K/ |
| events | 16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
66 event:0x30 counters:0 um:zero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill buffers already allocated
89 event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
90 event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
91 event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
92 event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
93 event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misses
|
| /external/oprofile/events/mips/34K/ |
| events | 16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
71 event:0x30 counters:0 um:zero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill buffers already allocated
96 event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
97 event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
98 event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
99 event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
100 event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misses
|
| /external/oprofile/events/mips/25K/ |
| events | 35 event:0x11 counters:0,1 um:zero minimum:500 name:UTLB_MISSES : U-TLB misses
36 event:0x12 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_IFETCH : Raw count of Joint-TLB misses for instruction fetch
37 event:0x13 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_LOADS_STORES : Raw count of Joint-TLB misses for loads/stores
|
| /external/chromium/chrome/browser/safe_browsing/ |
| filter_false_positive_perftest.cc | 211 // false positive rate (misses) against a URL list.
226 int misses = 0; local
265 ++misses;
280 << ", misses: " << misses; local
283 << ", weighted misses: " << weighted_misses;
|
| /external/oprofile/events/x86-64/family11h/ |
| events | 39 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
44 event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hits
45 event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 and L2 DTLB misses
51 event:0x4c counters:0,1,2,3 um:dcachemisslocked minimum:500 name:DCACHE_MISS_LOCKED_INSTRUCTIONS : DCACHE misses by locked instructions
60 event:0x7e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 cache misses
65 event:0x81 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
|
| /external/oprofile/events/x86-64/hammer/ |
| events | 39 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
44 event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hits
45 event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 and L2 DTLB misses
51 event:0x4c counters:0,1,2,3 um:dcachemisslocked minimum:500 name:DCACHE_MISS_LOCKED_INSTRUCTIONS : DCACHE misses by locked instructions
60 event:0x7e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 cache misses
65 event:0x81 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
|
| /external/antlr/antlr-3.4/tool/src/main/java/org/antlr/misc/ |
| Interval.java | 40 public static int misses = 0; field in class:Interval
|
| /external/oprofile/events/mips/1004K/ |
| events | 16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
72 event:0x30 counters:0 um:zero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill buffers already allocated
104 event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
105 event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
106 event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
107 event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
108 event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misses
|
| /external/webkit/Source/WebKit/efl/ewk/ |
| ewk_tiled_backing_store.h | 62 unsigned int misses; /**< number of times it became dirty but not member in struct:_Ewk_Tile_Stats
|
| /external/oprofile/events/i386/nehalem/ |
| unit_masks | 24 0x01 any Counts all load misses that cause a page walk
27 0x20 pde_miss Number of DTLB cache load misses where the low part of the linear to physical address translation was missed
28 0x40 pdp_miss Number of DTLB cache load misses where the high part of the linear to physical address translation was missed
91 0x80 prefetch_miss Counts L2 prefetch misses for both code and data
93 0xAA miss Counts all L2 misses for both code and data
155 0x01 any Counts the number of misses in the STLB which causes a page walk
156 0x02 walk_completed Counts number of misses in the STLB which resulted in a completed page walk
157 0x10 stlb_hit Counts the number of DTLB first level misses that hit in the second level TLB
158 0x20 pde_miss Number of DTLB cache misses where the low part of the linear to physical address translation was missed
159 0x40 pdp_miss Number of DTLB misses where the high part of the linear to physical address translation was misse
[all...] |
| /external/oprofile/events/mips/74K/ |
| events | 47 event:0x1d counters:0,2 um:zero minimum:500 name:L2_CACHE_MISSES : 29-0 L2 Cache Misses
98 event:0x404 counters:1,3 um:zero minimum:500 name:ITLB_MISSES : 4-1 Instruction micro-TLB misses
99 event:0x405 counters:1,3 um:zero minimum:500 name:JTLB_INSN_MISSES : 5-1 Joint TLB instruction misses
100 event:0x406 counters:1,3 um:zero minimum:500 name:ICACHE_MISSES : 6-1 Instruction cache misses, includes misses from fetch-ahead and speculation
118 event:0x418 counters:1,3 um:zero minimum:500 name:DCACHE_MISSES : 24-1 Data cache misses
119 event:0x419 counters:1,3 um:zero minimum:500 name:JTLB_DATA_MISSES : 25-1 Joint TLB data (non-instruction) misses
121 event:0x41b counters:1,3 um:zero minimum:500 name:LOAD_STORE_NO_FILL_REQUESTS : 27-1 Load/store graduations not resulting in a bus request because misses at integer pipe graduation turn into hit or merge with outstanding fill request
|
