| /external/clang/test/CodeGen/ |
| compound-literal.c | 6 typedef int v4i32 __attribute((vector_size(16))); typedef
7 v4i32 *y = &(v4i32){1,2,3,4};
|
| x86_32-arguments-darwin.c | 224 typedef int v4i32 __attribute__((__vector_size__(16))); typedef
228 v4i32 f55(v4i32 arg) { return arg+arg; }
|
| /external/llvm/test/CodeGen/CellSPU/useful-harnesses/ |
| vecoperations.c | 5 typedef int v4i32 __attribute__((ext_vector_type(4))); typedef
50 void print_v4i32(const char *str, v4i32 v) {
76 v4i32 v4i32_shuffle_1(v4i32 a) {
77 v4i32 c2 = a.yzwx;
81 v4i32 v4i32_shuffle_2(v4i32 a) {
82 v4i32 c2 = a.zwxy;
86 v4i32 v4i32_shuffle_3(v4i32 a)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 69 v4i32 = 23, // 4 x i32 enumerator in enum:llvm::MVT::SimpleValueType
210 case v4i32:
239 case v4i32:
288 case v4i32:
369 if (NumElements == 4) return MVT::v4i32;
501 return (V==MVT::v16i8 || V==MVT::v8i16 || V==MVT::v4i32 ||
|
| /external/llvm/lib/VMCore/ |
| ValueTypes.cpp | 129 case MVT::v4i32: return "v4i32";
178 case MVT::v4i32: return VectorType::get(Type::getInt32Ty(Context), 4);
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 402 addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass);
699 SDValue ones = DAG.getConstant(-1, MVT::v4i32 );
[all...] |
| SPUISelDAGToDAG.cpp | 121 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
136 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
184 ((vecVT == MVT::v4i32) &&
591 case MVT::v4i32:
655 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
663 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
671 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 79 DecodePSHUFMask(MVT::v4i32, MI->getOperand(MI->getNumOperands()-1).getImm(),
164 DecodeUNPCKHMask(MVT::v4i32, ShuffleMask);
172 DecodeUNPCKHMask(MVT::v4i32, ShuffleMask);
257 DecodeUNPCKLMask(MVT::v4i32, ShuffleMask);
265 DecodeUNPCKLMask(MVT::v4i32, ShuffleMask);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 324 // We promote all non-typed operations to v4i32.
326 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
328 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
330 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
332 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
334 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
336 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
366 setOperationAction(ISD::AND , MVT::v4i32, Legal);
367 setOperationAction(ISD::OR , MVT::v4i32, Legal);
368 setOperationAction(ISD::XOR , MVT::v4i32, Legal)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86FastISel.cpp | 267 case MVT::v4i32:
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 162 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
470 addQRTypeForNEON(MVT::v4i32);
526 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
562 // It is legal to extload from v4i8 to v4i16 or v4i32.
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 80 case MVT::v4i32: return "MVT::v4i32";
|
