| /frameworks/support/volley/src/com/android/volley/toolbox/ |
| DiskBasedCache.java | 21 import com.android.volley.Cache;
38 * Cache implementation that caches files directly onto the hard disk in the specified
41 public class DiskBasedCache implements Cache {
47 /** Total amount of space currently used by the cache in bytes. */
50 /** The root directory to use for the cache. */
53 /** The maximum size of the cache in bytes. */
59 /** High water mark percentage for the cache */
62 /** Current cache version */
67 * @param rootDirectory The root directory of the cache.
68 * @param maxCacheSizeInBytes The maximum size of the cache in bytes
[all...] |
| /external/oprofile/events/mips/1004K/ |
| events | 16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
29 event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
39 event:0x15 counters:0 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 21-0 L2 cache lines written back to memory
40 event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
55 event:0x24 counters:0 um:zero minimum:500 name:INTERVENTION_STALLS : 36-0 Cache coherence intervention processing stall cycles
60 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache mis
[all...] |
| /external/chromium/build/ |
| install-build-deps.sh | 319 if apt-cache show binutils-gold | grep -Eq 'Version: 2.2[1-9].*'; then
367 mkdir -p "${tmp}/apt/lists/partial" "${tmp}/cache" "${tmp}/partial"
373 Dir::Cache "${tmp}/cache";
374 Dir::Cache::Archives "${tmp}/";
|
| /external/oprofile/events/mips/rm9000/ |
| events | 13 event:0x0a counters:0,1 um:zero minimum:500 name:L2_CACHE_MISSES : L2 cache misses
22 event:0x13 counters:0,1 um:zero minimum:500 name:L2_WRITEBACKS : L2 cache writebacks
25 event:0x16 counters:0,1 um:zero minimum:500 name:CACHE_REMISSES : Cache remisses
31 event:0x1c counters:0,1 um:zero minimum:500 name:CACHE_INSN_STALL_CYCLES : Stall cycles due to cache instructions
|
| /external/chromium/net/base/ |
| x509_certificate.h | 84 SOURCE_FROM_CACHE = 2, // From the disk cache - which contains
136 // certificate cache prefers the handle from the network because our HTTP
137 // cache isn't caching the corresponding intermediate CA certificates yet
292 // cache as appropriate.
352 FRIEND_TEST_ALL_PREFIXES(X509CertificateTest, Cache);
433 // cache as appropriate. The returned string piece will be valid as long
|
| /external/javassist/src/main/javassist/ |
| CtNewWrappedMethod.java | 156 CtMember.Cache cache = clazz.hasMemberCache(); local
157 if (cache != null)
158 cache.addMethod(new CtMethod(body, clazz));
|
| /external/llvm/include/llvm/Analysis/ |
| MemoryDependenceAnalysis.h | 188 /// NonLocalDepEntry - This is an entry in the NonLocalDepInfo cache. For
270 /// block. If the pointer is null, the cache value is not a full query that
316 // used when removing instructions to keep the cache coherent.
324 /// Current AA implementation, just a cache.
429 NonLocalDepInfo *Cache,
|
| /external/webkit/PerformanceTests/SunSpider/ |
| sunspider | 60 --shark-cache Like --shark, but performs a L2 cache-miss sample instead of time sample
73 'shark-cache' => \$runSharkCache,
107 if ($profileName =~ /L2 Cache/) {
109 print "Using Shark L2 Cache Miss Profile: " . $profile . "\n";
113 die "Failed to find L2 Cache Miss Profile for --shark-cache\n" unless ($sharkCacheProfileIndex);
|
| /external/guava/guava-gwt/src-super/com/google/common/cache/super/com/google/common/cache/ |
| CacheBuilder.java | 17 package com.google.common.cache;
24 import com.google.common.cache.CacheLoader.InvalidCacheLoadException;
106 public <K1 extends K, V1 extends V> Cache<K1, V1> build() {
128 // Cache methods
190 // Cache methods
|
| /external/llvm/include/llvm/ADT/ |
| ImmutableSet.h | 350 factory->Cache[factory->maskCacheIndex(computeDigest())] = next;
373 CacheTy Cache;
619 TreeTy *&entry = Cache[maskCacheIndex(digest)];
[all...] |
| /external/llvm/tools/bugpoint/ |
| Miscompilation.cpp | [all...] |
| /external/oprofile/events/x86-64/family10/ |
| unit_masks | 36 0x01 (I)nvalid cache state
37 0x02 (S)hared cache state
38 0x04 (E)xclusive cache state
39 0x08 (O)wner cache state
40 0x10 (M)odified cache state
41 0x1f All cache states
48 0x1e All cache states except refill from northbridge
125 0x20 Hardware prefetch from data cache
130 0x08 Hardware prefetch from data cache
179 0x20 Change-to-Dirty (first store to clean block already in cache)
[all...] |
| /external/guava/guava/src/com/google/common/cache/ |
| CacheBuilder.java | 17 package com.google.common.cache;
34 import com.google.common.cache.AbstractCache.SimpleStatsCounter;
35 import com.google.common.cache.AbstractCache.StatsCounter;
36 import com.google.common.cache.LocalCache.Strength;
49 * <p>A builder of {@link LoadingCache} and {@link Cache} instances having any combination of the
53 * <li>automatic loading of entries into the cache
78 * <p>The returned cache is implemented as a hash table with similar performance characteristics to
80 * {@link Cache} interfaces. The {@code asMap} view (and its collection views) have <i>weakly
82 * modify the cache after the iterator is created, it is undefined which of these changes, if any,
86 * <p><b>Note:</b> by default, the returned cache uses equality comparisons (th
[all...] |
| /external/webkit/PerformanceTests/SunSpider/tests/parse-only/ |
| mootools-1.2.2-core-nc.js | [all...] |
| /external/llvm/lib/Analysis/ |
| LazyValueInfo.cpp | 297 /// LVIValueHandle - A callback value handle update the cache when
314 /// LazyValueInfoCache - This is the cache kept by LazyValueInfo which
328 /// for cache updating.
395 /// threadEdge - This is the update interface to inform the cache that an
400 /// eraseBlock - This is part of the update interface to inform the cache
404 /// clear - Empty the cache.
488 ValueCacheEntryTy &Cache = lookup(Val);
490 LVILatticeVal &BBLV = Cache[BB];
495 // cache needs updating, i.e. if we have solve a new value or not.
503 // OverDefinedCahce. The cache will have been properly updated
[all...] |
| /external/oprofile/events/i386/atom/ |
| events | 8 event:0x2e counters:0,1 um:x41 minimum:6000 name:LLC_MISSES : Last level cache demand requests from this core that missed the LLC
9 event:0x2e counters:0,1 um:x4f minimum:6000 name:LLC_REFS : Last level cache demand requests from this core
24 event:0x22 counters:0,1 um:core minimum:6000 name:L2_DBUS_BUSY : Cycles the L2 cache data bus is busy
25 event:0x24 counters:0,1 um:core,prefetch minimum:500 name:L2_LINES_IN : L2 cache misses
26 event:0x25 counters:0,1 um:core minimum:500 name:L2_M_LINES_IN : L2 cache line modifications
27 event:0x26 counters:0,1 um:core,prefetch minimum:500 name:L2_LINES_OUT : L2 cache lines evicted
28 event:0x27 counters:0,1 um:core,prefetch minimum:500 name:L2_M_LINES_OUT : Modified lines evicted from the L2 cache
30 event:0x29 counters:0,1 um:core,prefetch,mesi minimum:6000 name:L2_LD : L2 cache reads
33 event:0x2E counters:0,1 um:l2_rqsts,core,prefetch,mesi minimum:6000 name:L2_RQSTS : L2 cache requests
34 event:0x30 counters:0,1 um:core,prefetch,mesi minimum:500 name:L2_REJECT_BUSQ : Rejected L2 cache request
[all...] |
| /external/mesa3d/src/mesa/main/ |
| mtypes.h | [all...] |
| /external/oprofile/events/mips/74K/ |
| events | 24 event:0x6 counters:0,2 um:zero minimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache accesses including speculative instructions
25 event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles
41 event:0x17 counters:0,2 um:zero minimum:500 name:DCACHE_LOAD_ACCESSES : 23-0 Counts all accesses to the data cache caused by load instructions
42 event:0x18 counters:0,2 um:zero minimum:500 name:DCACHE_WRITEBACKS : 24-0 Data cache writebacks
46 event:0x1c counters:0,2 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 28-0 L2 Cache Writebacks
47 event:0x1d counters:0,2 um:zero minimum:500 name:L2_CACHE_MISSES : 29-0 L2 Cache Misses
100 event:0x406 counters:1,3 um:zero minimum:500 name:ICACHE_MISSES : 6-1 Instruction cache misses, includes misses from fetch-ahead and speculation
113 event:0x413 counters:1,3 um:zero minimum:500 name:AGEN_BUBBLE_CYCLES : 19-1 DDQ1 (AGEN out-of-order dispatch queue) bubbles due to MFC2 data write or cache access from FSB
116 event:0x416 counters:1,3 um:zero minimum:500 name:DCACHE_LINE_REFILL_REQUESTS : 22-1 Data cache line loads (line refill requests)
117 event:0x417 counters:1,3 um:zero minimum:500 name:DCACHE_ACCESSES : 23-1 Data cache accesse
[all...] |
| /external/oprofile/events/mips/24K/ |
| events | 16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
29 event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
39 event:0x15 counters:0 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 21-0 L2 cache lines written back to memory
40 event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 24K family microarchitecture)
55 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
57 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipelin
[all...] |
| /external/oprofile/events/mips/34K/ |
| events | 16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
29 event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
39 event:0x15 counters:0 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 21-0 L2 cache lines written back to memory
40 event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
59 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
61 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipelin
[all...] |
| /external/oprofile/events/x86-64/family11h/ |
| events | 37 # Data Cache event
38 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
39 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
41 event:0x42 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_SYSTEM : Data cache refills from L2 or system
42 event:0x43 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_SYSTEM : Data cache refills from system
43 event:0x44 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_LINES_EVICTED : Data cache lines evicted
53 # L2 Cache and System Interface events
59 event:0x7d counters:0,1,2,3 um:l2_internal minimum:500 name:REQUESTS_TO_L2 : Requests to L2 cache
60 event:0x7e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 cache misses
63 # Instruction Cache event
[all...] |
| /external/oprofile/events/x86-64/hammer/ |
| events | 37 # Data Cache event
38 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
39 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
41 event:0x42 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_SYSTEM : Data cache refills from L2 or system
42 event:0x43 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_SYSTEM : Data cache refills from system
43 event:0x44 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_LINES_EVICTED : Data cache lines evicted
53 # L2 Cache and System Interface events
59 event:0x7d counters:0,1,2,3 um:l2_internal minimum:500 name:REQUESTS_TO_L2 : Requests to L2 cache
60 event:0x7e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 cache misses
63 # Instruction Cache event
[all...] |
| /external/chromium/chrome/common/extensions/docs/examples/extensions/benchmark/jst/ |
| jsevalcontext.js | 82 * If this instance is recycled from the cache, then the property is
170 * A cache to reuse JsEvalContext instances. (IE6 perf)
314 * Cache for jsEvalToFunction results.
323 * only on expr, we cache the result so we save some Function
|
| /external/chromium/chrome/common/extensions/docs/examples/extensions/irc/servlet/jstemplate/ |
| jsevalcontext.js | 82 * If this instance is recycled from the cache, then the property is
170 * A cache to reuse JsEvalContext instances. (IE6 perf)
314 * Cache for jsEvalToFunction results.
323 * only on expr, we cache the result so we save some Function
|
| /external/llvm/lib/CodeGen/ |
| RegAllocGreedy.cpp | 209 void reset(InterferenceCache &Cache, unsigned Reg) {
212 Intf.setPhysReg(Cache, Reg);
[all...] |
