| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.cpp | 54 case SPU::R0: return 0;
189 SPUGenRegisterInfo(SPU::R0), Subtarget(subtarget), TII(tii)
219 SPU::R0, /* link register */
227 R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
232 Reserved.set(SPU::R0); // LR
|
| /external/openssl/crypto/md4/ |
| md4_locl.h | 102 #define R0(a,b,c,d,k,s,t) { \
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 303 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
309 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
315 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
321 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
327 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
333 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
339 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
345 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
351 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
357 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
[all...] |
| ARMBaseRegisterInfo.h | 36 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
41 case R0: case R1: case R2: case R3:
|
| /external/libvpx/vp8/common/ppc/ |
| idctllm_altivec.asm | 14 .macro load_c V, LABEL, OFF, R0, R1
15 lis \R0, \LABEL@ha
16 la \R1, \LABEL@l(\R0)
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 124 Reserved.set(PPC::R0);
209 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
255 /// addi R0, SP, \#frameSize ; get the address of the previous frame
256 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
287 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
299 Reg = PPC::R0;
367 /// reserving a whole register (R0), we scrounge for one here. This generates
391 (LP64 ? PPC::X0 : PPC::R0);
434 (LP64 ? PPC::X0 : PPC::R0);
[all...] |
| PPCInstrInfo.cpp | 408 // FIXME: We need a scatch reg here. The trouble with using R0 is that
419 (is64Bit ? PPC::X0 : PPC::R0);
477 // R0 = ADDI FI#
478 // STVX VAL, 0, R0
480 // FIXME: We use R0 here, because it isn't available for RA.
481 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
485 .addReg(PPC::R0)
486 .addReg(PPC::R0));
557 // FIXME: We need a scatch reg here. The trouble with using R0 is that
563 PPC::R2 : PPC::R0;
[all...] |
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 190 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
205 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
215 // When used as the base register, r0 reads constant zero rather than
217 // assembler requires that we print r0 as 0 (no r) when used as the base.
218 if (MI->getOperand(OpNo).getReg() == PPC::R0)
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCBaseInfo.h | 31 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
|
| /external/openssl/crypto/md5/ |
| md5_locl.h | 112 #define R0(a,b,c,d,k,s,t) { \
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMBaseInfo.h | 155 case R0: case S0: case D0: case Q0: return 0;
224 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
229 case R0: case R1: case R2: case R3:
|
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeBaseInfo.h | 102 /// MBlaze::R0, return the number that it corresponds to (e.g. 0).
105 case MBlaze::R0 : return 0;
166 /// MBlaze::R0, return the number that it corresponds to (e.g. 0).
169 case 0 : return MBlaze::R0;
|
| /libcore/luni/src/test/java/libcore/java/lang/ |
| ClassCastExceptionTest.java | 157 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
162 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.cpp | 73 Reserved.set(MBlaze::R0);
|
| MBlazeISelDAGToDAG.cpp | 168 Base = CurDAG->getRegister(MBlaze::R0, CN->getValueType(0));
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| Deemph_32_opt.s | 26 @x_hi RN R0
38 LDRSH r6, [r0], #2 @load x_hi[0]
50 LDRSH r6, [r0], #2 @load x_hi[1]
69 LDRSH r6, [r0], #2 @load x_hi[]
77 LDRSH r6, [r0], #2 @load x_hi[]
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| Deemph_32_neon.s | 26 @x_hi RN R0
38 LDRSH r6, [r0], #2 @load x_hi[0]
50 LDRSH r6, [r0], #2 @load x_hi[1]
69 LDRSH r6, [r0], #2 @load x_hi[]
77 LDRSH r6, [r0], #2 @load x_hi[]
|
| /frameworks/av/media/libstagefright/codecs/avc/enc/src/ |
| intra_est.cpp | 734 int P0, Q0, R0, S0, P1, Q1, R1, P2, Q2;
736 int r0, r1, r2, r3, r4, r5, r6, r7; local
863 temp |= (Q0 << 16); // [Q0 Q1 R0 DO]
864 temp |= (Q1 << 24); // [R0 D0 D1 D1]
868 R0 = (P_K + P_L + 1) >> 1;
871 temp |= (R0 << 16);
877 temp = R0 | (D0 << 8);
929 r0 = P_A;
934 r0 += (r1 << 1);
935 r0 += r2
[all...] |
| /external/valgrind/main/coregrind/m_sigframe/ |
| sigframe-arm-linux.c | 138 SC2(r0,R0);
312 REST(r0,R0);
|
| /external/libvpx/vp8/common/arm/armv6/ |
| recon_v6.asm | 17 prd RN r0
23 ; R0 char* pred_ptr
129 ; R0 char *pred_ptr
226 ; R0 char *pred_ptr
|
| /external/libvpx/vp8/encoder/ppc/ |
| fdct_altivec.asm | 15 .macro load_c V, LABEL, OFF, R0, R1
16 lis \R0, \LABEL@ha
17 la \R1, \LABEL@l(\R0)
96 stw r0, 0(r8)
97 lwz r0, 4(r3)
98 stw r0, 4(r8)
99 lwzux r0, r3,r5
100 stw r0, 8(r8)
101 lwz r0, 4(r3)
102 stw r0, 12(r8
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssembler.cpp | 155 MOV(AL, 0, R0, R0); // NOP
|
| ARMAssemblerInterface.h | 50 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
57 LIST(R0), LIST(R1), LIST(R2), LIST(R3), LIST(R4), LIST(R5), LIST(R6),
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 104 unsigned Reg = Hexagon::R0;
|
| /external/valgrind/main/VEX/auxprogs/ |
| genoffsets.c | 149 GENOFFSET(ARM,arm,R0);
|
