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      1 //===-- SPURegisterInfo.cpp - Cell SPU Register Information ---------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the Cell implementation of the TargetRegisterInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #define DEBUG_TYPE "reginfo"
     15 #include "SPURegisterInfo.h"
     16 #include "SPU.h"
     17 #include "SPUInstrBuilder.h"
     18 #include "SPUSubtarget.h"
     19 #include "SPUMachineFunction.h"
     20 #include "SPUFrameLowering.h"
     21 #include "llvm/Constants.h"
     22 #include "llvm/Type.h"
     23 #include "llvm/CodeGen/ValueTypes.h"
     24 #include "llvm/CodeGen/MachineInstrBuilder.h"
     25 #include "llvm/CodeGen/MachineModuleInfo.h"
     26 #include "llvm/CodeGen/MachineFunction.h"
     27 #include "llvm/CodeGen/MachineFrameInfo.h"
     28 #include "llvm/CodeGen/MachineRegisterInfo.h"
     29 #include "llvm/CodeGen/RegisterScavenging.h"
     30 #include "llvm/CodeGen/ValueTypes.h"
     31 #include "llvm/Target/TargetFrameLowering.h"
     32 #include "llvm/Target/TargetInstrInfo.h"
     33 #include "llvm/Target/TargetMachine.h"
     34 #include "llvm/Target/TargetOptions.h"
     35 #include "llvm/Support/CommandLine.h"
     36 #include "llvm/Support/Debug.h"
     37 #include "llvm/Support/ErrorHandling.h"
     38 #include "llvm/Support/MathExtras.h"
     39 #include "llvm/Support/raw_ostream.h"
     40 #include "llvm/ADT/BitVector.h"
     41 #include "llvm/ADT/STLExtras.h"
     42 #include <cstdlib>
     43 
     44 #define GET_REGINFO_TARGET_DESC
     45 #include "SPUGenRegisterInfo.inc"
     46 
     47 using namespace llvm;
     48 
     49 /// getRegisterNumbering - Given the enum value for some register, e.g.
     50 /// PPC::F14, return the number that it corresponds to (e.g. 14).
     51 unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
     52   using namespace SPU;
     53   switch (RegEnum) {
     54   case SPU::R0: return 0;
     55   case SPU::R1: return 1;
     56   case SPU::R2: return 2;
     57   case SPU::R3: return 3;
     58   case SPU::R4: return 4;
     59   case SPU::R5: return 5;
     60   case SPU::R6: return 6;
     61   case SPU::R7: return 7;
     62   case SPU::R8: return 8;
     63   case SPU::R9: return 9;
     64   case SPU::R10: return 10;
     65   case SPU::R11: return 11;
     66   case SPU::R12: return 12;
     67   case SPU::R13: return 13;
     68   case SPU::R14: return 14;
     69   case SPU::R15: return 15;
     70   case SPU::R16: return 16;
     71   case SPU::R17: return 17;
     72   case SPU::R18: return 18;
     73   case SPU::R19: return 19;
     74   case SPU::R20: return 20;
     75   case SPU::R21: return 21;
     76   case SPU::R22: return 22;
     77   case SPU::R23: return 23;
     78   case SPU::R24: return 24;
     79   case SPU::R25: return 25;
     80   case SPU::R26: return 26;
     81   case SPU::R27: return 27;
     82   case SPU::R28: return 28;
     83   case SPU::R29: return 29;
     84   case SPU::R30: return 30;
     85   case SPU::R31: return 31;
     86   case SPU::R32: return 32;
     87   case SPU::R33: return 33;
     88   case SPU::R34: return 34;
     89   case SPU::R35: return 35;
     90   case SPU::R36: return 36;
     91   case SPU::R37: return 37;
     92   case SPU::R38: return 38;
     93   case SPU::R39: return 39;
     94   case SPU::R40: return 40;
     95   case SPU::R41: return 41;
     96   case SPU::R42: return 42;
     97   case SPU::R43: return 43;
     98   case SPU::R44: return 44;
     99   case SPU::R45: return 45;
    100   case SPU::R46: return 46;
    101   case SPU::R47: return 47;
    102   case SPU::R48: return 48;
    103   case SPU::R49: return 49;
    104   case SPU::R50: return 50;
    105   case SPU::R51: return 51;
    106   case SPU::R52: return 52;
    107   case SPU::R53: return 53;
    108   case SPU::R54: return 54;
    109   case SPU::R55: return 55;
    110   case SPU::R56: return 56;
    111   case SPU::R57: return 57;
    112   case SPU::R58: return 58;
    113   case SPU::R59: return 59;
    114   case SPU::R60: return 60;
    115   case SPU::R61: return 61;
    116   case SPU::R62: return 62;
    117   case SPU::R63: return 63;
    118   case SPU::R64: return 64;
    119   case SPU::R65: return 65;
    120   case SPU::R66: return 66;
    121   case SPU::R67: return 67;
    122   case SPU::R68: return 68;
    123   case SPU::R69: return 69;
    124   case SPU::R70: return 70;
    125   case SPU::R71: return 71;
    126   case SPU::R72: return 72;
    127   case SPU::R73: return 73;
    128   case SPU::R74: return 74;
    129   case SPU::R75: return 75;
    130   case SPU::R76: return 76;
    131   case SPU::R77: return 77;
    132   case SPU::R78: return 78;
    133   case SPU::R79: return 79;
    134   case SPU::R80: return 80;
    135   case SPU::R81: return 81;
    136   case SPU::R82: return 82;
    137   case SPU::R83: return 83;
    138   case SPU::R84: return 84;
    139   case SPU::R85: return 85;
    140   case SPU::R86: return 86;
    141   case SPU::R87: return 87;
    142   case SPU::R88: return 88;
    143   case SPU::R89: return 89;
    144   case SPU::R90: return 90;
    145   case SPU::R91: return 91;
    146   case SPU::R92: return 92;
    147   case SPU::R93: return 93;
    148   case SPU::R94: return 94;
    149   case SPU::R95: return 95;
    150   case SPU::R96: return 96;
    151   case SPU::R97: return 97;
    152   case SPU::R98: return 98;
    153   case SPU::R99: return 99;
    154   case SPU::R100: return 100;
    155   case SPU::R101: return 101;
    156   case SPU::R102: return 102;
    157   case SPU::R103: return 103;
    158   case SPU::R104: return 104;
    159   case SPU::R105: return 105;
    160   case SPU::R106: return 106;
    161   case SPU::R107: return 107;
    162   case SPU::R108: return 108;
    163   case SPU::R109: return 109;
    164   case SPU::R110: return 110;
    165   case SPU::R111: return 111;
    166   case SPU::R112: return 112;
    167   case SPU::R113: return 113;
    168   case SPU::R114: return 114;
    169   case SPU::R115: return 115;
    170   case SPU::R116: return 116;
    171   case SPU::R117: return 117;
    172   case SPU::R118: return 118;
    173   case SPU::R119: return 119;
    174   case SPU::R120: return 120;
    175   case SPU::R121: return 121;
    176   case SPU::R122: return 122;
    177   case SPU::R123: return 123;
    178   case SPU::R124: return 124;
    179   case SPU::R125: return 125;
    180   case SPU::R126: return 126;
    181   case SPU::R127: return 127;
    182   default:
    183     report_fatal_error("Unhandled reg in SPURegisterInfo::getRegisterNumbering");
    184   }
    185 }
    186 
    187 SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
    188                                  const TargetInstrInfo &tii) :
    189   SPUGenRegisterInfo(SPU::R0), Subtarget(subtarget), TII(tii)
    190 {
    191 }
    192 
    193 /// getPointerRegClass - Return the register class to use to hold pointers.
    194 /// This is used for addressing modes.
    195 const TargetRegisterClass *
    196 SPURegisterInfo::getPointerRegClass(unsigned Kind) const {
    197   return &SPU::R32CRegClass;
    198 }
    199 
    200 const uint16_t *
    201 SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
    202 {
    203   // Cell ABI calling convention
    204   static const uint16_t SPU_CalleeSaveRegs[] = {
    205     SPU::R80, SPU::R81, SPU::R82, SPU::R83,
    206     SPU::R84, SPU::R85, SPU::R86, SPU::R87,
    207     SPU::R88, SPU::R89, SPU::R90, SPU::R91,
    208     SPU::R92, SPU::R93, SPU::R94, SPU::R95,
    209     SPU::R96, SPU::R97, SPU::R98, SPU::R99,
    210     SPU::R100, SPU::R101, SPU::R102, SPU::R103,
    211     SPU::R104, SPU::R105, SPU::R106, SPU::R107,
    212     SPU::R108, SPU::R109, SPU::R110, SPU::R111,
    213     SPU::R112, SPU::R113, SPU::R114, SPU::R115,
    214     SPU::R116, SPU::R117, SPU::R118, SPU::R119,
    215     SPU::R120, SPU::R121, SPU::R122, SPU::R123,
    216     SPU::R124, SPU::R125, SPU::R126, SPU::R127,
    217     SPU::R2,    /* environment pointer */
    218     SPU::R1,    /* stack pointer */
    219     SPU::R0,    /* link register */
    220     0 /* end */
    221   };
    222 
    223   return SPU_CalleeSaveRegs;
    224 }
    225 
    226 /*!
    227  R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
    228  generally unused) are the Cell's reserved registers
    229  */
    230 BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
    231   BitVector Reserved(getNumRegs());
    232   Reserved.set(SPU::R0);                // LR
    233   Reserved.set(SPU::R1);                // SP
    234   Reserved.set(SPU::R2);                // environment pointer
    235   return Reserved;
    236 }
    237 
    238 //===----------------------------------------------------------------------===//
    239 // Stack Frame Processing methods
    240 //===----------------------------------------------------------------------===//
    241 
    242 //--------------------------------------------------------------------------
    243 void
    244 SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
    245                                                MachineBasicBlock &MBB,
    246                                                MachineBasicBlock::iterator I)
    247   const
    248 {
    249   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
    250   MBB.erase(I);
    251 }
    252 
    253 void
    254 SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
    255                                      RegScavenger *RS) const
    256 {
    257   unsigned i = 0;
    258   MachineInstr &MI = *II;
    259   MachineBasicBlock &MBB = *MI.getParent();
    260   MachineFunction &MF = *MBB.getParent();
    261   MachineFrameInfo *MFI = MF.getFrameInfo();
    262   DebugLoc dl = II->getDebugLoc();
    263 
    264   while (!MI.getOperand(i).isFI()) {
    265     ++i;
    266     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
    267   }
    268 
    269   MachineOperand &SPOp = MI.getOperand(i);
    270   int FrameIndex = SPOp.getIndex();
    271 
    272   // Now add the frame object offset to the offset from r1.
    273   int Offset = MFI->getObjectOffset(FrameIndex);
    274 
    275   // Most instructions, except for generated FrameIndex additions using AIr32
    276   // and ILAr32, have the immediate in operand 1. AIr32 and ILAr32 have the
    277   // immediate in operand 2.
    278   unsigned OpNo = 1;
    279   if (MI.getOpcode() == SPU::AIr32 || MI.getOpcode() == SPU::ILAr32)
    280     OpNo = 2;
    281 
    282   MachineOperand &MO = MI.getOperand(OpNo);
    283 
    284   // Offset is biased by $lr's slot at the bottom.
    285   Offset += MO.getImm() + MFI->getStackSize() + SPUFrameLowering::minStackSize();
    286   assert((Offset & 0xf) == 0
    287          && "16-byte alignment violated in eliminateFrameIndex");
    288 
    289   // Replace the FrameIndex with base register with $sp (aka $r1)
    290   SPOp.ChangeToRegister(SPU::R1, false);
    291 
    292   // if 'Offset' doesn't fit to the D-form instruction's
    293   // immediate, convert the instruction to X-form
    294   // if the instruction is not an AI (which takes a s10 immediate), assume
    295   // it is a load/store that can take a s14 immediate
    296   if ((MI.getOpcode() == SPU::AIr32 && !isInt<10>(Offset))
    297       || !isInt<14>(Offset)) {
    298     int newOpcode = convertDFormToXForm(MI.getOpcode());
    299     unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj);
    300     BuildMI(MBB, II, dl, TII.get(SPU::ILr32), tmpReg )
    301         .addImm(Offset);
    302     BuildMI(MBB, II, dl, TII.get(newOpcode), MI.getOperand(0).getReg())
    303         .addReg(tmpReg, RegState::Kill)
    304         .addReg(SPU::R1);
    305     // remove the replaced D-form instruction
    306     MBB.erase(II);
    307   } else {
    308     MO.ChangeToImmediate(Offset);
    309   }
    310 }
    311 
    312 unsigned
    313 SPURegisterInfo::getFrameRegister(const MachineFunction &MF) const
    314 {
    315   return SPU::R1;
    316 }
    317 
    318 int
    319 SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
    320 {
    321   switch(dFormOpcode)
    322   {
    323     case SPU::AIr32:     return SPU::Ar32;
    324     case SPU::LQDr32:    return SPU::LQXr32;
    325     case SPU::LQDr128:   return SPU::LQXr128;
    326     case SPU::LQDv16i8:  return SPU::LQXv16i8;
    327     case SPU::LQDv4i32:  return SPU::LQXv4i32;
    328     case SPU::LQDv4f32:  return SPU::LQXv4f32;
    329     case SPU::STQDr32:   return SPU::STQXr32;
    330     case SPU::STQDr128:  return SPU::STQXr128;
    331     case SPU::STQDv16i8: return SPU::STQXv16i8;
    332     case SPU::STQDv4i32: return SPU::STQXv4i32;
    333     case SPU::STQDv4f32: return SPU::STQXv4f32;
    334 
    335     default: assert( false && "Unhandled D to X-form conversion");
    336   }
    337   // default will assert, but need to return something to keep the
    338   // compiler happy.
    339   return dFormOpcode;
    340 }
    341 
    342 // TODO this is already copied from PPC. Could this convenience function
    343 // be moved to the RegScavenger class?
    344 unsigned
    345 SPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II,
    346                                      RegScavenger *RS,
    347                                      const TargetRegisterClass *RC,
    348                                      int SPAdj) const
    349 {
    350   assert(RS && "Register scavenging must be on");
    351   unsigned Reg = RS->FindUnusedReg(RC);
    352   if (Reg == 0)
    353     Reg = RS->scavengeRegister(RC, II, SPAdj);
    354   assert( Reg && "Register scavenger failed");
    355   return Reg;
    356 }
    357