| /external/openssl/crypto/bn/asm/ |
| mips3.s | 89 sltu v0,t1,v0 /* All manuals say it "compares 32-bit
96 sltu AT,t1,AT
104 sltu v0,t3,v0
109 sltu AT,t3,AT
118 sltu v0,ta1,v0
123 sltu AT,ta1,AT
131 sltu v0,ta3,v0
136 sltu AT,ta3,AT
155 sltu v0,t1,v0
160 sltu AT,t1,A
[all...] |
| bn-mips.s | 37 sltu $2,$13,$2 # All manuals say it "compares 32-bit
45 sltu $1,$13,$1
52 sltu $2,$15,$2
58 sltu $1,$15,$1
66 sltu $2,$9,$2
72 sltu $1,$9,$1
79 sltu $2,$11,$2
84 sltu $1,$11,$1
101 sltu $2,$13,$2
106 sltu $1,$13,$
[all...] |
| mips.pl | 154 sltu $v0,$t1,$v0 # All manuals say it "compares 32-bit
162 sltu $at,$t1,$at
169 sltu $v0,$t3,$v0
175 sltu $at,$t3,$at
183 sltu $v0,$ta1,$v0
189 sltu $at,$ta1,$at
196 sltu $v0,$ta3,$v0
201 sltu $at,$ta3,$at
218 sltu $v0,$t1,$v0
223 sltu $at,$t1,$a
[all...] |
| mips-mont.s | 66 sltu $1,$24,$10
84 sltu $1,$10,$11
85 sltu $2,$24,$25
92 sltu $1,$24,$10
97 sltu $2,$22,$9
106 sltu $1,$10,$11
110 sltu $2,$24,$25
113 sltu $1,$24,$10
119 sltu $1,$25,$11
139 sltu $1,$10,$2
[all...] |
| mips3-mont.pl | 111 sltu AT,$lo1,$lo0
129 sltu AT,$lo0,$hi0
130 sltu s7,$lo1,$hi1
137 sltu AT,$lo1,$lo0
142 sltu s7,$j,$num
151 sltu AT,$lo0,$hi0
155 sltu s7,$lo1,$hi1
158 sltu AT,$lo1,$lo0
164 sltu AT,$hi1,$hi0
184 sltu AT,$lo0,$t
[all...] |
| mips-mont.pl | 196 sltu $at,$lo1,$lo0
214 sltu $at,$lo0,$hi0
215 sltu $t0,$lo1,$hi1
222 sltu $at,$lo1,$lo0
227 sltu $t0,$j,$num
236 sltu $at,$lo0,$hi0
240 sltu $t0,$lo1,$hi1
243 sltu $at,$lo1,$lo0
249 sltu $at,$hi1,$hi0
269 sltu $at,$lo0,$t
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| 2008-06-05-Carry.ll | 6 ; CHECK: sltu
17 ; CHECK: sltu
|
| /external/kernel-headers/original/asm-mips/ |
| checksum.h | 83 " sltu $1, %0, $1 \n"
141 " sltu $1, %0, %2 \n"
145 " sltu $1, %0, %3 \n"
149 " sltu $1, %0, %4 \n"
206 " sltu $1, %0, %5 \n"
210 " sltu $1, %0, %6 \n"
214 " sltu $1, %0, %1 \n"
219 " sltu $1, %0, %1 \n"
224 " sltu $1, %0, %1 \n"
229 " sltu $1, %0, %1 \n
[all...] |
| div64.h | 41 " sltu %5, %0, %z6\n\t" \
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 356 COMPARE(sltu(a0, a1, a2),
357 "00a6202b sltu a0, a1, a2");
358 COMPARE(sltu(s0, s1, s2),
359 "0232802b sltu s0, s1, s2");
360 COMPARE(sltu(t2, t3, t4),
361 "016c502b sltu t2, t3, t4");
362 COMPARE(sltu(v0, v1, a2),
363 "0066102b sltu v0, v1, a2");
|
| /external/llvm/lib/Target/Mips/ |
| MipsCondMov.td | 171 defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
174 defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
191 defm : MovzPats0<CPURegs, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
202 defm : MovzPats0<CPURegs, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
207 defm : MovzPats0<CPURegs, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
|
| MipsInstrInfo.td | [all...] |
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MacroAssemblerMIPS.h | [all...] |
| /bionic/libc/kernel/arch-mips/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /prebuilts/gcc/darwin-x86/mips/mipsel-linux-android-4.4.3/sysroot/usr/include/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /prebuilts/gcc/linux-x86/mips/mipsel-linux-android-4.4.3/sysroot/usr/include/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | 730 void MacroAssembler::Sltu(Register rd, Register rs, const Operand& rt) {
732 sltu(rd, rs, rt.rm());
740 sltu(rd, rs, at);
[all...] |
| constants-mips.cc | 264 case SLTU:
|
| deoptimizer-mips.cc | 122 // sltu at, sp, t0 / slt at, a3, zero_reg (in case of count based interrupts)
132 // Replace the sltu instruction with load-imm 1 to at, so beq is not taken.
168 // Restore the sltu instruction so beq can be taken again.
173 patcher.masm()->sltu(at, sp, t0);
[all...] |
| disasm-mips.cc | 717 case SLTU:
718 Format(instr, "sltu 'rd, 'rs, 'rt");
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips32.txt | 366 # CHECK: sltu v1,v1,a1
|
| mips32_le.txt | 369 # CHECK: sltu v1,v1,a1
|
| mips32r2.txt | 381 # CHECK: sltu v1,v1,a1
|
| mips32r2_le.txt | 384 # CHECK: sltu v1,v1,a1
|
