| /external/llvm/lib/Transforms/Utils/ |
| AddrModeMatcher.cpp | 65 /// Return true and update AddrMode if this addr mode is legal for the target,
80 if (AddrMode.Scale != 0 && AddrMode.ScaledReg != ScaleReg)
83 ExtAddrMode TestAddrMode = AddrMode;
95 AddrMode = TestAddrMode;
97 // Okay, we decided that we can add ScaleReg+Scale to AddrMode. Check now
110 AddrMode = TestAddrMode;
152 /// mode and return true, otherwise return false without modifying AddrMode.
181 ExtAddrMode BackupAddrMode = AddrMode;
188 AddrMode = BackupAddrMode
[all...] |
| /external/llvm/include/llvm/Transforms/Utils/ |
| AddrModeMatcher.h | 34 /// ExtAddrMode - This is an extended version of TargetLowering::AddrMode
36 struct ExtAddrMode : public TargetLowering::AddrMode {
64 /// AddrMode - This is the addressing mode that we're building up. This is
66 ExtAddrMode &AddrMode;
76 : AddrModeInsts(AMI), TLI(T), AccessTy(AT), MemoryInst(MI), AddrMode(AM) {
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 393 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
398 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
468 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
474 if (AddrMode == ARMII::AddrModeT2_so) {
484 AddrMode = ARMII::AddrModeT2_i12;
489 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
503 } else if (AddrMode == ARMII::AddrMode5) {
534 if (AddrMode == ARMII::AddrMode5
[all...] |
| ARMInstrFormats.td | 90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>
[all...] |
| Thumb1RegisterInfo.cpp | 394 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
481 if (AddrMode != ARMII::AddrModeT1_s)
692 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
713 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
|
| ARMBaseRegisterInfo.cpp | 785 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
789 switch (AddrMode) {
[all...] |
| ARMISelLowering.h | 286 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
287 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
|
| ARMBaseInstrInfo.cpp | 146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
158 switch (AddrMode) {
[all...] |
| ARMInstrThumb.td | 552 AddrMode am, InstrItinClass itin_r,
569 AddrMode am, InstrItinClass itin_r,
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| CodeGenPrepare.cpp | 767 ExtAddrMode AddrMode;
797 AddrMode = NewAddrMode;
800 } else if (NewAddrMode == AddrMode) {
840 DEBUG(dbgs() << "CGP: Found local addrmode: " << AddrMode << "\n");
855 DEBUG(dbgs() << "CGP: Reusing nonlocal addrmode: " << AddrMode << " for "
860 DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode << " for "
872 if (AddrMode.BaseReg)
[all...] |
| LoopStrengthReduce.cpp | 40 // TODO: Should TargetLowering::AddrMode::BaseGV be changed to a ConstantExpr
226 TargetLowering::AddrMode AM;
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMBaseInfo.h | 251 enum AddrMode {
271 inline static const char *AddrModeToString(AddrMode addrmode) {
272 switch (addrmode) {
342 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.h | 180 virtual bool isLegalAddressingMode(const AddrMode &AM,
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 152 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
|
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 103 virtual bool isLegalAddressingMode(const AddrMode &AM,
|
| XCoreISelLowering.cpp | [all...] |
| /external/v8/src/arm/ |
| assembler-arm.h | 459 explicit MemOperand(Register rn, int32_t offset = 0, AddrMode am = Offset);
464 explicit MemOperand(Register rn, Register rm, AddrMode am = Offset);
470 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
484 AddrMode am() const { return am_; }
496 AddrMode am_; // bits P, U, and W
[all...] |
| constants-arm.h | 318 enum AddrMode {
|
| assembler-arm.cc | 208 MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am) {
215 MemOperand::MemOperand(Register rn, Register rm, AddrMode am) {
225 ShiftOp shift_op, int shift_imm, AddrMode am) {
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 339 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 559 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 3103 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); local
[all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcherGen.cpp | 483 // checks (e.g. addrmode matches). We emit this after the structural match
[all...] |
