| /external/llvm/test/CodeGen/X86/ |
| vec_ctbits.ll | 3 declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
4 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1)
5 declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
8 %c = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 true)
12 %c = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 true)
16 %c = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)
|
| widen_conv-1.ll | 4 ; truncate v2i64 to v2i32
|
| legalizedag_vec.ll | 6 ; v2i64 is a legal type but with mmx disabled, i64 is an illegal type. When
|
| dagcombine-buildvector.ll | 4 ; with v2i64 build_vector i32, i32.
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| vec_i64.ll | 4 ; Used movq to load i64 into a v2i64 when the top i64 is 0.
|
| /external/llvm/lib/Target/CellSPU/ |
| SPU64InstrInfo.td | 21 // 4. v2i64 setcc results are v4i32, which can be converted to a FSM mask (TODO)
24 // 5. The code sequences for r64 and v2i64 are probably overly conservative,
67 // v2i64 seteq (equality): the setcc result is v4i32
71 def v2i64: CodeFrag<(i32 (COPY_TO_REGCLASS CEQv2i64compare.Fragment, R32C))>;
83 def : Pat<(seteq (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)), I64EQv2i64.Fragment>;
120 def v2i64: CodeFrag<CLGTv2i64compare.Fragment>;
132 //def : Pat<(setugt (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)),
154 def v2i64: CodeFrag<CLGEv2i64compare.Fragment>
[all...] |
| SPUCallingConv.td | 20 CCIfType<[i8,i16,i32,i64,i128,f32,f64,v16i8,v8i16,v4i32,v2i64,v4f32,v2f64],
37 v16i8, v8i16, v4i32, v4f32, v2i64, v2f64],
51 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
| SPUInstrInfo.td | 63 def v2i64: LoadDFormVec<v2i64>;
95 def v2i64: LoadAFormVec<v2i64>;
127 def v2i64: LoadXFormVec<v2i64>;
175 def v2i64: StoreDFormVec<v2i64>;
205 def v2i64: StoreAFormVec<v2i64>;
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| 2010-06-29-PartialRedefFastAlloc.ll | 19 %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %arg, i32 1)
25 declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly
|
| vshll.ll | 23 %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
47 %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
73 %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >)
79 declare <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
83 declare <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
|
| vpadal.ll | 80 %tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
107 %tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
121 declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
125 declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
|
| /external/llvm/test/CodeGen/CellSPU/useful-harnesses/ |
| vecoperations.c | 7 typedef long long v2i64 __attribute__((ext_vector_type(2))); typedef
58 void print_v2i64(const char *str, v2i64 v) {
126 v2i64 v2i64_shuffle(v2i64 a) {
127 v2i64 c2 = a.yx;
147 v2i64 v3 = { 691043ll, 910301513ll };
|
| /external/llvm/test/TableGen/ |
| TargetInstrSpec.td | 10 def v2i64 : ValueType<128, 22>; // 2 x i64 vector value
59 def VR128 : RegisterClass<[v2i64, v2f64],
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| cast.td | 9 def v2i64 : ValueType<128, 22>; // 2 x i64 vector value
58 def VR128 : RegisterClass<[v2i64, v2f64],
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| MultiPat.td | 9 def v2i64 : ValueType<128, 22>; // 2 x i64 vector value
67 def VR128 : RegisterClass<[v2i64, v2f64],
|
| /external/valgrind/main/coregrind/m_gdbserver/ |
| 32bit-sse-valgrind-s1.xml | 15 <vector id="v2i64" type="int64" count="2"/>
22 <field name="v2_int64" type="v2i64"/>
|
| 32bit-sse-valgrind-s2.xml | 15 <vector id="v2i64" type="int64" count="2"/>
22 <field name="v2_int64" type="v2i64"/>
|
| 32bit-sse.xml | 15 <vector id="v2i64" type="int64" count="2"/>
22 <field name="v2_int64" type="v2i64"/>
|
| 64bit-sse-valgrind-s1.xml | 15 <vector id="v2i64" type="int64" count="2"/>
22 <field name="v2_int64" type="v2i64"/>
|
| 64bit-sse-valgrind-s2.xml | 15 <vector id="v2i64" type="int64" count="2"/>
22 <field name="v2_int64" type="v2i64"/>
|
| 64bit-sse.xml | 15 <vector id="v2i64" type="int64" count="2"/>
22 <field name="v2_int64" type="v2i64"/>
|
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.td | 28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
73 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
118 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
128 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
143 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
155 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
|
| /external/llvm/lib/Target/X86/ |
| X86InstrFragmentsSIMD.td | 201 // NOTE: all 128-bit integer vector loads are promoted to v2i64
204 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
245 // NOTE: all 128-bit integer vector loads are promoted to v2i64
251 (v2i64 (alignedload node:$ptr))>;
277 // NOTE: all 128-bit integer vector loads are promoted to v2i64
280 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
329 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
338 (bitconvert (v2i64 (X86vzmovl
339 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
345 (bitconvert (v2i64 (X86vzload node:$src)))>
[all...] |
| X86InstrMMX.td | 186 (i64 (vector_extract (v2i64 VR128:$src),
192 (v2i64 (scalar_to_vector
416 [SDTCisVT<0, v2i64>, SDTCisVT<1, x86mmx>]>>;
418 def : Pat<(v2i64 (MMX_X86movq2dq VR64:$src)),
419 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
421 def : Pat<(v2i64 (MMX_X86movq2dq (load_mmx addr:$src))),
422 (v2i64 (MOVQI2PQIrm addr:$src))>;
424 def : Pat<(v2i64 (MMX_X86movq2dq
426 (v2i64 (MOVDI2PDIrm addr:$src))>;
430 [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
[all...] |
| X86InstrSSE.td | 259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
271 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
298 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
299 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
300 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>
[all...] |
