1 ; RUN: llc < %s -O0 -mcpu=cortex-a8 | FileCheck %s 2 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" 3 target triple = "thumbv7-apple-darwin10" 4 5 ; This tests the fast register allocator's handling of partial redefines: 6 ; 7 ; %reg1028:dsub_0<def>, %reg1028:dsub_1<def> = VLD1q64 %reg1025... 8 ; %reg1030:dsub_1<def> = COPY %reg1028:dsub_0<kill> 9 ; 10 ; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial 11 ; redef, it cannot also get %Q0. 12 13 ; CHECK: vld1.64 {d16, d17}, [r{{.}}] 14 ; CHECK-NOT: vld1.64 {d16, d17} 15 ; CHECK: vmov.f64 16 17 define i32 @test(i8* %arg) nounwind { 18 entry: 19 %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %arg, i32 1) 20 %1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> <i32 1, i32 2> 21 store <2 x i64> %1, <2 x i64>* undef, align 16 22 ret i32 undef 23 } 24 25 declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly 26
