1 /* 2 * Copyright (c) 2008, Google Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <boot/boot.h> 30 #include <boot/uart.h> 31 #include <msm7k/uart.h> 32 33 static unsigned uart_base = MSM_UART1_BASE; 34 35 #define uwr(v,a) writel(v, uart_base + (a)) 36 #define urd(a) readl(uart_base + (a)) 37 38 #define UART_NEED_INIT 1 39 40 void uart_init(unsigned n) 41 { 42 43 switch(n) { 44 case 0: 45 uart_base = MSM_UART1_BASE; 46 break; 47 case 1: 48 uart_base = MSM_UART2_BASE; 49 break; 50 case 2: 51 uart_base = MSM_UART3_BASE; 52 break; 53 } 54 55 #if UART_NEED_INIT 56 uwr(0x0A, UART_CR); /* disable TX and RX */ 57 58 uwr(0x30, UART_CR); /* reset error status */ 59 uwr(0x10, UART_CR); /* reset receiver */ 60 uwr(0x20, UART_CR); /* reset transmitter */ 61 62 mdelay(100); 63 64 /* configuration for 19.2MHz TCXO */ 65 uwr(0xC0, UART_MREG); 66 uwr(0xAF, UART_NREG); 67 uwr(0x80, UART_DREG); 68 uwr(0x19, UART_MNDREG); 69 70 uwr(0x10, UART_CR); /* reset RX */ 71 uwr(0x20, UART_CR); /* reset TX */ 72 uwr(0x30, UART_CR); /* reset error status */ 73 uwr(0x40, UART_CR); /* reset RX break */ 74 uwr(0x70, UART_CR); /* rest? */ 75 uwr(0xD0, UART_CR); /* reset */ 76 77 uwr(0x7BF, UART_IPR); /* stale timeout = 630 * bitrate */ 78 uwr(0, UART_IMR); 79 uwr(115, UART_RFWR); /* RX watermark = 58 * 2 - 1 */ 80 uwr(10, UART_TFWR); /* TX watermark */ 81 82 uwr(0, UART_RFWR); 83 84 uwr(UART_CSR_115200, UART_CSR); 85 uwr(0, UART_IRDA); 86 uwr(0x1E, UART_HCR); 87 // uwr(0x7F4, UART_MR1); /* RFS/ CTS/ 500chr RFR */ 88 uwr(16, UART_MR1); 89 uwr(0x34, UART_MR2); /* 8N1 */ 90 91 mdelay(100); 92 93 uwr(0x05, UART_CR); /* enable TX & RX */ 94 mdelay(100); 95 #endif 96 } 97 98 int uart_getc(void) 99 { 100 if(!(urd(UART_SR) & UART_SR_RX_READY)) 101 return -1; 102 return urd(UART_RF); 103 } 104 105 void uart_putc(unsigned c) 106 { 107 while(!(urd(UART_SR) & UART_SR_TX_READY)) ; 108 uwr(c, UART_TF); 109 } 110 111 int uart_tx_ready(void) 112 { 113 return urd(UART_SR) & UART_SR_TX_READY; 114 } 115 116 117 void uart_puts(const char *s) 118 { 119 while(*s) { 120 if(*s == '\n') uart_putc('\r'); 121 uart_putc(*s++); 122 } 123 } 124 125
