1 /* 2 * Copyright (C) 2008 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 /* 17 * 32-bit x86 definitions and declarations. 18 */ 19 20 /* 21 386 ABI general notes: 22 23 Caller save set: 24 eax, edx, ecx, st(0)-st(7) 25 Callee save set: 26 ebx, esi, edi, ebp 27 Return regs: 28 32-bit in eax 29 64-bit in edx:eax (low-order 32 in eax) 30 fp on top of fp stack st(0) 31 32 Parameters passed on stack, pushed right-to-left. On entry to target, first 33 parm is at 4(%esp). Traditional entry code is: 34 35 functEntry: 36 push %ebp # save old frame pointer 37 mov %ebp,%esp # establish new frame pointer 38 sub FrameSize,%esp # Allocate storage for spill, locals & outs 39 40 Once past the prologue, arguments are referenced at ((argno + 2)*4)(%ebp) 41 42 Stack must be 16-byte aligned to support SSE in native code. 43 44 If we're not doing variable stack allocation (alloca), the frame pointer can be 45 eliminated and all arg references adjusted to be esp relative. 46 47 Mterp notes: 48 49 Some key interpreter variables will be assigned to registers. Note that each 50 will also have an associated spill location (mostly useful for those assigned 51 to callee save registers). 52 53 nick reg purpose 54 rPC edi interpreted program counter, used for fetching instructions 55 rFP esi interpreted frame pointer, used for accessing locals and args 56 rINSTw bx first 16-bit code of current instruction 57 rINSTbl bl opcode portion of instruction word 58 rINSTbh bh high byte of inst word, usually contains src/tgt reg names 59 rIBASE edx base of instruction handler table 60 61 Notes: 62 o High order 16 bits of ebx must be zero on entry to handler 63 o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit 64 o eax and ecx are scratch, rINSTw/ebx sometimes scratch 65 66 */ 67 68 #define rSELF 8(%ebp) 69 #define rPC %esi 70 #define rFP %edi 71 #define rINST %ebx 72 #define rINSTw %bx 73 #define rINSTbh %bh 74 #define rINSTbl %bl 75 #define rIBASE %edx 76 77 78 /* Frame diagram while executing dvmMterpStdRun, high to low addresses */ 79 #define IN_ARG0 ( 8) 80 #define CALLER_RP ( 4) 81 #define PREV_FP ( 0) 82 /* Spill offsets relative to %ebp */ 83 #define EDI_SPILL ( -4) 84 #define ESI_SPILL ( -8) 85 #define EBX_SPILL (-12) 86 #define rPC_SPILL (-16) 87 #define rFP_SPILL (-20) 88 #define rINST_SPILL (-24) 89 #define rIBASE_SPILL (-28) 90 #define TMP_SPILL1 (-32) 91 #define TMP_SPILL2 (-36) 92 #define TMP_SPILL3 (-20) 93 #define LOCAL0_OFFSET (-44) 94 #define LOCAL1_OFFSET (-48) 95 #define LOCAL2_OFFSET (-52) 96 /* Out Arg offsets, relative to %esp */ 97 #define OUT_ARG4 ( 16) 98 #define OUT_ARG3 ( 12) 99 #define OUT_ARG2 ( 8) 100 #define OUT_ARG1 ( 4) 101 #define OUT_ARG0 ( 0) /* <- dvmMterpStdRun esp */ 102 #define FRAME_SIZE 76 103 104 #define SPILL(reg) movl reg##,reg##_SPILL(%ebp) 105 #define UNSPILL(reg) movl reg##_SPILL(%ebp),reg 106 #define SPILL_TMP1(reg) movl reg,TMP_SPILL1(%ebp) 107 #define UNSPILL_TMP1(reg) movl TMP_SPILL1(%ebp),reg 108 #define SPILL_TMP2(reg) movl reg,TMP_SPILL2(%ebp) 109 #define UNSPILL_TMP2(reg) movl TMP_SPILL2(%ebp),reg 110 #define SPILL_TMP3(reg) movl reg,TMP_SPILL3(%ebp) 111 #define UNSPILL_TMP3(reg) movl TMP_SPILL3(%ebp),reg 112 113 #if defined(WITH_JIT) 114 .macro GET_JIT_PROF_TABLE _self _reg 115 movl offThread_pJitProfTable(\_self),\_reg 116 .endm 117 .macro GET_JIT_THRESHOLD _self _reg 118 movl offThread_jitThreshold(\_self),\_reg 119 .endm 120 #endif 121 122 /* save/restore the PC and/or FP from the self struct */ 123 .macro SAVE_PC_FP_TO_SELF _reg 124 movl rSELF,\_reg 125 movl rPC,offThread_pc(\_reg) 126 movl rFP,offThread_curFrame(\_reg) 127 .endm 128 129 .macro LOAD_PC_FP_FROM_SELF 130 movl rSELF,rFP 131 movl offThread_pc(rFP),rPC 132 movl offThread_curFrame(rFP),rFP 133 .endm 134 135 /* The interpreter assumes a properly aligned stack on entry, and 136 * will preserve 16-byte alignment. 137 */ 138 139 /* 140 * "export" the PC to the interpreted stack frame, f/b/o future exception 141 * objects. Must be done *before* something throws. 142 * 143 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 144 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 145 * 146 * It's okay to do this more than once. 147 */ 148 .macro EXPORT_PC 149 movl rPC, (-sizeofStackSaveArea + offStackSaveArea_currentPc)(rFP) 150 .endm 151 152 /* 153 * Given a frame pointer, find the stack save area. 154 * 155 * In C this is "((StackSaveArea*)(_fp) -1)". 156 */ 157 .macro SAVEAREA_FROM_FP _reg 158 leal -sizeofStackSaveArea(rFP), \_reg 159 .endm 160 161 /* 162 * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. 163 */ 164 .macro FETCH_INST 165 movzwl (rPC),rINST 166 .endm 167 168 /* 169 * Fetch the opcode byte and zero-extend it into _reg. Must be used 170 * in conjunction with GOTO_NEXT_R 171 */ 172 .macro FETCH_INST_R _reg 173 movzbl (rPC),\_reg 174 .endm 175 176 /* 177 * Fetch the opcode byte at _count words offset from rPC and zero-extend 178 * it into _reg. Must be used in conjunction with GOTO_NEXT_R 179 */ 180 .macro FETCH_INST_OPCODE _count _reg 181 movzbl \_count*2(rPC),\_reg 182 .endm 183 184 /* 185 * Fetch the nth instruction word from rPC into rINSTw. Does not advance 186 * rPC, and _count is in words 187 */ 188 .macro FETCH_INST_WORD _count 189 movzwl \_count*2(rPC),rINST 190 .endm 191 192 /* 193 * Fetch instruction word indexed (used for branching). 194 * Index is in instruction word units. 195 */ 196 .macro FETCH_INST_INDEXED _reg 197 movzwl (rPC,\_reg,2),rINST 198 .endm 199 200 /* 201 * Advance rPC by instruction count 202 */ 203 .macro ADVANCE_PC _count 204 leal 2*\_count(rPC),rPC 205 .endm 206 207 /* 208 * Advance rPC by branch offset in register 209 */ 210 .macro ADVANCE_PC_INDEXED _reg 211 leal (rPC,\_reg,2),rPC 212 .endm 213 214 .macro GOTO_NEXT 215 movzx rINSTbl,%eax 216 movzbl rINSTbh,rINST 217 jmp *(rIBASE,%eax,4) 218 .endm 219 220 /* 221 * Version of GOTO_NEXT that assumes _reg preloaded with opcode. 222 * Should be paired with FETCH_INST_R 223 */ 224 .macro GOTO_NEXT_R _reg 225 movzbl 1(rPC),rINST 226 jmp *(rIBASE,\_reg,4) 227 .endm 228 229 /* 230 * Get/set the 32-bit value from a Dalvik register. 231 */ 232 .macro GET_VREG_R _reg _vreg 233 movl (rFP,\_vreg,4),\_reg 234 .endm 235 236 .macro SET_VREG _reg _vreg 237 movl \_reg,(rFP,\_vreg,4) 238 .endm 239 240 .macro GET_VREG_WORD _reg _vreg _offset 241 movl 4*(\_offset)(rFP,\_vreg,4),\_reg 242 .endm 243 244 .macro SET_VREG_WORD _reg _vreg _offset 245 movl \_reg,4*(\_offset)(rFP,\_vreg,4) 246 .endm 247 248 #define sReg0 LOCAL0_OFFSET(%ebp) 249 #define sReg1 LOCAL1_OFFSET(%ebp) 250 #define sReg2 LOCAL2_OFFSET(%ebp) 251 252 /* 253 * Hard coded helper values. 254 */ 255 256 .balign 16 257 258 .LdoubNeg: 259 .quad 0x8000000000000000 260 261 .L64bits: 262 .quad 0xFFFFFFFFFFFFFFFF 263 264 .LshiftMask2: 265 .quad 0x0000000000000000 266 .LshiftMask: 267 .quad 0x000000000000003F 268 269 .Lvalue64: 270 .quad 0x0000000000000040 271 272 .LvaluePosInfLong: 273 .quad 0x7FFFFFFFFFFFFFFF 274 275 .LvalueNegInfLong: 276 .quad 0x8000000000000000 277 278 .LvalueNanLong: 279 .quad 0x0000000000000000 280 281 .LintMin: 282 .long 0x80000000 283 284 .LintMax: 285 .long 0x7FFFFFFF 286 287 288 /* 289 * This is a #include, not a %include, because we want the C pre-processor 290 * to expand the macros into assembler assignment statements. 291 */ 292 #include "../common/asm-constants.h" 293 294 #if defined(WITH_JIT) 295 #include "../common/jit-config.h" 296 #endif 297
