1 /************************************************************************** 2 Etherboot - BOOTP/TFTP Bootstrap Program 3 Schneider & Koch G16 NIC driver for Etherboot 4 heavily based on SK G16 driver from Linux 2.0.36 5 Changes to make it work with Etherboot by Georg Baum <Georg.Baum (at) gmx.de> 6 ***************************************************************************/ 7 8 /*- 9 * Copyright (C) 1994 by PJD Weichmann & SWS Bern, Switzerland 10 * 11 * This software may be used and distributed according to the terms 12 * of the GNU Public License, incorporated herein by reference. 13 * 14 * Module : sk_g16.c 15 * 16 * Version : $Revision: 1.4 $ 17 * 18 * Author : Patrick J.D. Weichmann 19 * 20 * Date Created : 94/05/26 21 * Last Updated : $Date: 2002/01/02 21:56:40 $ 22 * 23 * Description : Schneider & Koch G16 Ethernet Device Driver for 24 * Linux Kernel >= 1.1.22 25 * Update History : 26 * 27 -*/ 28 29 /* 30 * The Schneider & Koch (SK) G16 Network device driver is based 31 * on the 'ni6510' driver from Michael Hipp which can be found at 32 * ftp://sunsite.unc.edu/pub/Linux/system/Network/drivers/nidrivers.tar.gz 33 * 34 * Sources: 1) ni6510.c by M. Hipp 35 * 2) depca.c by D.C. Davies 36 * 3) skeleton.c by D. Becker 37 * 4) Am7990 Local Area Network Controller for Ethernet (LANCE), 38 * AMD, Pub. #05698, June 1989 39 * 40 * Many Thanks for helping me to get things working to: 41 * 42 * A. Cox (A.Cox (at) swansea.ac.uk) 43 * M. Hipp (mhipp (at) student.uni-tuebingen.de) 44 * R. Bolz (Schneider & Koch, Germany) 45 * 46 * See README.sk_g16 for details about limitations and bugs for the 47 * current version. 48 * 49 * To Do: 50 * - Support of SK_G8 and other SK Network Cards. 51 * - Autoset memory mapped RAM. Check for free memory and then 52 * configure RAM correctly. 53 * - SK_close should really set card in to initial state. 54 * - Test if IRQ 3 is not switched off. Use autoirq() functionality. 55 * (as in /drivers/net/skeleton.c) 56 * - Implement Multicast addressing. At minimum something like 57 * in depca.c. 58 * - Redo the statistics part. 59 * - Try to find out if the board is in 8 Bit or 16 Bit slot. 60 * If in 8 Bit mode don't use IRQ 11. 61 * - (Try to make it slightly faster.) 62 */ 63 64 /* to get some global routines like printf */ 65 #include "etherboot.h" 66 /* to get the interface to the body of the program */ 67 #include "nic.h" 68 69 /* From linux/if_ether.h: */ 70 #define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ 71 72 #include "sk_g16.h" 73 74 /* 75 * Schneider & Koch Card Definitions 76 * ================================= 77 */ 78 79 #define SK_NAME "SK_G16" 80 81 /* 82 * SK_G16 Configuration 83 * -------------------- 84 */ 85 86 /* 87 * Abbreviations 88 * ------------- 89 * 90 * RAM - used for the 16KB shared memory 91 * Boot_ROM, ROM - are used for referencing the BootEPROM 92 * 93 * SK_ADDR is a symbolic constant used to configure 94 * the behaviour of the driver and the SK_G16. 95 * 96 * SK_ADDR defines the address where the RAM will be mapped into the real 97 * host memory. 98 * valid addresses are from 0xa0000 to 0xfc000 in 16Kbyte steps. 99 */ 100 101 #define SK_ADDR 0xcc000 102 103 /* 104 * In POS3 are bits A14-A19 of the address bus. These bits can be set 105 * to choose the RAM address. That's why we only can choose the RAM address 106 * in 16KB steps. 107 */ 108 109 #define POS_ADDR (rom_addr>>14) /* Do not change this line */ 110 111 /* 112 * SK_G16 I/O PORT's + IRQ's + Boot_ROM locations 113 * ---------------------------------------------- 114 */ 115 116 /* 117 * As nearly every card has also SK_G16 a specified I/O Port region and 118 * only a few possible IRQ's. 119 * In the Installation Guide from Schneider & Koch is listed a possible 120 * Interrupt IRQ2. IRQ2 is always IRQ9 in boards with two cascaded interrupt 121 * controllers. So we use in SK_IRQS IRQ9. 122 */ 123 124 /* Don't touch any of the following #defines. */ 125 126 #define SK_IO_PORTS { 0x100, 0x180, 0x208, 0x220, 0x288, 0x320, 0x328, 0x390, 0 } 127 128 /* 129 * SK_G16 POS REGISTERS 130 * -------------------- 131 */ 132 133 /* 134 * SK_G16 has a Programmable Option Select (POS) Register. 135 * The POS is composed of 8 separate registers (POS0-7) which 136 * are I/O mapped on an address set by the W1 switch. 137 * 138 */ 139 140 #define SK_POS_SIZE 8 /* 8 I/O Ports are used by SK_G16 */ 141 142 #define SK_POS0 ioaddr /* Card-ID Low (R) */ 143 #define SK_POS1 ioaddr+1 /* Card-ID High (R) */ 144 #define SK_POS2 ioaddr+2 /* Card-Enable, Boot-ROM Disable (RW) */ 145 #define SK_POS3 ioaddr+3 /* Base address of RAM */ 146 #define SK_POS4 ioaddr+4 /* IRQ */ 147 148 /* POS5 - POS7 are unused */ 149 150 /* 151 * SK_G16 MAC PREFIX 152 * ----------------- 153 */ 154 155 /* 156 * Scheider & Koch manufacturer code (00:00:a5). 157 * This must be checked, that we are sure it is a SK card. 158 */ 159 160 #define SK_MAC0 0x00 161 #define SK_MAC1 0x00 162 #define SK_MAC2 0x5a 163 164 /* 165 * SK_G16 ID 166 * --------- 167 */ 168 169 /* 170 * If POS0,POS1 contain the following ID, then we know 171 * at which I/O Port Address we are. 172 */ 173 174 #define SK_IDLOW 0xfd 175 #define SK_IDHIGH 0x6a 176 177 178 /* 179 * LANCE POS Bit definitions 180 * ------------------------- 181 */ 182 183 #define SK_ROM_RAM_ON (POS2_CARD) 184 #define SK_ROM_RAM_OFF (POS2_EPROM) 185 #define SK_ROM_ON (inb(SK_POS2) & POS2_CARD) 186 #define SK_ROM_OFF (inb(SK_POS2) | POS2_EPROM) 187 #define SK_RAM_ON (inb(SK_POS2) | POS2_CARD) 188 #define SK_RAM_OFF (inb(SK_POS2) & POS2_EPROM) 189 190 #define POS2_CARD 0x0001 /* 1 = SK_G16 on 0 = off */ 191 #define POS2_EPROM 0x0002 /* 1 = Boot EPROM off 0 = on */ 192 193 /* 194 * SK_G16 Memory mapped Registers 195 * ------------------------------ 196 * 197 */ 198 199 #define SK_IOREG (board->ioreg) /* LANCE data registers. */ 200 #define SK_PORT (board->port) /* Control, Status register */ 201 #define SK_IOCOM (board->iocom) /* I/O Command */ 202 203 /* 204 * SK_G16 Status/Control Register bits 205 * ----------------------------------- 206 * 207 * (C) Controlreg (S) Statusreg 208 */ 209 210 /* 211 * Register transfer: 0 = no transfer 212 * 1 = transferring data between LANCE and I/O reg 213 */ 214 #define SK_IORUN 0x20 215 216 /* 217 * LANCE interrupt: 0 = LANCE interrupt occurred 218 * 1 = no LANCE interrupt occurred 219 */ 220 #define SK_IRQ 0x10 221 222 #define SK_RESET 0x08 /* Reset SK_CARD: 0 = RESET 1 = normal */ 223 #define SK_RW 0x02 /* 0 = write to 1 = read from */ 224 #define SK_ADR 0x01 /* 0 = REG DataPort 1 = RAP Reg addr port */ 225 226 227 #define SK_RREG SK_RW /* Transferdirection to read from lance */ 228 #define SK_WREG 0 /* Transferdirection to write to lance */ 229 #define SK_RAP SK_ADR /* Destination Register RAP */ 230 #define SK_RDATA 0 /* Destination Register REG DataPort */ 231 232 /* 233 * SK_G16 I/O Command 234 * ------------------ 235 */ 236 237 /* 238 * Any bitcombination sets the internal I/O bit (transfer will start) 239 * when written to I/O Command 240 */ 241 242 #define SK_DOIO 0x80 /* Do Transfer */ 243 244 /* 245 * LANCE RAP (Register Address Port). 246 * --------------------------------- 247 */ 248 249 /* 250 * The LANCE internal registers are selected through the RAP. 251 * The Registers are: 252 * 253 * CSR0 - Status and Control flags 254 * CSR1 - Low order bits of initialize block (bits 15:00) 255 * CSR2 - High order bits of initialize block (bits 07:00, 15:08 are reserved) 256 * CSR3 - Allows redefinition of the Bus Master Interface. 257 * This register must be set to 0x0002, which means BSWAP = 0, 258 * ACON = 1, BCON = 0; 259 * 260 */ 261 262 #define CSR0 0x00 263 #define CSR1 0x01 264 #define CSR2 0x02 265 #define CSR3 0x03 266 267 /* 268 * General Definitions 269 * =================== 270 */ 271 272 /* 273 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 274 * We have 16KB RAM which can be accessed by the LANCE. In the 275 * memory are not only the buffers but also the ring descriptors and 276 * the initialize block. 277 * Don't change anything unless you really know what you do. 278 */ 279 280 #define LC_LOG_TX_BUFFERS 1 /* (2 == 2^^1) 2 Transmit buffers */ 281 #define LC_LOG_RX_BUFFERS 2 /* (8 == 2^^3) 8 Receive buffers */ 282 283 /* Descriptor ring sizes */ 284 285 #define TMDNUM (1 << (LC_LOG_TX_BUFFERS)) /* 2 Transmit descriptor rings */ 286 #define RMDNUM (1 << (LC_LOG_RX_BUFFERS)) /* 8 Receive Buffers */ 287 288 /* Define Mask for setting RMD, TMD length in the LANCE init_block */ 289 290 #define TMDNUMMASK (LC_LOG_TX_BUFFERS << 29) 291 #define RMDNUMMASK (LC_LOG_RX_BUFFERS << 29) 292 293 /* 294 * Data Buffer size is set to maximum packet length. 295 */ 296 297 #define PKT_BUF_SZ 1518 298 299 /* 300 * The number of low I/O ports used by the ethercard. 301 */ 302 303 #define ETHERCARD_TOTAL_SIZE SK_POS_SIZE 304 305 /* 306 * Portreserve is there to mark the Card I/O Port region as used. 307 * Check_region is to check if the region at ioaddr with the size "size" 308 * is free or not. 309 * Snarf_region allocates the I/O Port region. 310 */ 311 312 #ifndef HAVE_PORTRESERVE 313 314 #define check_region(ioaddr1, size) 0 315 #define request_region(ioaddr1, size,name) do ; while (0) 316 317 #endif 318 319 /* 320 * SK_DEBUG 321 * 322 * Here you can choose what level of debugging wanted. 323 * 324 * If SK_DEBUG and SK_DEBUG2 are undefined, then only the 325 * necessary messages will be printed. 326 * 327 * If SK_DEBUG is defined, there will be many debugging prints 328 * which can help to find some mistakes in configuration or even 329 * in the driver code. 330 * 331 * If SK_DEBUG2 is defined, many many messages will be printed 332 * which normally you don't need. I used this to check the interrupt 333 * routine. 334 * 335 * (If you define only SK_DEBUG2 then only the messages for 336 * checking interrupts will be printed!) 337 * 338 * Normal way of live is: 339 * 340 * For the whole thing get going let both symbolic constants 341 * undefined. If you face any problems and you know what's going 342 * on (you know something about the card and you can interpret some 343 * hex LANCE register output) then define SK_DEBUG 344 * 345 */ 346 347 #undef SK_DEBUG /* debugging */ 348 #undef SK_DEBUG2 /* debugging with more verbose report */ 349 350 #ifdef SK_DEBUG 351 #define PRINTF(x) printf x 352 #else 353 #define PRINTF(x) /**/ 354 #endif 355 356 #ifdef SK_DEBUG2 357 #define PRINTF2(x) printf x 358 #else 359 #define PRINTF2(x) /**/ 360 #endif 361 362 /* 363 * SK_G16 RAM 364 * 365 * The components are memory mapped and can be set in a region from 366 * 0x00000 through 0xfc000 in 16KB steps. 367 * 368 * The Network components are: dual ported RAM, Prom, I/O Reg, Status-, 369 * Controlregister and I/O Command. 370 * 371 * dual ported RAM: This is the only memory region which the LANCE chip 372 * has access to. From the Lance it is addressed from 0x0000 to 373 * 0x3fbf. The host accesses it normally. 374 * 375 * PROM: The PROM obtains the ETHERNET-MAC-Address. It is realised as a 376 * 8-Bit PROM, this means only the 16 even addresses are used of the 377 * 32 Byte Address region. Access to a odd address results in invalid 378 * data. 379 * 380 * LANCE I/O Reg: The I/O Reg is build of 4 single Registers, Low-Byte Write, 381 * Hi-Byte Write, Low-Byte Read, Hi-Byte Read. 382 * Transfer from or to the LANCE is always in 16Bit so Low and High 383 * registers are always relevant. 384 * 385 * The Data from the Readregister is not the data in the Writeregister!! 386 * 387 * Port: Status- and Controlregister. 388 * Two different registers which share the same address, Status is 389 * read-only, Control is write-only. 390 * 391 * I/O Command: 392 * Any bitcombination written in here starts the transmission between 393 * Host and LANCE. 394 */ 395 396 typedef struct 397 { 398 unsigned char ram[0x3fc0]; /* 16KB dual ported ram */ 399 unsigned char rom[0x0020]; /* 32Byte PROM containing 6Byte MAC */ 400 unsigned char res1[0x0010]; /* reserved */ 401 unsigned volatile short ioreg;/* LANCE I/O Register */ 402 unsigned volatile char port; /* Statusregister and Controlregister */ 403 unsigned char iocom; /* I/O Command Register */ 404 } SK_RAM; 405 406 /* struct */ 407 408 /* 409 * This is the structure for the dual ported ram. We 410 * have exactly 16 320 Bytes. In here there must be: 411 * 412 * - Initialize Block (starting at a word boundary) 413 * - Receive and Transmit Descriptor Rings (quadword boundary) 414 * - Data Buffers (arbitrary boundary) 415 * 416 * This is because LANCE has on SK_G16 only access to the dual ported 417 * RAM and nowhere else. 418 */ 419 420 struct SK_ram 421 { 422 struct init_block ib; 423 struct tmd tmde[TMDNUM]; 424 struct rmd rmde[RMDNUM]; 425 char tmdbuf[TMDNUM][PKT_BUF_SZ]; 426 char rmdbuf[RMDNUM][PKT_BUF_SZ]; 427 }; 428 429 /* 430 * Structure where all necessary information is for ring buffer 431 * management and statistics. 432 */ 433 434 struct priv 435 { 436 struct SK_ram *ram; /* dual ported ram structure */ 437 struct rmd *rmdhead; /* start of receive ring descriptors */ 438 struct tmd *tmdhead; /* start of transmit ring descriptors */ 439 int rmdnum; /* actual used ring descriptor */ 440 int tmdnum; /* actual transmit descriptor for transmitting data */ 441 int tmdlast; /* last sent descriptor used for error handling, etc */ 442 void *rmdbufs[RMDNUM]; /* pointer to the receive buffers */ 443 void *tmdbufs[TMDNUM]; /* pointer to the transmit buffers */ 444 }; 445 446 /* global variable declaration */ 447 448 /* static variables */ 449 450 static SK_RAM *board; /* pointer to our memory mapped board components */ 451 static unsigned short ioaddr; /* base io address */ 452 static struct priv p_data; 453 454 /* Macros */ 455 456 457 /* Function Prototypes */ 458 459 /* 460 * Device Driver functions 461 * ----------------------- 462 * See for short explanation of each function its definitions header. 463 */ 464 465 static int SK_probe1(struct nic *nic, short ioaddr1); 466 467 static void SK_reset(struct nic *nic); 468 static int SK_poll(struct nic *nic); 469 static void SK_transmit( 470 struct nic *nic, 471 const char *d, /* Destination */ 472 unsigned int t, /* Type */ 473 unsigned int s, /* size */ 474 const char *p); /* Packet */ 475 static void SK_disable(struct nic *nic); 476 struct nic *SK_probe(struct nic *nic, unsigned short *probe_addrs); 477 478 /* 479 * LANCE Functions 480 * --------------- 481 */ 482 483 static int SK_lance_init(struct nic *nic, unsigned short mode); 484 static void SK_reset_board(void); 485 static void SK_set_RAP(int reg_number); 486 static int SK_read_reg(int reg_number); 487 static int SK_rread_reg(void); 488 static void SK_write_reg(int reg_number, int value); 489 490 /* 491 * Debugging functions 492 * ------------------- 493 */ 494 495 static void SK_print_pos(struct nic *nic, char *text); 496 static void SK_print_ram(struct nic *nic); 497 498 499 /************************************************************************** 500 RESET - Reset adapter 501 ***************************************************************************/ 502 static void SK_reset(struct nic *nic) 503 { 504 /* put the card in its initial state */ 505 SK_lance_init(nic, MODE_NORMAL); 506 } 507 508 /************************************************************************** 509 POLL - Wait for a frame 510 ***************************************************************************/ 511 static int SK_poll(struct nic *nic) 512 { 513 /* return true if there's an ethernet packet ready to read */ 514 struct priv *p; /* SK_G16 private structure */ 515 struct rmd *rmdp; 516 int csr0, rmdstat, packet_there; 517 PRINTF2(("## %s: At beginning of SK_poll(). CSR0: %#hX\n", 518 SK_NAME, SK_read_reg(CSR0))); 519 520 p = nic->priv_data; 521 csr0 = SK_read_reg(CSR0); /* store register for checking */ 522 523 /* 524 * Acknowledge all of the current interrupt sources, disable 525 * Interrupts (INEA = 0) 526 */ 527 528 SK_write_reg(CSR0, csr0 & CSR0_CLRALL); 529 530 if (csr0 & CSR0_ERR) /* LANCE Error */ 531 { 532 printf("%s: error: %#hX", SK_NAME, csr0); 533 534 if (csr0 & CSR0_MISS) /* No place to store packet ? */ 535 { 536 printf(", Packet dropped."); 537 } 538 putchar('\n'); 539 } 540 541 rmdp = p->rmdhead + p->rmdnum; 542 packet_there = 0; 543 /* As long as we own the next entry, check status and send 544 * it up to higher layer 545 */ 546 547 while (!( (rmdstat = rmdp->u.s.status) & RX_OWN)) 548 { 549 /* 550 * Start and end of packet must be set, because we use 551 * the ethernet maximum packet length (1518) as buffer size. 552 * 553 * Because our buffers are at maximum OFLO and BUFF errors are 554 * not to be concerned (see Data sheet) 555 */ 556 557 if ((rmdstat & (RX_STP | RX_ENP)) != (RX_STP | RX_ENP)) 558 { 559 /* Start of a frame > 1518 Bytes ? */ 560 561 if (rmdstat & RX_STP) 562 { 563 printf("%s: packet too long\n", SK_NAME); 564 } 565 566 /* 567 * All other packets will be ignored until a new frame with 568 * start (RX_STP) set follows. 569 * 570 * What we do is just give descriptor free for new incoming 571 * packets. 572 */ 573 574 rmdp->u.s.status = RX_OWN; /* Relinquish ownership to LANCE */ 575 576 } 577 else if (rmdstat & RX_ERR) /* Receive Error ? */ 578 { 579 printf("%s: RX error: %#hX\n", SK_NAME, (int) rmdstat); 580 rmdp->u.s.status = RX_OWN; /* Relinquish ownership to LANCE */ 581 } 582 else /* We have a packet which can be queued for the upper layers */ 583 { 584 585 int len = (rmdp->mlen & 0x0fff); /* extract message length from receive buffer */ 586 587 /* 588 * Copy data out of our receive descriptor into nic->packet. 589 * 590 * (rmdp->u.buffer & 0x00ffffff) -> get address of buffer and 591 * ignore status fields) 592 */ 593 594 memcpy(nic->packet, (unsigned char *) (rmdp->u.buffer & 0x00ffffff), nic->packetlen = len); 595 packet_there = 1; 596 597 598 /* 599 * Packet is queued and marked for processing so we 600 * free our descriptor 601 */ 602 603 rmdp->u.s.status = RX_OWN; 604 605 p->rmdnum++; 606 p->rmdnum %= RMDNUM; 607 608 rmdp = p->rmdhead + p->rmdnum; 609 } 610 } 611 SK_write_reg(CSR0, CSR0_INEA); /* Enable Interrupts */ 612 return (packet_there); 613 } 614 615 /************************************************************************** 616 TRANSMIT - Transmit a frame 617 ***************************************************************************/ 618 static void SK_transmit( 619 struct nic *nic, 620 const char *d, /* Destination */ 621 unsigned int t, /* Type */ 622 unsigned int s, /* size */ 623 const char *pack) /* Packet */ 624 { 625 /* send the packet to destination */ 626 struct priv *p; /* SK_G16 private structure */ 627 struct tmd *tmdp; 628 short len; 629 int csr0, i, tmdstat; 630 631 PRINTF2(("## %s: At beginning of SK_transmit(). CSR0: %#hX\n", 632 SK_NAME, SK_read_reg(CSR0))); 633 p = nic->priv_data; 634 tmdp = p->tmdhead + p->tmdnum; /* Which descriptor for transmitting */ 635 636 /* Copy data into dual ported ram */ 637 638 memcpy(&p->ram->tmdbuf[p->tmdnum][0], d, ETH_ALEN); /* dst */ 639 memcpy(&p->ram->tmdbuf[p->tmdnum][ETH_ALEN], nic->node_addr, ETH_ALEN); /* src */ 640 p->ram->tmdbuf[p->tmdnum][ETH_ALEN + ETH_ALEN] = t >> 8; /* type */ 641 p->ram->tmdbuf[p->tmdnum][ETH_ALEN + ETH_ALEN + 1] = t; /* type */ 642 memcpy(&p->ram->tmdbuf[p->tmdnum][ETH_HLEN], pack, s); 643 s += ETH_HLEN; 644 while (s < ETH_ZLEN) /* pad to min length */ 645 p->ram->tmdbuf[p->tmdnum][s++] = 0; 646 p->ram->tmde[p->tmdnum].status2 = 0x0; 647 648 /* Evaluate Packet length */ 649 len = ETH_ZLEN < s ? s : ETH_ZLEN; 650 651 /* Fill in Transmit Message Descriptor */ 652 653 tmdp->blen = -len; /* set length to transmit */ 654 655 /* 656 * Packet start and end is always set because we use the maximum 657 * packet length as buffer length. 658 * Relinquish ownership to LANCE 659 */ 660 661 tmdp->u.s.status = TX_OWN | TX_STP | TX_ENP; 662 663 /* Start Demand Transmission */ 664 SK_write_reg(CSR0, CSR0_TDMD | CSR0_INEA); 665 666 csr0 = SK_read_reg(CSR0); /* store register for checking */ 667 668 /* 669 * Acknowledge all of the current interrupt sources, disable 670 * Interrupts (INEA = 0) 671 */ 672 673 SK_write_reg(CSR0, csr0 & CSR0_CLRALL); 674 675 if (csr0 & CSR0_ERR) /* LANCE Error */ 676 { 677 printf("%s: error: %#hX", SK_NAME, csr0); 678 679 if (csr0 & CSR0_MISS) /* No place to store packet ? */ 680 { 681 printf(", Packet dropped."); 682 } 683 putchar('\n'); 684 } 685 686 687 /* Set next buffer */ 688 p->tmdlast++; 689 p->tmdlast &= TMDNUM-1; 690 691 tmdstat = tmdp->u.s.status & 0xff00; /* filter out status bits 15:08 */ 692 693 /* 694 * We check status of transmitted packet. 695 * see LANCE data-sheet for error explanation 696 */ 697 if (tmdstat & TX_ERR) /* Error occurred */ 698 { 699 printf("%s: TX error: %#hX %#hX\n", SK_NAME, (int) tmdstat, 700 (int) tmdp->status2); 701 702 if (tmdp->status2 & TX_TDR) /* TDR problems? */ 703 { 704 printf("%s: tdr-problems \n", SK_NAME); 705 } 706 707 if (tmdp->status2 & TX_UFLO) /* Underflow error ? */ 708 { 709 /* 710 * If UFLO error occurs it will turn transmitter of. 711 * So we must reinit LANCE 712 */ 713 714 SK_lance_init(nic, MODE_NORMAL); 715 } 716 717 tmdp->status2 = 0; /* Clear error flags */ 718 } 719 720 SK_write_reg(CSR0, CSR0_INEA); /* Enable Interrupts */ 721 722 /* Set pointer to next transmit buffer */ 723 p->tmdnum++; 724 p->tmdnum &= TMDNUM-1; 725 726 } 727 728 /************************************************************************** 729 DISABLE - Turn off ethernet interface 730 ***************************************************************************/ 731 static void SK_disable(struct nic *nic) 732 { 733 PRINTF(("## %s: At beginning of SK_disable(). CSR0: %#hX\n", 734 SK_NAME, SK_read_reg(CSR0))); 735 PRINTF(("%s: Shutting %s down CSR0 %#hX\n", SK_NAME, SK_NAME, 736 (int) SK_read_reg(CSR0))); 737 738 SK_write_reg(CSR0, CSR0_STOP); /* STOP the LANCE */ 739 } 740 741 /************************************************************************** 742 PROBE - Look for an adapter, this routine's visible to the outside 743 ***************************************************************************/ 744 struct nic *SK_probe(struct nic *nic, unsigned short *probe_addrs) 745 { 746 unsigned short *p; 747 static unsigned short io_addrs[] = SK_IO_PORTS; 748 /* if probe_addrs is 0, then routine can use a hardwired default */ 749 putchar('\n'); 750 nic->priv_data = &p_data; 751 if (probe_addrs == 0) 752 probe_addrs = io_addrs; 753 for (p = probe_addrs; (ioaddr = *p) != 0; ++p) 754 { 755 long offset1, offset0 = inb(ioaddr); 756 if ((offset0 == SK_IDLOW) && 757 ((offset1 = inb(ioaddr + 1)) == SK_IDHIGH)) 758 if (SK_probe1(nic, ioaddr) >= 0) 759 break; 760 } 761 /* if board found */ 762 if (ioaddr != 0) 763 { 764 /* point to NIC specific routines */ 765 nic->reset = SK_reset; 766 nic->poll = SK_poll; 767 nic->transmit = SK_transmit; 768 nic->disable = SK_disable; 769 return nic; 770 } 771 /* else */ 772 { 773 return 0; 774 } 775 } 776 777 int SK_probe1(struct nic *nic, short ioaddr1) 778 { 779 int i,j; /* Counters */ 780 int sk_addr_flag = 0; /* SK ADDR correct? 1 - no, 0 - yes */ 781 unsigned int rom_addr; /* used to store RAM address used for POS_ADDR */ 782 783 struct priv *p; /* SK_G16 private structure */ 784 785 if (SK_ADDR & 0x3fff || SK_ADDR < 0xa0000) 786 { 787 /* 788 * Now here we could use a routine which searches for a free 789 * place in the ram and set SK_ADDR if found. TODO. 790 */ 791 printf("%s: SK_ADDR %#hX is not valid. Check configuration.\n", 792 SK_NAME, SK_ADDR); 793 return -1; 794 } 795 796 rom_addr = SK_ADDR; 797 798 outb(SK_ROM_RAM_OFF, SK_POS2); /* Boot_ROM + RAM off */ 799 outb(POS_ADDR, SK_POS3); /* Set RAM address */ 800 outb(SK_ROM_RAM_ON, SK_POS2); /* RAM on, BOOT_ROM on */ 801 #ifdef SK_DEBUG 802 SK_print_pos(nic, "POS registers after ROM, RAM config"); 803 #endif 804 805 board = (SK_RAM *) rom_addr; 806 PRINTF(("adr[0]: %hX, adr[1]: %hX, adr[2]: %hX\n", 807 board->rom[0], board->rom[2], board->rom[4])); 808 809 /* Read in station address */ 810 for (i = 0, j = 0; i < ETH_ALEN; i++, j+=2) 811 { 812 *(nic->node_addr+i) = board->rom[j]; 813 } 814 815 /* Check for manufacturer code */ 816 #ifdef SK_DEBUG 817 if (!(*(nic->node_addr+0) == SK_MAC0 && 818 *(nic->node_addr+1) == SK_MAC1 && 819 *(nic->node_addr+2) == SK_MAC2) ) 820 { 821 PRINTF(("## %s: We did not find SK_G16 at RAM location.\n", 822 SK_NAME)); 823 return -1; /* NO SK_G16 found */ 824 } 825 #endif 826 827 p = nic->priv_data; 828 829 /* Initialize private structure */ 830 831 p->ram = (struct SK_ram *) rom_addr; /* Set dual ported RAM addr */ 832 p->tmdhead = &(p->ram)->tmde[0]; /* Set TMD head */ 833 p->rmdhead = &(p->ram)->rmde[0]; /* Set RMD head */ 834 835 printf("Schneider & Koch G16 at %#hX, mem at %#hX, HW addr: %!\n", 836 (unsigned int) ioaddr, (unsigned int) p->ram, nic->node_addr); 837 838 /* Initialize buffer pointers */ 839 840 for (i = 0; i < TMDNUM; i++) 841 { 842 p->tmdbufs[i] = p->ram->tmdbuf[i]; 843 } 844 845 for (i = 0; i < RMDNUM; i++) 846 { 847 p->rmdbufs[i] = p->ram->rmdbuf[i]; 848 } 849 i = 0; 850 851 if (!(i = SK_lance_init(nic, MODE_NORMAL))) /* LANCE init OK? */ 852 { 853 854 #ifdef SK_DEBUG 855 /* 856 * This debug block tries to stop LANCE, 857 * reinit LANCE with transmitter and receiver disabled, 858 * then stop again and reinit with NORMAL_MODE 859 */ 860 861 printf("## %s: After lance init. CSR0: %#hX\n", 862 SK_NAME, SK_read_reg(CSR0)); 863 SK_write_reg(CSR0, CSR0_STOP); 864 printf("## %s: LANCE stopped. CSR0: %#hX\n", 865 SK_NAME, SK_read_reg(CSR0)); 866 SK_lance_init(nic, MODE_DTX | MODE_DRX); 867 printf("## %s: Reinit with DTX + DRX off. CSR0: %#hX\n", 868 SK_NAME, SK_read_reg(CSR0)); 869 SK_write_reg(CSR0, CSR0_STOP); 870 printf("## %s: LANCE stopped. CSR0: %#hX\n", 871 SK_NAME, SK_read_reg(CSR0)); 872 SK_lance_init(nic, MODE_NORMAL); 873 printf("## %s: LANCE back to normal mode. CSR0: %#hX\n", 874 SK_NAME, SK_read_reg(CSR0)); 875 SK_print_pos(nic, "POS regs before returning OK"); 876 877 #endif /* SK_DEBUG */ 878 879 } 880 else /* LANCE init failed */ 881 { 882 883 PRINTF(("## %s: LANCE init failed: CSR0: %#hX\n", 884 SK_NAME, SK_read_reg(CSR0))); 885 return -1; 886 } 887 888 #ifdef SK_DEBUG 889 SK_print_pos(nic, "End of SK_probe1"); 890 SK_print_ram(nic); 891 #endif 892 893 return 0; /* Initialization done */ 894 895 } /* End of SK_probe1() */ 896 897 static int SK_lance_init(struct nic *nic, unsigned short mode) 898 { 899 int i; 900 struct priv *p = (struct priv *) nic->priv_data; 901 struct tmd *tmdp; 902 struct rmd *rmdp; 903 904 PRINTF(("## %s: At beginning of LANCE init. CSR0: %#hX\n", 905 SK_NAME, SK_read_reg(CSR0))); 906 907 /* Reset LANCE */ 908 SK_reset_board(); 909 910 /* Initialize TMD's with start values */ 911 p->tmdnum = 0; /* First descriptor for transmitting */ 912 p->tmdlast = 0; /* First descriptor for reading stats */ 913 914 for (i = 0; i < TMDNUM; i++) /* Init all TMD's */ 915 { 916 tmdp = p->tmdhead + i; 917 918 tmdp->u.buffer = (unsigned long) p->tmdbufs[i]; /* assign buffer */ 919 920 /* Mark TMD as start and end of packet */ 921 tmdp->u.s.status = TX_STP | TX_ENP; 922 } 923 924 925 /* Initialize RMD's with start values */ 926 927 p->rmdnum = 0; /* First RMD which will be used */ 928 929 for (i = 0; i < RMDNUM; i++) /* Init all RMD's */ 930 { 931 rmdp = p->rmdhead + i; 932 933 934 rmdp->u.buffer = (unsigned long) p->rmdbufs[i]; /* assign buffer */ 935 936 /* 937 * LANCE must be owner at beginning so that he can fill in 938 * receiving packets, set status and release RMD 939 */ 940 941 rmdp->u.s.status = RX_OWN; 942 943 rmdp->blen = -PKT_BUF_SZ; /* Buffer Size in a two's complement */ 944 945 rmdp->mlen = 0; /* init message length */ 946 947 } 948 949 /* Fill LANCE Initialize Block */ 950 951 (p->ram)->ib.mode = mode; /* Set operation mode */ 952 953 for (i = 0; i < ETH_ALEN; i++) /* Set physical address */ 954 { 955 (p->ram)->ib.paddr[i] = *(nic->node_addr+i); 956 } 957 958 for (i = 0; i < 8; i++) /* Set multicast, logical address */ 959 { 960 (p->ram)->ib.laddr[i] = 0; /* We do not use logical addressing */ 961 } 962 963 /* Set ring descriptor pointers and set number of descriptors */ 964 965 (p->ram)->ib.rdrp = (int) p->rmdhead | RMDNUMMASK; 966 (p->ram)->ib.tdrp = (int) p->tmdhead | TMDNUMMASK; 967 968 /* Prepare LANCE Control and Status Registers */ 969 970 SK_write_reg(CSR3, CSR3_ACON); /* Ale Control !!!THIS MUST BE SET!!!! */ 971 972 /* 973 * LANCE addresses the RAM from 0x0000 to 0x3fbf and has no access to 974 * PC Memory locations. 975 * 976 * In structure SK_ram is defined that the first thing in ram 977 * is the initialization block. So his address is for LANCE always 978 * 0x0000 979 * 980 * CSR1 contains low order bits 15:0 of initialization block address 981 * CSR2 is built of: 982 * 7:0 High order bits 23:16 of initialization block address 983 * 15:8 reserved, must be 0 984 */ 985 986 /* Set initialization block address (must be on word boundary) */ 987 SK_write_reg(CSR1, 0); /* Set low order bits 15:0 */ 988 SK_write_reg(CSR2, 0); /* Set high order bits 23:16 */ 989 990 991 PRINTF(("## %s: After setting CSR1-3. CSR0: %#hX\n", 992 SK_NAME, SK_read_reg(CSR0))); 993 994 /* Initialize LANCE */ 995 996 /* 997 * INIT = Initialize, when set, causes the LANCE to begin the 998 * initialization procedure and access the Init Block. 999 */ 1000 1001 SK_write_reg(CSR0, CSR0_INIT); 1002 1003 /* Wait until LANCE finished initialization */ 1004 1005 SK_set_RAP(CSR0); /* Register Address Pointer to CSR0 */ 1006 1007 for (i = 0; (i < 100) && !(SK_rread_reg() & CSR0_IDON); i++) 1008 ; /* Wait until init done or go ahead if problems (i>=100) */ 1009 1010 if (i >= 100) /* Something is wrong ! */ 1011 { 1012 printf("%s: can't init am7990, status: %#hX " 1013 "init_block: %#hX\n", 1014 SK_NAME, (int) SK_read_reg(CSR0), 1015 (unsigned int) &(p->ram)->ib); 1016 1017 #ifdef SK_DEBUG 1018 SK_print_pos(nic, "LANCE INIT failed"); 1019 #endif 1020 1021 return -1; /* LANCE init failed */ 1022 } 1023 1024 PRINTF(("## %s: init done after %d ticks\n", SK_NAME, i)); 1025 1026 /* Clear Initialize done, enable Interrupts, start LANCE */ 1027 1028 SK_write_reg(CSR0, CSR0_IDON | CSR0_INEA | CSR0_STRT); 1029 1030 PRINTF(("## %s: LANCE started. CSR0: %#hX\n", SK_NAME, 1031 SK_read_reg(CSR0))); 1032 1033 return 0; /* LANCE is up and running */ 1034 1035 } /* End of SK_lance_init() */ 1036 1037 /* LANCE access functions 1038 * 1039 * ! CSR1-3 can only be accessed when in CSR0 the STOP bit is set ! 1040 */ 1041 1042 static void SK_reset_board(void) 1043 { 1044 int i; 1045 1046 PRINTF(("## %s: At beginning of SK_reset_board.\n", SK_NAME)); 1047 SK_PORT = 0x00; /* Reset active */ 1048 for (i = 0; i < 10 ; i++) /* Delay min 5ms */ 1049 ; 1050 SK_PORT = SK_RESET; /* Set back to normal operation */ 1051 1052 } /* End of SK_reset_board() */ 1053 1054 static void SK_set_RAP(int reg_number) 1055 { 1056 SK_IOREG = reg_number; 1057 SK_PORT = SK_RESET | SK_RAP | SK_WREG; 1058 SK_IOCOM = SK_DOIO; 1059 1060 while (SK_PORT & SK_IORUN) 1061 ; 1062 } /* End of SK_set_RAP() */ 1063 1064 static int SK_read_reg(int reg_number) 1065 { 1066 SK_set_RAP(reg_number); 1067 1068 SK_PORT = SK_RESET | SK_RDATA | SK_RREG; 1069 SK_IOCOM = SK_DOIO; 1070 1071 while (SK_PORT & SK_IORUN) 1072 ; 1073 return (SK_IOREG); 1074 1075 } /* End of SK_read_reg() */ 1076 1077 static int SK_rread_reg(void) 1078 { 1079 SK_PORT = SK_RESET | SK_RDATA | SK_RREG; 1080 1081 SK_IOCOM = SK_DOIO; 1082 1083 while (SK_PORT & SK_IORUN) 1084 ; 1085 return (SK_IOREG); 1086 1087 } /* End of SK_rread_reg() */ 1088 1089 static void SK_write_reg(int reg_number, int value) 1090 { 1091 SK_set_RAP(reg_number); 1092 1093 SK_IOREG = value; 1094 SK_PORT = SK_RESET | SK_RDATA | SK_WREG; 1095 SK_IOCOM = SK_DOIO; 1096 1097 while (SK_PORT & SK_IORUN) 1098 ; 1099 } /* End of SK_write_reg */ 1100 1101 /* 1102 * Debugging functions 1103 * ------------------- 1104 */ 1105 1106 #ifdef SK_DEBUG 1107 static void SK_print_pos(struct nic *nic, char *text) 1108 { 1109 1110 unsigned char pos0 = inb(SK_POS0), 1111 pos1 = inb(SK_POS1), 1112 pos2 = inb(SK_POS2), 1113 pos3 = inb(SK_POS3), 1114 pos4 = inb(SK_POS4); 1115 1116 1117 printf("## %s: %s.\n" 1118 "## pos0=%#hX pos1=%#hX pos2=%#hX pos3=%#hX pos4=%#hX\n", 1119 SK_NAME, text, pos0, pos1, pos2, (pos3<<14), pos4); 1120 1121 } /* End of SK_print_pos() */ 1122 1123 static void SK_print_ram(struct nic *nic) 1124 { 1125 1126 int i; 1127 struct priv *p = (struct priv *) nic->priv_data; 1128 1129 printf("## %s: RAM Details.\n" 1130 "## RAM at %#hX tmdhead: %#hX rmdhead: %#hX initblock: %#hX\n", 1131 SK_NAME, 1132 (unsigned int) p->ram, 1133 (unsigned int) p->tmdhead, 1134 (unsigned int) p->rmdhead, 1135 (unsigned int) &(p->ram)->ib); 1136 1137 printf("## "); 1138 1139 for(i = 0; i < TMDNUM; i++) 1140 { 1141 if (!(i % 3)) /* Every third line do a newline */ 1142 { 1143 printf("\n## "); 1144 } 1145 printf("tmdbufs%d: %#hX ", (i+1), (int) p->tmdbufs[i]); 1146 } 1147 printf("## "); 1148 1149 for(i = 0; i < RMDNUM; i++) 1150 { 1151 if (!(i % 3)) /* Every third line do a newline */ 1152 { 1153 printf("\n## "); 1154 } 1155 printf("rmdbufs%d: %#hX ", (i+1), (int) p->rmdbufs[i]); 1156 } 1157 putchar('\n'); 1158 1159 } /* End of SK_print_ram() */ 1160 #endif 1161
