1 /*- 2 * 3 * This software may be used and distributed according to the terms 4 * of the GNU Public License, incorporated herein by reference. 5 * 6 * Module : sk_g16.h 7 * Version : $Revision: 1.3 $ 8 * 9 * Author : M.Hipp (mhipp (at) student.uni-tuebingen.de) 10 * changes by : Patrick J.D. Weichmann 11 * 12 * Date Created : 94/05/25 13 * 14 * Description : In here are all necessary definitions of 15 * the am7990 (LANCE) chip used for writing a 16 * network device driver which uses this chip 17 * 18 * $Log: sk_g16.h,v $ 19 * Revision 1.3 2000/07/29 19:22:54 okuji 20 * update the network support to etherboot-4.6.4. 21 * 22 -*/ 23 24 #ifndef SK_G16_H 25 26 #define SK_G16_H 27 28 29 /* 30 * Control and Status Register 0 (CSR0) bit definitions 31 * 32 * (R=Readable) (W=Writeable) (S=Set on write) (C-Clear on write) 33 * 34 */ 35 36 #define CSR0_ERR 0x8000 /* Error summary (R) */ 37 #define CSR0_BABL 0x4000 /* Babble transmitter timeout error (RC) */ 38 #define CSR0_CERR 0x2000 /* Collision Error (RC) */ 39 #define CSR0_MISS 0x1000 /* Missed packet (RC) */ 40 #define CSR0_MERR 0x0800 /* Memory Error (RC) */ 41 #define CSR0_RINT 0x0400 /* Receiver Interrupt (RC) */ 42 #define CSR0_TINT 0x0200 /* Transmit Interrupt (RC) */ 43 #define CSR0_IDON 0x0100 /* Initialization Done (RC) */ 44 #define CSR0_INTR 0x0080 /* Interrupt Flag (R) */ 45 #define CSR0_INEA 0x0040 /* Interrupt Enable (RW) */ 46 #define CSR0_RXON 0x0020 /* Receiver on (R) */ 47 #define CSR0_TXON 0x0010 /* Transmitter on (R) */ 48 #define CSR0_TDMD 0x0008 /* Transmit Demand (RS) */ 49 #define CSR0_STOP 0x0004 /* Stop (RS) */ 50 #define CSR0_STRT 0x0002 /* Start (RS) */ 51 #define CSR0_INIT 0x0001 /* Initialize (RS) */ 52 53 #define CSR0_CLRALL 0x7f00 /* mask for all clearable bits */ 54 55 /* 56 * Control and Status Register 3 (CSR3) bit definitions 57 * 58 */ 59 60 #define CSR3_BSWAP 0x0004 /* Byte Swap (RW) */ 61 #define CSR3_ACON 0x0002 /* ALE Control (RW) */ 62 #define CSR3_BCON 0x0001 /* Byte Control (RW) */ 63 64 /* 65 * Initialization Block Mode operation Bit Definitions. 66 */ 67 68 #define MODE_PROM 0x8000 /* Promiscuous Mode */ 69 #define MODE_INTL 0x0040 /* Internal Loopback */ 70 #define MODE_DRTY 0x0020 /* Disable Retry */ 71 #define MODE_COLL 0x0010 /* Force Collision */ 72 #define MODE_DTCR 0x0008 /* Disable Transmit CRC) */ 73 #define MODE_LOOP 0x0004 /* Loopback */ 74 #define MODE_DTX 0x0002 /* Disable the Transmitter */ 75 #define MODE_DRX 0x0001 /* Disable the Receiver */ 76 77 #define MODE_NORMAL 0x0000 /* Normal operation mode */ 78 79 /* 80 * Receive message descriptor status bit definitions. 81 */ 82 83 #define RX_OWN 0x80 /* Owner bit 0 = host, 1 = lance */ 84 #define RX_ERR 0x40 /* Error Summary */ 85 #define RX_FRAM 0x20 /* Framing Error */ 86 #define RX_OFLO 0x10 /* Overflow Error */ 87 #define RX_CRC 0x08 /* CRC Error */ 88 #define RX_BUFF 0x04 /* Buffer Error */ 89 #define RX_STP 0x02 /* Start of Packet */ 90 #define RX_ENP 0x01 /* End of Packet */ 91 92 93 /* 94 * Transmit message descriptor status bit definitions. 95 */ 96 97 #define TX_OWN 0x80 /* Owner bit 0 = host, 1 = lance */ 98 #define TX_ERR 0x40 /* Error Summary */ 99 #define TX_MORE 0x10 /* More the 1 retry needed to Xmit */ 100 #define TX_ONE 0x08 /* One retry needed to Xmit */ 101 #define TX_DEF 0x04 /* Deferred */ 102 #define TX_STP 0x02 /* Start of Packet */ 103 #define TX_ENP 0x01 /* End of Packet */ 104 105 /* 106 * Transmit status (2) (valid if TX_ERR == 1) 107 */ 108 109 #define TX_BUFF 0x8000 /* Buffering error (no ENP) */ 110 #define TX_UFLO 0x4000 /* Underflow (late memory) */ 111 #define TX_LCOL 0x1000 /* Late collision */ 112 #define TX_LCAR 0x0400 /* Loss of Carrier */ 113 #define TX_RTRY 0x0200 /* Failed after 16 retransmissions */ 114 #define TX_TDR 0x003f /* Time-domain-reflectometer-value */ 115 116 117 /* 118 * Structures used for Communication with the LANCE 119 */ 120 121 /* LANCE Initialize Block */ 122 123 struct init_block 124 { 125 unsigned short mode; /* Mode Register */ 126 unsigned char paddr[6]; /* Physical Address (MAC) */ 127 unsigned char laddr[8]; /* Logical Filter Address (not used) */ 128 unsigned int rdrp; /* Receive Descriptor Ring pointer */ 129 unsigned int tdrp; /* Transmit Descriptor Ring pointer */ 130 }; 131 132 133 /* Receive Message Descriptor Entry */ 134 135 struct rmd 136 { 137 union rmd_u 138 { 139 unsigned long buffer; /* Address of buffer */ 140 struct rmd_s 141 { 142 unsigned char unused[3]; 143 unsigned volatile char status; /* Status Bits */ 144 } s; 145 } u; 146 volatile short blen; /* Buffer Length (two's complement) */ 147 unsigned short mlen; /* Message Byte Count */ 148 }; 149 150 151 /* Transmit Message Descriptor Entry */ 152 153 struct tmd 154 { 155 union tmd_u 156 { 157 unsigned long buffer; /* Address of buffer */ 158 struct tmd_s 159 { 160 unsigned char unused[3]; 161 unsigned volatile char status; /* Status Bits */ 162 } s; 163 } u; 164 unsigned short blen; /* Buffer Length (two's complement) */ 165 unsigned volatile short status2; /* Error Status Bits */ 166 }; 167 168 #endif /* End of SK_G16_H */ 169
