1 /* 2 * include/asm-i386/processor.h 3 * 4 * Copyright (C) 1994 Linus Torvalds 5 */ 6 7 #ifndef __ASM_I386_PROCESSOR_H 8 #define __ASM_I386_PROCESSOR_H 9 10 #include <asm/vm86.h> 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/page.h> 14 #include <asm/types.h> 15 #include <asm/sigcontext.h> 16 #include <asm/cpufeature.h> 17 #include <asm/msr.h> 18 #include <asm/system.h> 19 #include <linux/cache.h> 20 #include <linux/threads.h> 21 #include <asm/percpu.h> 22 #include <linux/cpumask.h> 23 #include <linux/init.h> 24 #include <asm/processor-flags.h> 25 26 /* flag for disabling the tsc */ 27 extern int tsc_disable; 28 29 struct desc_struct { 30 unsigned long a,b; 31 }; 32 33 #define desc_empty(desc) \ 34 (!((desc)->a | (desc)->b)) 35 36 #define desc_equal(desc1, desc2) \ 37 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b)) 38 /* 39 * Default implementation of macro that returns current 40 * instruction pointer ("program counter"). 41 */ 42 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; }) 43 44 /* 45 * CPU type and hardware bug flags. Kept separately for each CPU. 46 * Members of this structure are referenced in head.S, so think twice 47 * before touching them. [mj] 48 */ 49 50 struct cpuinfo_x86 { 51 __u8 x86; /* CPU family */ 52 __u8 x86_vendor; /* CPU vendor */ 53 __u8 x86_model; 54 __u8 x86_mask; 55 char wp_works_ok; /* It doesn't on 386's */ 56 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */ 57 char hard_math; 58 char rfu; 59 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */ 60 unsigned long x86_capability[NCAPINTS]; 61 char x86_vendor_id[16]; 62 char x86_model_id[64]; 63 int x86_cache_size; /* in KB - valid for CPUS which support this 64 call */ 65 int x86_cache_alignment; /* In bytes */ 66 char fdiv_bug; 67 char f00f_bug; 68 char coma_bug; 69 char pad0; 70 int x86_power; 71 unsigned long loops_per_jiffy; 72 #ifdef CONFIG_SMP 73 cpumask_t llc_shared_map; /* cpus sharing the last level cache */ 74 #endif 75 unsigned char x86_max_cores; /* cpuid returned max cores value */ 76 unsigned char apicid; 77 unsigned short x86_clflush_size; 78 #ifdef CONFIG_SMP 79 unsigned char booted_cores; /* number of cores as seen by OS */ 80 __u8 phys_proc_id; /* Physical processor id. */ 81 __u8 cpu_core_id; /* Core id */ 82 __u8 cpu_index; /* index into per_cpu list */ 83 #endif 84 } __attribute__((__aligned__(SMP_CACHE_BYTES))); 85 86 #define X86_VENDOR_INTEL 0 87 #define X86_VENDOR_CYRIX 1 88 #define X86_VENDOR_AMD 2 89 #define X86_VENDOR_UMC 3 90 #define X86_VENDOR_NEXGEN 4 91 #define X86_VENDOR_CENTAUR 5 92 #define X86_VENDOR_TRANSMETA 7 93 #define X86_VENDOR_NSC 8 94 #define X86_VENDOR_NUM 9 95 #define X86_VENDOR_UNKNOWN 0xff 96 97 /* 98 * capabilities of CPUs 99 */ 100 101 extern struct cpuinfo_x86 boot_cpu_data; 102 extern struct cpuinfo_x86 new_cpu_data; 103 extern struct tss_struct doublefault_tss; 104 DECLARE_PER_CPU(struct tss_struct, init_tss); 105 106 #ifdef CONFIG_SMP 107 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info); 108 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 109 #define current_cpu_data cpu_data(smp_processor_id()) 110 #else 111 #define cpu_data(cpu) boot_cpu_data 112 #define current_cpu_data boot_cpu_data 113 #endif 114 115 /* 116 * the following now lives in the per cpu area: 117 * extern int cpu_llc_id[NR_CPUS]; 118 */ 119 DECLARE_PER_CPU(u8, cpu_llc_id); 120 extern char ignore_fpu_irq; 121 122 void __init cpu_detect(struct cpuinfo_x86 *c); 123 124 extern void identify_boot_cpu(void); 125 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 126 extern void print_cpu_info(struct cpuinfo_x86 *); 127 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 128 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 129 extern unsigned short num_cache_leaves; 130 131 #ifdef CONFIG_X86_HT 132 extern void detect_ht(struct cpuinfo_x86 *c); 133 #else 134 static inline void detect_ht(struct cpuinfo_x86 *c) {} 135 #endif 136 137 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 138 unsigned int *ecx, unsigned int *edx) 139 { 140 /* ecx is often an input as well as an output. */ 141 __asm__("cpuid" 142 : "=a" (*eax), 143 "=b" (*ebx), 144 "=c" (*ecx), 145 "=d" (*edx) 146 : "0" (*eax), "2" (*ecx)); 147 } 148 149 #define load_cr3(pgdir) write_cr3(__pa(pgdir)) 150 151 /* 152 * Save the cr4 feature set we're using (ie 153 * Pentium 4MB enable and PPro Global page 154 * enable), so that any CPU's that boot up 155 * after us can get the correct flags. 156 */ 157 extern unsigned long mmu_cr4_features; 158 159 static inline void set_in_cr4 (unsigned long mask) 160 { 161 unsigned cr4; 162 mmu_cr4_features |= mask; 163 cr4 = read_cr4(); 164 cr4 |= mask; 165 write_cr4(cr4); 166 } 167 168 static inline void clear_in_cr4 (unsigned long mask) 169 { 170 unsigned cr4; 171 mmu_cr4_features &= ~mask; 172 cr4 = read_cr4(); 173 cr4 &= ~mask; 174 write_cr4(cr4); 175 } 176 177 /* Stop speculative execution */ 178 static inline void sync_core(void) 179 { 180 int tmp; 181 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory"); 182 } 183 184 static inline void __monitor(const void *eax, unsigned long ecx, 185 unsigned long edx) 186 { 187 /* "monitor %eax,%ecx,%edx;" */ 188 asm volatile( 189 ".byte 0x0f,0x01,0xc8;" 190 : :"a" (eax), "c" (ecx), "d"(edx)); 191 } 192 193 static inline void __mwait(unsigned long eax, unsigned long ecx) 194 { 195 /* "mwait %eax,%ecx;" */ 196 asm volatile( 197 ".byte 0x0f,0x01,0xc9;" 198 : :"a" (eax), "c" (ecx)); 199 } 200 201 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx); 202 203 /* from system description table in BIOS. Mostly for MCA use, but 204 others may find it useful. */ 205 extern unsigned int machine_id; 206 extern unsigned int machine_submodel_id; 207 extern unsigned int BIOS_revision; 208 extern unsigned int mca_pentium_flag; 209 210 /* Boot loader type from the setup header */ 211 extern int bootloader_type; 212 213 /* 214 * User space process size: 3GB (default). 215 */ 216 #define TASK_SIZE (PAGE_OFFSET) 217 218 /* This decides where the kernel will search for a free chunk of vm 219 * space during mmap's. 220 */ 221 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 222 223 #define HAVE_ARCH_PICK_MMAP_LAYOUT 224 225 extern void hard_disable_TSC(void); 226 extern void disable_TSC(void); 227 extern void hard_enable_TSC(void); 228 229 /* 230 * Size of io_bitmap. 231 */ 232 #define IO_BITMAP_BITS 65536 233 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 234 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 235 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap) 236 #define INVALID_IO_BITMAP_OFFSET 0x8000 237 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000 238 239 struct i387_fsave_struct { 240 long cwd; 241 long swd; 242 long twd; 243 long fip; 244 long fcs; 245 long foo; 246 long fos; 247 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */ 248 long status; /* software status information */ 249 }; 250 251 struct i387_fxsave_struct { 252 unsigned short cwd; 253 unsigned short swd; 254 unsigned short twd; 255 unsigned short fop; 256 long fip; 257 long fcs; 258 long foo; 259 long fos; 260 long mxcsr; 261 long mxcsr_mask; 262 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ 263 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ 264 long padding[56]; 265 } __attribute__ ((aligned (16))); 266 267 struct i387_soft_struct { 268 long cwd; 269 long swd; 270 long twd; 271 long fip; 272 long fcs; 273 long foo; 274 long fos; 275 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */ 276 unsigned char ftop, changed, lookahead, no_update, rm, alimit; 277 struct info *info; 278 unsigned long entry_eip; 279 }; 280 281 union i387_union { 282 struct i387_fsave_struct fsave; 283 struct i387_fxsave_struct fxsave; 284 struct i387_soft_struct soft; 285 }; 286 287 typedef struct { 288 unsigned long seg; 289 } mm_segment_t; 290 291 struct thread_struct; 292 293 /* This is the TSS defined by the hardware. */ 294 struct i386_hw_tss { 295 unsigned short back_link,__blh; 296 unsigned long esp0; 297 unsigned short ss0,__ss0h; 298 unsigned long esp1; 299 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */ 300 unsigned long esp2; 301 unsigned short ss2,__ss2h; 302 unsigned long __cr3; 303 unsigned long eip; 304 unsigned long eflags; 305 unsigned long eax,ecx,edx,ebx; 306 unsigned long esp; 307 unsigned long ebp; 308 unsigned long esi; 309 unsigned long edi; 310 unsigned short es, __esh; 311 unsigned short cs, __csh; 312 unsigned short ss, __ssh; 313 unsigned short ds, __dsh; 314 unsigned short fs, __fsh; 315 unsigned short gs, __gsh; 316 unsigned short ldt, __ldth; 317 unsigned short trace, io_bitmap_base; 318 } __attribute__((packed)); 319 320 struct tss_struct { 321 struct i386_hw_tss x86_tss; 322 323 /* 324 * The extra 1 is there because the CPU will access an 325 * additional byte beyond the end of the IO permission 326 * bitmap. The extra byte must be all 1 bits, and must 327 * be within the limit. 328 */ 329 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 330 /* 331 * Cache the current maximum and the last task that used the bitmap: 332 */ 333 unsigned long io_bitmap_max; 334 struct thread_struct *io_bitmap_owner; 335 /* 336 * pads the TSS to be cacheline-aligned (size is 0x100) 337 */ 338 unsigned long __cacheline_filler[35]; 339 /* 340 * .. and then another 0x100 bytes for emergency kernel stack 341 */ 342 unsigned long stack[64]; 343 } __attribute__((packed)); 344 345 #define ARCH_MIN_TASKALIGN 16 346 347 struct thread_struct { 348 /* cached TLS descriptors. */ 349 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 350 unsigned long esp0; 351 unsigned long sysenter_cs; 352 unsigned long eip; 353 unsigned long esp; 354 unsigned long fs; 355 unsigned long gs; 356 /* Hardware debugging registers */ 357 unsigned long debugreg[8]; /* %%db0-7 debug registers */ 358 /* fault info */ 359 unsigned long cr2, trap_no, error_code; 360 /* floating point info */ 361 union i387_union i387; 362 /* virtual 86 mode info */ 363 struct vm86_struct __user * vm86_info; 364 unsigned long screen_bitmap; 365 unsigned long v86flags, v86mask, saved_esp0; 366 unsigned int saved_fs, saved_gs; 367 /* IO permissions */ 368 unsigned long *io_bitmap_ptr; 369 unsigned long iopl; 370 /* max allowed port in the bitmap, in bytes: */ 371 unsigned long io_bitmap_max; 372 }; 373 374 #define INIT_THREAD { \ 375 .esp0 = sizeof(init_stack) + (long)&init_stack, \ 376 .vm86_info = NULL, \ 377 .sysenter_cs = __KERNEL_CS, \ 378 .io_bitmap_ptr = NULL, \ 379 .fs = __KERNEL_PERCPU, \ 380 } 381 382 /* 383 * Note that the .io_bitmap member must be extra-big. This is because 384 * the CPU will access an additional byte beyond the end of the IO 385 * permission bitmap. The extra byte must be all 1 bits, and must 386 * be within the limit. 387 */ 388 #define INIT_TSS { \ 389 .x86_tss = { \ 390 .esp0 = sizeof(init_stack) + (long)&init_stack, \ 391 .ss0 = __KERNEL_DS, \ 392 .ss1 = __KERNEL_CS, \ 393 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ 394 }, \ 395 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \ 396 } 397 398 #define start_thread(regs, new_eip, new_esp) do { \ 399 __asm__("movl %0,%%gs": :"r" (0)); \ 400 regs->xfs = 0; \ 401 set_fs(USER_DS); \ 402 regs->xds = __USER_DS; \ 403 regs->xes = __USER_DS; \ 404 regs->xss = __USER_DS; \ 405 regs->xcs = __USER_CS; \ 406 regs->eip = new_eip; \ 407 regs->esp = new_esp; \ 408 } while (0) 409 410 /* Forward declaration, a strange C thing */ 411 struct task_struct; 412 struct mm_struct; 413 414 /* Free all resources held by a thread. */ 415 extern void release_thread(struct task_struct *); 416 417 /* Prepare to copy thread state - unlazy all lazy status */ 418 extern void prepare_to_copy(struct task_struct *tsk); 419 420 /* 421 * create a kernel thread without removing it from tasklists 422 */ 423 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); 424 425 extern unsigned long thread_saved_pc(struct task_struct *tsk); 426 void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack); 427 428 unsigned long get_wchan(struct task_struct *p); 429 430 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) 431 #define KSTK_TOP(info) \ 432 ({ \ 433 unsigned long *__ptr = (unsigned long *)(info); \ 434 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ 435 }) 436 437 /* 438 * The below -8 is to reserve 8 bytes on top of the ring0 stack. 439 * This is necessary to guarantee that the entire "struct pt_regs" 440 * is accessable even if the CPU haven't stored the SS/ESP registers 441 * on the stack (interrupt gate does not save these registers 442 * when switching to the same priv ring). 443 * Therefore beware: accessing the xss/esp fields of the 444 * "struct pt_regs" is possible, but they may contain the 445 * completely wrong values. 446 */ 447 #define task_pt_regs(task) \ 448 ({ \ 449 struct pt_regs *__regs__; \ 450 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ 451 __regs__ - 1; \ 452 }) 453 454 #define KSTK_EIP(task) (task_pt_regs(task)->eip) 455 #define KSTK_ESP(task) (task_pt_regs(task)->esp) 456 457 458 struct microcode_header { 459 unsigned int hdrver; 460 unsigned int rev; 461 unsigned int date; 462 unsigned int sig; 463 unsigned int cksum; 464 unsigned int ldrver; 465 unsigned int pf; 466 unsigned int datasize; 467 unsigned int totalsize; 468 unsigned int reserved[3]; 469 }; 470 471 struct microcode { 472 struct microcode_header hdr; 473 unsigned int bits[0]; 474 }; 475 476 typedef struct microcode microcode_t; 477 typedef struct microcode_header microcode_header_t; 478 479 /* microcode format is extended from prescott processors */ 480 struct extended_signature { 481 unsigned int sig; 482 unsigned int pf; 483 unsigned int cksum; 484 }; 485 486 struct extended_sigtable { 487 unsigned int count; 488 unsigned int cksum; 489 unsigned int reserved[3]; 490 struct extended_signature sigs[0]; 491 }; 492 493 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 494 static inline void rep_nop(void) 495 { 496 __asm__ __volatile__("rep;nop": : :"memory"); 497 } 498 499 #define cpu_relax() rep_nop() 500 501 static inline void native_load_esp0(struct tss_struct *tss, struct thread_struct *thread) 502 { 503 tss->x86_tss.esp0 = thread->esp0; 504 /* This can only happen when SEP is enabled, no need to test "SEP"arately */ 505 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 506 tss->x86_tss.ss1 = thread->sysenter_cs; 507 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 508 } 509 } 510 511 512 static inline unsigned long native_get_debugreg(int regno) 513 { 514 unsigned long val = 0; /* Damn you, gcc! */ 515 516 switch (regno) { 517 case 0: 518 asm("movl %%db0, %0" :"=r" (val)); break; 519 case 1: 520 asm("movl %%db1, %0" :"=r" (val)); break; 521 case 2: 522 asm("movl %%db2, %0" :"=r" (val)); break; 523 case 3: 524 asm("movl %%db3, %0" :"=r" (val)); break; 525 case 6: 526 asm("movl %%db6, %0" :"=r" (val)); break; 527 case 7: 528 asm("movl %%db7, %0" :"=r" (val)); break; 529 default: 530 BUG(); 531 } 532 return val; 533 } 534 535 static inline void native_set_debugreg(int regno, unsigned long value) 536 { 537 switch (regno) { 538 case 0: 539 asm("movl %0,%%db0" : /* no output */ :"r" (value)); 540 break; 541 case 1: 542 asm("movl %0,%%db1" : /* no output */ :"r" (value)); 543 break; 544 case 2: 545 asm("movl %0,%%db2" : /* no output */ :"r" (value)); 546 break; 547 case 3: 548 asm("movl %0,%%db3" : /* no output */ :"r" (value)); 549 break; 550 case 6: 551 asm("movl %0,%%db6" : /* no output */ :"r" (value)); 552 break; 553 case 7: 554 asm("movl %0,%%db7" : /* no output */ :"r" (value)); 555 break; 556 default: 557 BUG(); 558 } 559 } 560 561 /* 562 * Set IOPL bits in EFLAGS from given mask 563 */ 564 static inline void native_set_iopl_mask(unsigned mask) 565 { 566 unsigned int reg; 567 __asm__ __volatile__ ("pushfl;" 568 "popl %0;" 569 "andl %1, %0;" 570 "orl %2, %0;" 571 "pushl %0;" 572 "popfl" 573 : "=&r" (reg) 574 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 575 } 576 577 #ifdef CONFIG_PARAVIRT 578 #include <asm/paravirt.h> 579 #else 580 #define paravirt_enabled() 0 581 #define __cpuid native_cpuid 582 583 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread) 584 { 585 native_load_esp0(tss, thread); 586 } 587 588 /* 589 * These special macros can be used to get or set a debugging register 590 */ 591 #define get_debugreg(var, register) \ 592 (var) = native_get_debugreg(register) 593 #define set_debugreg(value, register) \ 594 native_set_debugreg(register, value) 595 596 #define set_iopl_mask native_set_iopl_mask 597 #endif /* CONFIG_PARAVIRT */ 598 599 /* 600 * Generic CPUID function 601 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 602 * resulting in stale register contents being returned. 603 */ 604 static inline void cpuid(unsigned int op, 605 unsigned int *eax, unsigned int *ebx, 606 unsigned int *ecx, unsigned int *edx) 607 { 608 *eax = op; 609 *ecx = 0; 610 __cpuid(eax, ebx, ecx, edx); 611 } 612 613 /* Some CPUID calls want 'count' to be placed in ecx */ 614 static inline void cpuid_count(unsigned int op, int count, 615 unsigned int *eax, unsigned int *ebx, 616 unsigned int *ecx, unsigned int *edx) 617 { 618 *eax = op; 619 *ecx = count; 620 __cpuid(eax, ebx, ecx, edx); 621 } 622 623 /* 624 * CPUID functions returning a single datum 625 */ 626 static inline unsigned int cpuid_eax(unsigned int op) 627 { 628 unsigned int eax, ebx, ecx, edx; 629 630 cpuid(op, &eax, &ebx, &ecx, &edx); 631 return eax; 632 } 633 static inline unsigned int cpuid_ebx(unsigned int op) 634 { 635 unsigned int eax, ebx, ecx, edx; 636 637 cpuid(op, &eax, &ebx, &ecx, &edx); 638 return ebx; 639 } 640 static inline unsigned int cpuid_ecx(unsigned int op) 641 { 642 unsigned int eax, ebx, ecx, edx; 643 644 cpuid(op, &eax, &ebx, &ecx, &edx); 645 return ecx; 646 } 647 static inline unsigned int cpuid_edx(unsigned int op) 648 { 649 unsigned int eax, ebx, ecx, edx; 650 651 cpuid(op, &eax, &ebx, &ecx, &edx); 652 return edx; 653 } 654 655 /* generic versions from gas */ 656 #define GENERIC_NOP1 ".byte 0x90\n" 657 #define GENERIC_NOP2 ".byte 0x89,0xf6\n" 658 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n" 659 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n" 660 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4 661 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n" 662 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n" 663 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7 664 665 /* Opteron nops */ 666 #define K8_NOP1 GENERIC_NOP1 667 #define K8_NOP2 ".byte 0x66,0x90\n" 668 #define K8_NOP3 ".byte 0x66,0x66,0x90\n" 669 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n" 670 #define K8_NOP5 K8_NOP3 K8_NOP2 671 #define K8_NOP6 K8_NOP3 K8_NOP3 672 #define K8_NOP7 K8_NOP4 K8_NOP3 673 #define K8_NOP8 K8_NOP4 K8_NOP4 674 675 /* K7 nops */ 676 /* uses eax dependencies (arbitary choice) */ 677 #define K7_NOP1 GENERIC_NOP1 678 #define K7_NOP2 ".byte 0x8b,0xc0\n" 679 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n" 680 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n" 681 #define K7_NOP5 K7_NOP4 ASM_NOP1 682 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n" 683 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n" 684 #define K7_NOP8 K7_NOP7 ASM_NOP1 685 686 /* P6 nops */ 687 /* uses eax dependencies (Intel-recommended choice) */ 688 #define P6_NOP1 GENERIC_NOP1 689 #define P6_NOP2 ".byte 0x66,0x90\n" 690 #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n" 691 #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n" 692 #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n" 693 #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n" 694 #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n" 695 #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n" 696 697 #ifdef CONFIG_MK8 698 #define ASM_NOP1 K8_NOP1 699 #define ASM_NOP2 K8_NOP2 700 #define ASM_NOP3 K8_NOP3 701 #define ASM_NOP4 K8_NOP4 702 #define ASM_NOP5 K8_NOP5 703 #define ASM_NOP6 K8_NOP6 704 #define ASM_NOP7 K8_NOP7 705 #define ASM_NOP8 K8_NOP8 706 #elif defined(CONFIG_MK7) 707 #define ASM_NOP1 K7_NOP1 708 #define ASM_NOP2 K7_NOP2 709 #define ASM_NOP3 K7_NOP3 710 #define ASM_NOP4 K7_NOP4 711 #define ASM_NOP5 K7_NOP5 712 #define ASM_NOP6 K7_NOP6 713 #define ASM_NOP7 K7_NOP7 714 #define ASM_NOP8 K7_NOP8 715 #elif defined(CONFIG_M686) || defined(CONFIG_MPENTIUMII) || \ 716 defined(CONFIG_MPENTIUMIII) || defined(CONFIG_MPENTIUMM) || \ 717 defined(CONFIG_MCORE2) || defined(CONFIG_PENTIUM4) 718 #define ASM_NOP1 P6_NOP1 719 #define ASM_NOP2 P6_NOP2 720 #define ASM_NOP3 P6_NOP3 721 #define ASM_NOP4 P6_NOP4 722 #define ASM_NOP5 P6_NOP5 723 #define ASM_NOP6 P6_NOP6 724 #define ASM_NOP7 P6_NOP7 725 #define ASM_NOP8 P6_NOP8 726 #else 727 #define ASM_NOP1 GENERIC_NOP1 728 #define ASM_NOP2 GENERIC_NOP2 729 #define ASM_NOP3 GENERIC_NOP3 730 #define ASM_NOP4 GENERIC_NOP4 731 #define ASM_NOP5 GENERIC_NOP5 732 #define ASM_NOP6 GENERIC_NOP6 733 #define ASM_NOP7 GENERIC_NOP7 734 #define ASM_NOP8 GENERIC_NOP8 735 #endif 736 737 #define ASM_NOP_MAX 8 738 739 /* Prefetch instructions for Pentium III and AMD Athlon */ 740 /* It's not worth to care about 3dnow! prefetches for the K6 741 because they are microcoded there and very slow. 742 However we don't do prefetches for pre XP Athlons currently 743 That should be fixed. */ 744 #define ARCH_HAS_PREFETCH 745 static inline void prefetch(const void *x) 746 { 747 alternative_input(ASM_NOP4, 748 "prefetchnta (%1)", 749 X86_FEATURE_XMM, 750 "r" (x)); 751 } 752 753 #define ARCH_HAS_PREFETCH 754 #define ARCH_HAS_PREFETCHW 755 #define ARCH_HAS_SPINLOCK_PREFETCH 756 757 /* 3dnow! prefetch to get an exclusive cache line. Useful for 758 spinlocks to avoid one state transition in the cache coherency protocol. */ 759 static inline void prefetchw(const void *x) 760 { 761 alternative_input(ASM_NOP4, 762 "prefetchw (%1)", 763 X86_FEATURE_3DNOW, 764 "r" (x)); 765 } 766 #define spin_lock_prefetch(x) prefetchw(x) 767 768 extern void select_idle_routine(const struct cpuinfo_x86 *c); 769 770 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 771 772 extern unsigned long boot_option_idle_override; 773 extern void enable_sep_cpu(void); 774 extern int sysenter_setup(void); 775 776 /* Defined in head.S */ 777 extern struct Xgt_desc_struct early_gdt_descr; 778 779 extern void cpu_set_gdt(int); 780 extern void switch_to_new_gdt(void); 781 extern void cpu_init(void); 782 extern void init_gdt(int cpu); 783 784 extern int force_mwait; 785 786 #endif /* __ASM_I386_PROCESSOR_H */ 787
