1 //===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the RegAllocBase class, which is the skeleton of a basic 11 // register allocation algorithm and interface for extending it. It provides the 12 // building blocks on which to construct other experimental allocators and test 13 // the validity of two principles: 14 // 15 // - If virtual and physical register liveness is modeled using intervals, then 16 // on-the-fly interference checking is cheap. Furthermore, interferences can be 17 // lazily cached and reused. 18 // 19 // - Register allocation complexity, and generated code performance is 20 // determined by the effectiveness of live range splitting rather than optimal 21 // coloring. 22 // 23 // Following the first principle, interfering checking revolves around the 24 // LiveIntervalUnion data structure. 25 // 26 // To fulfill the second principle, the basic allocator provides a driver for 27 // incremental splitting. It essentially punts on the problem of register 28 // coloring, instead driving the assignment of virtual to physical registers by 29 // the cost of splitting. The basic allocator allows for heuristic reassignment 30 // of registers, if a more sophisticated allocator chooses to do that. 31 // 32 // This framework provides a way to engineer the compile time vs. code 33 // quality trade-off without relying on a particular theoretical solver. 34 // 35 //===----------------------------------------------------------------------===// 36 37 #ifndef LLVM_CODEGEN_REGALLOCBASE 38 #define LLVM_CODEGEN_REGALLOCBASE 39 40 #include "llvm/ADT/OwningPtr.h" 41 #include "LiveIntervalUnion.h" 42 #include "RegisterClassInfo.h" 43 44 namespace llvm { 45 46 template<typename T> class SmallVectorImpl; 47 class TargetRegisterInfo; 48 class VirtRegMap; 49 class LiveIntervals; 50 class Spiller; 51 52 /// RegAllocBase provides the register allocation driver and interface that can 53 /// be extended to add interesting heuristics. 54 /// 55 /// Register allocators must override the selectOrSplit() method to implement 56 /// live range splitting. They must also override enqueue/dequeue to provide an 57 /// assignment order. 58 class RegAllocBase { 59 LiveIntervalUnion::Allocator UnionAllocator; 60 61 // Cache tag for PhysReg2LiveUnion entries. Increment whenever virtual 62 // registers may have changed. 63 unsigned UserTag; 64 65 // Array of LiveIntervalUnions indexed by physical register. 66 class LiveUnionArray { 67 unsigned NumRegs; 68 LiveIntervalUnion *Array; 69 public: 70 LiveUnionArray(): NumRegs(0), Array(0) {} 71 ~LiveUnionArray() { clear(); } 72 73 unsigned numRegs() const { return NumRegs; } 74 75 void init(LiveIntervalUnion::Allocator &, unsigned NRegs); 76 77 void clear(); 78 79 LiveIntervalUnion& operator[](unsigned PhysReg) { 80 assert(PhysReg < NumRegs && "physReg out of bounds"); 81 return Array[PhysReg]; 82 } 83 }; 84 85 LiveUnionArray PhysReg2LiveUnion; 86 87 // Current queries, one per physreg. They must be reinitialized each time we 88 // query on a new live virtual register. 89 OwningArrayPtr<LiveIntervalUnion::Query> Queries; 90 91 protected: 92 const TargetRegisterInfo *TRI; 93 MachineRegisterInfo *MRI; 94 VirtRegMap *VRM; 95 LiveIntervals *LIS; 96 RegisterClassInfo RegClassInfo; 97 98 RegAllocBase(): UserTag(0), TRI(0), MRI(0), VRM(0), LIS(0) {} 99 100 virtual ~RegAllocBase() {} 101 102 // A RegAlloc pass should call this before allocatePhysRegs. 103 void init(VirtRegMap &vrm, LiveIntervals &lis); 104 105 // Get an initialized query to check interferences between lvr and preg. Note 106 // that Query::init must be called at least once for each physical register 107 // before querying a new live virtual register. This ties Queries and 108 // PhysReg2LiveUnion together. 109 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) { 110 Queries[PhysReg].init(UserTag, &VirtReg, &PhysReg2LiveUnion[PhysReg]); 111 return Queries[PhysReg]; 112 } 113 114 // Get direct access to the underlying LiveIntervalUnion for PhysReg. 115 LiveIntervalUnion &getLiveUnion(unsigned PhysReg) { 116 return PhysReg2LiveUnion[PhysReg]; 117 } 118 119 // Invalidate all cached information about virtual registers - live ranges may 120 // have changed. 121 void invalidateVirtRegs() { ++UserTag; } 122 123 // The top-level driver. The output is a VirtRegMap that us updated with 124 // physical register assignments. 125 void allocatePhysRegs(); 126 127 // Get a temporary reference to a Spiller instance. 128 virtual Spiller &spiller() = 0; 129 130 /// enqueue - Add VirtReg to the priority queue of unassigned registers. 131 virtual void enqueue(LiveInterval *LI) = 0; 132 133 /// dequeue - Return the next unassigned register, or NULL. 134 virtual LiveInterval *dequeue() = 0; 135 136 // A RegAlloc pass should override this to provide the allocation heuristics. 137 // Each call must guarantee forward progess by returning an available PhysReg 138 // or new set of split live virtual registers. It is up to the splitter to 139 // converge quickly toward fully spilled live ranges. 140 virtual unsigned selectOrSplit(LiveInterval &VirtReg, 141 SmallVectorImpl<LiveInterval*> &splitLVRs) = 0; 142 143 // A RegAlloc pass should call this when PassManager releases its memory. 144 virtual void releaseMemory(); 145 146 // Helper for checking interference between a live virtual register and a 147 // physical register, including all its register aliases. If an interference 148 // exists, return the interfering register, which may be preg or an alias. 149 unsigned checkPhysRegInterference(LiveInterval& VirtReg, unsigned PhysReg); 150 151 /// assign - Assign VirtReg to PhysReg. 152 /// This should not be called from selectOrSplit for the current register. 153 void assign(LiveInterval &VirtReg, unsigned PhysReg); 154 155 /// unassign - Undo a previous assignment of VirtReg to PhysReg. 156 /// This can be invoked from selectOrSplit, but be careful to guarantee that 157 /// allocation is making progress. 158 void unassign(LiveInterval &VirtReg, unsigned PhysReg); 159 160 /// addMBBLiveIns - Add physreg liveins to basic blocks. 161 void addMBBLiveIns(MachineFunction *); 162 163 #ifndef NDEBUG 164 // Verify each LiveIntervalUnion. 165 void verify(); 166 #endif 167 168 // Use this group name for NamedRegionTimer. 169 static const char *TimerGroupName; 170 171 public: 172 /// VerifyEnabled - True when -verify-regalloc is given. 173 static bool VerifyEnabled; 174 175 private: 176 void seedLiveRegs(); 177 }; 178 179 } // end namespace llvm 180 181 #endif // !defined(LLVM_CODEGEN_REGALLOCBASE) 182
