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      1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // Implements the info about Hexagon target spec.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "HexagonTargetMachine.h"
     15 #include "Hexagon.h"
     16 #include "HexagonISelLowering.h"
     17 #include "llvm/Module.h"
     18 #include "llvm/CodeGen/Passes.h"
     19 #include "llvm/PassManager.h"
     20 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
     21 #include "llvm/Transforms/Scalar.h"
     22 #include "llvm/Support/CommandLine.h"
     23 #include "llvm/Support/TargetRegistry.h"
     24 
     25 using namespace llvm;
     26 
     27 static cl::
     28 opt<bool> DisableHardwareLoops(
     29                         "disable-hexagon-hwloops", cl::Hidden,
     30                         cl::desc("Disable Hardware Loops for Hexagon target"));
     31 
     32 /// HexagonTargetMachineModule - Note that this is used on hosts that
     33 /// cannot link in a library unless there are references into the
     34 /// library.  In particular, it seems that it is not possible to get
     35 /// things to work on Win32 without this.  Though it is unused, do not
     36 /// remove it.
     37 extern "C" int HexagonTargetMachineModule;
     38 int HexagonTargetMachineModule = 0;
     39 
     40 extern "C" void LLVMInitializeHexagonTarget() {
     41   // Register the target.
     42   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
     43 }
     44 
     45 
     46 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
     47 ///
     48 
     49 /// Hexagon_TODO: Do I need an aggregate alignment?
     50 ///
     51 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
     52                                            StringRef CPU, StringRef FS,
     53                                            const TargetOptions &Options,
     54                                            Reloc::Model RM,
     55                                            CodeModel::Model CM,
     56                                            CodeGenOpt::Level OL)
     57   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
     58     DataLayout("e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-a0:0") ,
     59     Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
     60     TSInfo(*this),
     61     FrameLowering(Subtarget),
     62     InstrItins(&Subtarget.getInstrItineraryData()) {
     63   setMCUseCFI(false);
     64 }
     65 
     66 // addPassesForOptimizations - Allow the backend (target) to add Target
     67 // Independent Optimization passes to the Pass Manager.
     68 bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
     69 
     70   PM.add(createConstantPropagationPass());
     71   PM.add(createLoopSimplifyPass());
     72   PM.add(createDeadCodeEliminationPass());
     73   PM.add(createConstantPropagationPass());
     74   PM.add(createLoopUnrollPass());
     75   PM.add(createLoopStrengthReducePass(getTargetLowering()));
     76   return true;
     77 }
     78 
     79 namespace {
     80 /// Hexagon Code Generator Pass Configuration Options.
     81 class HexagonPassConfig : public TargetPassConfig {
     82 public:
     83   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
     84     : TargetPassConfig(TM, PM) {}
     85 
     86   HexagonTargetMachine &getHexagonTargetMachine() const {
     87     return getTM<HexagonTargetMachine>();
     88   }
     89 
     90   virtual bool addInstSelector();
     91   virtual bool addPreRegAlloc();
     92   virtual bool addPostRegAlloc();
     93   virtual bool addPreSched2();
     94   virtual bool addPreEmitPass();
     95 };
     96 } // namespace
     97 
     98 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
     99   return new HexagonPassConfig(this, PM);
    100 }
    101 
    102 bool HexagonPassConfig::addInstSelector() {
    103   PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
    104   PM.add(createHexagonISelDag(getHexagonTargetMachine()));
    105   PM.add(createHexagonPeephole());
    106   return false;
    107 }
    108 
    109 
    110 bool HexagonPassConfig::addPreRegAlloc() {
    111   if (!DisableHardwareLoops) {
    112     PM.add(createHexagonHardwareLoops());
    113   }
    114 
    115   return false;
    116 }
    117 
    118 bool HexagonPassConfig::addPostRegAlloc() {
    119   PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
    120   return true;
    121 }
    122 
    123 
    124 bool HexagonPassConfig::addPreSched2() {
    125   addPass(IfConverterID);
    126   return true;
    127 }
    128 
    129 bool HexagonPassConfig::addPreEmitPass() {
    130 
    131   if (!DisableHardwareLoops) {
    132     PM.add(createHexagonFixupHwLoops());
    133   }
    134 
    135   // Expand Spill code for predicate registers.
    136   PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
    137 
    138   // Split up TFRcondsets into conditional transfers.
    139   PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
    140 
    141   return false;
    142 }
    143