1 //===-- MBlazeSchedule3.td - MBlaze Scheduling Definitions -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // MBlaze instruction itineraries for the three stage pipeline. 12 //===----------------------------------------------------------------------===// 13 def MBlazePipe3Itineraries : ProcessorItineraries< 14 [IF,ID,EX], [], [ 15 16 // ALU instruction with one destination register and either two register 17 // source operands or one register source operand and one immediate operand. 18 // The instruction takes one cycle to execute in each of the stages. The 19 // two source operands are read during the decode stage and the result is 20 // ready after the execute stage. 21 InstrItinData< IIC_ALU, 22 [ InstrStage<1,[IF]> // one cycle in fetch stage 23 , InstrStage<1,[ID]> // one cycle in decode stage 24 , InstrStage<1,[EX]>], // one cycle in execute stage 25 [ 2 // result ready after two cycles 26 , 1 // first operand read after one cycle 27 , 1 ]>, // second operand read after one cycle 28 29 // ALU multiply instruction with one destination register and either two 30 // register source operands or one register source operand and one immediate 31 // operand. The instruction takes one cycle to execute in each of the 32 // pipeline stages except the execute stage, which takes three cycles. The 33 // two source operands are read during the decode stage and the result is 34 // ready after the execute stage. 35 InstrItinData< IIC_ALUm, 36 [ InstrStage<1,[IF]> // one cycle in fetch stage 37 , InstrStage<1,[ID]> // one cycle in decode stage 38 , InstrStage<3,[EX]>], // three cycles in execute stage 39 [ 4 // result ready after four cycles 40 , 1 // first operand read after one cycle 41 , 1 ]>, // second operand read after one cycle 42 43 // ALU divide instruction with one destination register two register source 44 // operands. The instruction takes one cycle to execute in each the pipeline 45 // stages except the execute stage, which takes 34 cycles. The two 46 // source operands are read during the decode stage and the result is ready 47 // after the execute stage. 48 InstrItinData< IIC_ALUd, 49 [ InstrStage<1,[IF]> // one cycle in fetch stage 50 , InstrStage<1,[ID]> // one cycle in decode stage 51 , InstrStage<34,[EX]>], // 34 cycles in execute stage 52 [ 35 // result ready after 35 cycles 53 , 1 // first operand read after one cycle 54 , 1 ]>, // second operand read after one cycle 55 56 // Shift instruction with one destination register and either two register 57 // source operands or one register source operand and one immediate operand. 58 // The instruction takes one cycle to execute in each of the pipeline stages 59 // except the execute stage, which takes two cycles. The two source operands 60 // are read during the decode stage and the result is ready after the execute 61 // stage. 62 InstrItinData< IIC_SHT, 63 [ InstrStage<1,[IF]> // one cycle in fetch stage 64 , InstrStage<1,[ID]> // one cycle in decode stage 65 , InstrStage<2,[EX]>], // two cycles in execute stage 66 [ 3 // result ready after three cycles 67 , 1 // first operand read after one cycle 68 , 1 ]>, // second operand read after one cycle 69 70 // Branch instruction with one source operand register. The instruction takes 71 // one cycle to execute in each of the pipeline stages. The source operand is 72 // read during the decode stage. 73 InstrItinData< IIC_BR, 74 [ InstrStage<1,[IF]> // one cycle in fetch stage 75 , InstrStage<1,[ID]> // one cycle in decode stage 76 , InstrStage<1,[EX]>], // one cycle in execute stage 77 [ 1 ]>, // first operand read after one cycle 78 79 // Conditional branch instruction with two source operand registers. The 80 // instruction takes one cycle to execute in each of the pipeline stages. The 81 // two source operands are read during the decode stage. 82 InstrItinData< IIC_BRc, 83 [ InstrStage<1,[IF]> // one cycle in fetch stage 84 , InstrStage<1,[ID]> // one cycle in decode stage 85 , InstrStage<1,[EX]>], // one cycle in execute stage 86 [ 1 // first operand read after one cycle 87 , 1 ]>, // second operand read after one cycle 88 89 // Branch and link instruction with one destination register and one source 90 // operand register. The instruction takes one cycle to execute in each of 91 // the pipeline stages. The source operand is read during the decode stage 92 // and the destination register is ready after the execute stage. 93 InstrItinData< IIC_BRl, 94 [ InstrStage<1,[IF]> // one cycle in fetch stage 95 , InstrStage<1,[ID]> // one cycle in decode stage 96 , InstrStage<1,[EX]>], // one cycle in execute stage 97 [ 2 // result ready after two cycles 98 , 1 ]>, // first operand read after one cycle 99 100 // Cache control instruction with two source operand registers. The 101 // instruction takes one cycle to execute in each of the pipeline stages 102 // except the memory access stage, which takes two cycles. The source 103 // operands are read during the decode stage. 104 InstrItinData< IIC_WDC, 105 [ InstrStage<1,[IF]> // one cycle in fetch stage 106 , InstrStage<1,[ID]> // one cycle in decode stage 107 , InstrStage<2,[EX]>], // two cycles in execute stage 108 [ 1 // first operand read after one cycle 109 , 1 ]>, // second operand read after one cycle 110 111 // Floating point instruction with one destination register and two source 112 // operand registers. The instruction takes one cycle to execute in each of 113 // the pipeline stages except the execute stage, which takes six cycles. The 114 // source operands are read during the decode stage and the results are ready 115 // after the execute stage. 116 InstrItinData< IIC_FPU, 117 [ InstrStage<1,[IF]> // one cycle in fetch stage 118 , InstrStage<1,[ID]> // one cycle in decode stage 119 , InstrStage<6,[EX]>], // six cycles in execute stage 120 [ 7 // result ready after seven cycles 121 , 1 // first operand read after one cycle 122 , 1 ]>, // second operand read after one cycle 123 124 // Floating point divide instruction with one destination register and two 125 // source operand registers. The instruction takes one cycle to execute in 126 // each of the pipeline stages except the execute stage, which takes 30 127 // cycles. The source operands are read during the decode stage and the 128 // results are ready after the execute stage. 129 InstrItinData< IIC_FPUd, 130 [ InstrStage<1,[IF]> // one cycle in fetch stage 131 , InstrStage<1,[ID]> // one cycle in decode stage 132 , InstrStage<30,[EX]>], // one cycle in execute stage 133 [ 31 // result ready after 31 cycles 134 , 1 // first operand read after one cycle 135 , 1 ]>, // second operand read after one cycle 136 137 // Convert floating point to integer instruction with one destination 138 // register and one source operand register. The instruction takes one cycle 139 // to execute in each of the pipeline stages except the execute stage, 140 // which takes seven cycles. The source operands are read during the decode 141 // stage and the results are ready after the execute stage. 142 InstrItinData< IIC_FPUi, 143 [ InstrStage<1,[IF]> // one cycle in fetch stage 144 , InstrStage<1,[ID]> // one cycle in decode stage 145 , InstrStage<7,[EX]>], // seven cycles in execute stage 146 [ 8 // result ready after eight cycles 147 , 1 ]>, // first operand read after one cycle 148 149 // Convert integer to floating point instruction with one destination 150 // register and one source operand register. The instruction takes one cycle 151 // to execute in each of the pipeline stages except the execute stage, 152 // which takes six cycles. The source operands are read during the decode 153 // stage and the results are ready after the execute stage. 154 InstrItinData< IIC_FPUf, 155 [ InstrStage<1,[IF]> // one cycle in fetch stage 156 , InstrStage<1,[ID]> // one cycle in decode stage 157 , InstrStage<6,[EX]>], // six cycles in execute stage 158 [ 7 // result ready after seven cycles 159 , 1 ]>, // first operand read after one cycle 160 161 // Floating point square root instruction with one destination register and 162 // one source operand register. The instruction takes one cycle to execute in 163 // each of the pipeline stages except the execute stage, which takes 29 164 // cycles. The source operands are read during the decode stage and the 165 // results are ready after the execute stage. 166 InstrItinData< IIC_FPUs, 167 [ InstrStage<1,[IF]> // one cycle in fetch stage 168 , InstrStage<1,[ID]> // one cycle in decode stage 169 , InstrStage<29,[EX]>], // 29 cycles in execute stage 170 [ 30 // result ready after 30 cycles 171 , 1 ]>, // first operand read after one cycle 172 173 // Floating point comparison instruction with one destination register and 174 // two source operand registers. The instruction takes one cycle to execute 175 // in each of the pipeline stages except the execute stage, which takes three 176 // cycles. The source operands are read during the decode stage and the 177 // results are ready after the execute stage. 178 InstrItinData< IIC_FPUc, 179 [ InstrStage<1,[IF]> // one cycle in fetch stage 180 , InstrStage<1,[ID]> // one cycle in decode stage 181 , InstrStage<3,[EX]>], // three cycles in execute stage 182 [ 4 // result ready after four cycles 183 , 1 // first operand read after one cycle 184 , 1 ]>, // second operand read after one cycle 185 186 // FSL get instruction with one register or immediate source operand and one 187 // destination register. The instruction takes one cycle to execute in each 188 // of the pipeline stages except the execute stage, which takes two cycles. 189 // The one source operand is read during the decode stage and the result is 190 // ready after the execute stage. 191 InstrItinData< IIC_FSLg, 192 [ InstrStage<1,[IF]> // one cycle in fetch stage 193 , InstrStage<1,[ID]> // one cycle in decode stage 194 , InstrStage<2,[EX]>], // two cycles in execute stage 195 [ 3 // result ready after two cycles 196 , 1 ]>, // first operand read after one cycle 197 198 // FSL put instruction with either two register source operands or one 199 // register source operand and one immediate operand. There is no result 200 // produced by the instruction. The instruction takes one cycle to execute in 201 // each of the pipeline stages except the execute stage, which takes two 202 // cycles. The two source operands are read during the decode stage. 203 InstrItinData< IIC_FSLp, 204 [ InstrStage<1,[IF]> // one cycle in fetch stage 205 , InstrStage<1,[ID]> // one cycle in decode stage 206 , InstrStage<2,[EX]>], // two cycles in execute stage 207 [ 1 // first operand read after one cycle 208 , 1 ]>, // second operand read after one cycle 209 210 // Memory store instruction with either three register source operands or two 211 // register source operands and one immediate operand. There is no result 212 // produced by the instruction. The instruction takes one cycle to execute in 213 // each of the pipeline stages except the execute stage, which takes two 214 // cycles. All of the source operands are read during the decode stage. 215 InstrItinData< IIC_MEMs, 216 [ InstrStage<1,[IF]> // one cycle in fetch stage 217 , InstrStage<1,[ID]> // one cycle in decode stage 218 , InstrStage<2,[EX]>], // two cycles in execute stage 219 [ 1 // first operand read after one cycle 220 , 1 // second operand read after one cycle 221 , 1 ]>, // third operand read after one cycle 222 223 // Memory load instruction with one destination register and either two 224 // register source operands or one register source operand and one immediate 225 // operand. The instruction takes one cycle to execute in each of the 226 // pipeline stages except the execute stage, which takes two cycles. All of 227 // the source operands are read during the decode stage and the result is 228 // ready after the execute stage. 229 InstrItinData< IIC_MEMl, 230 [ InstrStage<1,[IF]> // one cycle in fetch stage 231 , InstrStage<1,[ID]> // one cycle in decode stage 232 , InstrStage<2,[EX]>], // two cycles in execute stage 233 [ 3 // result ready after four cycles 234 , 1 // second operand read after one cycle 235 , 1 ]> // third operand read after one cycle 236 ]>; 237
