1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips64 instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Mips Operand, Complex Patterns and Transformations Definitions. 16 //===----------------------------------------------------------------------===// 17 18 // Instruction operand types 19 def shamt_64 : Operand<i64>; 20 21 // Unsigned Operand 22 def uimm16_64 : Operand<i64> { 23 let PrintMethod = "printUnsignedImm"; 24 } 25 26 // Transformation Function - get Imm - 32. 27 def Subtract32 : SDNodeXForm<imm, [{ 28 return getImm(N, (unsigned)N->getZExtValue() - 32); 29 }]>; 30 31 // shamt must fit in 6 bits. 32 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 33 34 //===----------------------------------------------------------------------===// 35 // Instructions specific format 36 //===----------------------------------------------------------------------===// 37 // Shifts 38 // 64-bit shift instructions. 39 let DecoderNamespace = "Mips64" in { 40 class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm, 41 SDNode OpNode>: 42 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt6, shamt, 43 CPU64Regs>; 44 45 // Mul, Div 46 class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>: 47 Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 48 class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 49 Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 50 51 multiclass Atomic2Ops64<PatFrag Op, string Opstr> { 52 def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, Requires<[NotN64]>; 53 def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, Requires<[IsN64]> { 54 let isCodeGenOnly = 1; 55 } 56 } 57 58 multiclass AtomicCmpSwap64<PatFrag Op, string Width> { 59 def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, Requires<[NotN64]>; 60 def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>, 61 Requires<[IsN64]> { 62 let isCodeGenOnly = 1; 63 } 64 } 65 } 66 let usesCustomInserter = 1, Predicates = [HasMips64], 67 DecoderNamespace = "Mips64" in { 68 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">; 69 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">; 70 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">; 71 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">; 72 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">; 73 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">; 74 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">; 75 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">; 76 } 77 78 //===----------------------------------------------------------------------===// 79 // Instruction definition 80 //===----------------------------------------------------------------------===// 81 let DecoderNamespace = "Mips64" in { 82 /// Arithmetic Instructions (ALU Immediate) 83 def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16, 84 CPU64Regs>; 85 def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>; 86 def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; 87 def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; 88 def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>; 89 def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>; 90 def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; 91 92 /// Arithmetic Instructions (3-Operand, R-Type) 93 def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>; 94 def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>; 95 def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; 96 def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; 97 def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>; 98 def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>; 99 def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>; 100 def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; 101 102 /// Shift Instructions 103 def DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>; 104 def DSRL : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>; 105 def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>; 106 def DSLLV : shift_rotate_reg<0x14, 0x00, "dsllv", shl, CPU64Regs>; 107 def DSRLV : shift_rotate_reg<0x16, 0x00, "dsrlv", srl, CPU64Regs>; 108 def DSRAV : shift_rotate_reg<0x17, 0x00, "dsrav", sra, CPU64Regs>; 109 } 110 // Rotate Instructions 111 let Predicates = [HasMips64r2], DecoderNamespace = "Mips64" in { 112 def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>; 113 def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>; 114 } 115 116 let DecoderNamespace = "Mips64" in { 117 /// Load and Store Instructions 118 /// aligned 119 defm LB64 : LoadM64<0x20, "lb", sextloadi8>; 120 defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>; 121 defm LH64 : LoadM64<0x21, "lh", sextloadi16_a>; 122 defm LHu64 : LoadM64<0x25, "lhu", zextloadi16_a>; 123 defm LW64 : LoadM64<0x23, "lw", sextloadi32_a>; 124 defm LWu64 : LoadM64<0x27, "lwu", zextloadi32_a>; 125 defm SB64 : StoreM64<0x28, "sb", truncstorei8>; 126 defm SH64 : StoreM64<0x29, "sh", truncstorei16_a>; 127 defm SW64 : StoreM64<0x2b, "sw", truncstorei32_a>; 128 defm LD : LoadM64<0x37, "ld", load_a>; 129 defm SD : StoreM64<0x3f, "sd", store_a>; 130 131 /// unaligned 132 defm ULH64 : LoadM64<0x21, "ulh", sextloadi16_u, 1>; 133 defm ULHu64 : LoadM64<0x25, "ulhu", zextloadi16_u, 1>; 134 defm ULW64 : LoadM64<0x23, "ulw", sextloadi32_u, 1>; 135 defm USH64 : StoreM64<0x29, "ush", truncstorei16_u, 1>; 136 defm USW64 : StoreM64<0x2b, "usw", truncstorei32_u, 1>; 137 defm ULD : LoadM64<0x37, "uld", load_u, 1>; 138 defm USD : StoreM64<0x3f, "usd", store_u, 1>; 139 140 /// Load-linked, Store-conditional 141 def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, Requires<[NotN64]>; 142 def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, Requires<[IsN64]> { 143 let isCodeGenOnly = 1; 144 } 145 def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, Requires<[NotN64]>; 146 def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, Requires<[IsN64]> { 147 let isCodeGenOnly = 1; 148 } 149 150 /// Jump and Branch Instructions 151 def JR64 : JumpFR<0x00, 0x08, "jr", CPU64Regs>; 152 def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>; 153 def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>; 154 def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>; 155 def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>; 156 def BLEZ64 : CBranchZero<0x06, 0, "blez", setle, CPU64Regs>; 157 def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>; 158 } 159 let DecoderNamespace = "Mips64" in 160 def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>; 161 162 let DecoderNamespace = "Mips64" in { 163 /// Multiply and Divide Instructions. 164 def DMULT : Mult64<0x1c, "dmult", IIImul>; 165 def DMULTu : Mult64<0x1d, "dmultu", IIImul>; 166 def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>; 167 def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>; 168 169 def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>; 170 def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>; 171 def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>; 172 def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>; 173 174 /// Sign Ext In Register Instructions. 175 def SEB64 : SignExtInReg<0x10, "seb", i8, CPU64Regs>; 176 def SEH64 : SignExtInReg<0x18, "seh", i16, CPU64Regs>; 177 178 /// Count Leading 179 def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>; 180 def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>; 181 182 /// Double Word Swap Bytes/HalfWords 183 def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>; 184 def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>; 185 186 def LEA_ADDiu64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>; 187 } 188 let Uses = [SP_64], DecoderNamespace = "Mips64" in 189 def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>, 190 Requires<[IsN64]> { 191 let isCodeGenOnly = 1; 192 } 193 let DecoderNamespace = "Mips64" in { 194 def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>; 195 196 def DEXT : ExtBase<3, "dext", CPU64Regs>; 197 def DINS : InsBase<7, "dins", CPU64Regs>; 198 199 def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 200 "dsll\t$rd, $rt, 32", [], IIAlu>; 201 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 202 "sll\t$rd, $rt, 0", [], IIAlu>; 203 let isCodeGenOnly = 1 in 204 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), 205 "sll\t$rd, $rt, 0", [], IIAlu>; 206 } 207 //===----------------------------------------------------------------------===// 208 // Arbitrary patterns that map to one or more instructions 209 //===----------------------------------------------------------------------===// 210 211 // extended loads 212 let Predicates = [NotN64] in { 213 def : Pat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 214 def : Pat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 215 def : Pat<(i64 (extloadi16_a addr:$src)), (LH64 addr:$src)>; 216 def : Pat<(i64 (extloadi16_u addr:$src)), (ULH64 addr:$src)>; 217 def : Pat<(i64 (extloadi32_a addr:$src)), (LW64 addr:$src)>; 218 def : Pat<(i64 (extloadi32_u addr:$src)), (ULW64 addr:$src)>; 219 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>; 220 } 221 let Predicates = [IsN64] in { 222 def : Pat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; 223 def : Pat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; 224 def : Pat<(i64 (extloadi16_a addr:$src)), (LH64_P8 addr:$src)>; 225 def : Pat<(i64 (extloadi16_u addr:$src)), (ULH64_P8 addr:$src)>; 226 def : Pat<(i64 (extloadi32_a addr:$src)), (LW64_P8 addr:$src)>; 227 def : Pat<(i64 (extloadi32_u addr:$src)), (ULW64_P8 addr:$src)>; 228 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>; 229 } 230 231 // hi/lo relocs 232 def : Pat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 233 def : Pat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 234 def : Pat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 235 def : Pat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 236 def : Pat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 237 238 def : Pat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 239 def : Pat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 240 def : Pat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 241 def : Pat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 242 def : Pat<(MipsLo tglobaltlsaddr:$in), (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 243 244 def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 245 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 246 def : Pat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 247 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 248 def : Pat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 249 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 250 def : Pat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 251 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 252 def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 253 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 254 255 def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>; 256 def : WrapperPat<tconstpool, DADDiu, CPU64Regs>; 257 def : WrapperPat<texternalsym, DADDiu, CPU64Regs>; 258 def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>; 259 def : WrapperPat<tjumptable, DADDiu, CPU64Regs>; 260 def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; 261 262 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 263 ZERO_64>; 264 265 // setcc patterns 266 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 267 defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 268 defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 269 defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 270 defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 271 272 // select MipsDynAlloc 273 def : Pat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>, Requires<[IsN64]>; 274 275 // truncate 276 def : Pat<(i32 (trunc CPU64Regs:$src)), 277 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>; 278 279 // 32-to-64-bit extension 280 def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 281 def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 282 def : Pat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 283 284 // Sign extend in register 285 def : Pat<(i64 (sext_inreg CPU64Regs:$src, i32)), (SLL64_64 CPU64Regs:$src)>; 286 287 // bswap pattern 288 def : Pat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; 289