1 //===-- PTXInstrInfo.td - PTX Instruction defs --------------*- tablegen-*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the PTX instructions in TableGen format. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Instruction format superclass 16 //===----------------------------------------------------------------------===// 17 18 include "PTXInstrFormats.td" 19 20 //===----------------------------------------------------------------------===// 21 // Code Generation Predicates 22 //===----------------------------------------------------------------------===// 23 24 // Shader Model Support 25 def FDivNeedsRoundingMode : Predicate<"getSubtarget().fdivNeedsRoundingMode()">; 26 def FDivNoRoundingMode : Predicate<"!getSubtarget().fdivNeedsRoundingMode()">; 27 def FMadNeedsRoundingMode : Predicate<"getSubtarget().fmadNeedsRoundingMode()">; 28 def FMadNoRoundingMode : Predicate<"!getSubtarget().fmadNeedsRoundingMode()">; 29 30 // PTX Version Support 31 def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">; 32 def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">; 33 def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">; 34 def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">; 35 def SupportsPTX23 : Predicate<"getSubtarget().supportsPTX23()">; 36 def DoesNotSupportPTX23 : Predicate<"!getSubtarget().supportsPTX23()">; 37 38 // Fused-Multiply Add 39 def SupportsFMA : Predicate<"getSubtarget().supportsFMA()">; 40 def DoesNotSupportFMA : Predicate<"!getSubtarget().supportsFMA()">; 41 42 43 44 // def SDT_PTXCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 45 // def SDT_PTXCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 46 47 // def PTXcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PTXCallSeqStart, 48 // [SDNPHasChain, SDNPOutGlue]>; 49 // def PTXcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PTXCallSeqEnd, 50 // [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 51 52 def PTXcall : SDNode<"PTXISD::CALL", SDTNone, 53 [SDNPHasChain, SDNPVariadic, SDNPOptInGlue, SDNPOutGlue]>; 54 55 56 // Branch & call targets have OtherVT type. 57 def brtarget : Operand<OtherVT>; 58 def calltarget : Operand<i32>; 59 60 //===----------------------------------------------------------------------===// 61 // PTX Specific Node Definitions 62 //===----------------------------------------------------------------------===// 63 64 // PTX allow generic 3-reg shifts like shl r0, r1, r2 65 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>; 66 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>; 67 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>; 68 69 def PTXexit 70 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>; 71 def PTXret 72 : SDNode<"PTXISD::RET", SDTNone, 73 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 74 def PTXcopyaddress 75 : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>; 76 77 78 79 //===----------------------------------------------------------------------===// 80 // Instruction Class Templates 81 //===----------------------------------------------------------------------===// 82 83 // For floating-point instructions, we cannot just embed the pattern into the 84 // instruction definition since we need to muck around with the rounding mode, 85 // and I do not know how to insert constants into instructions directly from 86 // pattern matches. 87 88 //===- Floating-Point Instructions - 2 Operand Form -----------------------===// 89 multiclass PTX_FLOAT_2OP<string opcstr> { 90 def rr32 : InstPTX<(outs RegF32:$d), 91 (ins RndMode:$r, RegF32:$a), 92 !strconcat(opcstr, "$r.f32\t$d, $a"), []>; 93 def ri32 : InstPTX<(outs RegF32:$d), 94 (ins RndMode:$r, f32imm:$a), 95 !strconcat(opcstr, "$r.f32\t$d, $a"), []>; 96 def rr64 : InstPTX<(outs RegF64:$d), 97 (ins RndMode:$r, RegF64:$a), 98 !strconcat(opcstr, "$r.f64\t$d, $a"), []>; 99 def ri64 : InstPTX<(outs RegF64:$d), 100 (ins RndMode:$r, f64imm:$a), 101 !strconcat(opcstr, "$r.f64\t$d, $a"), []>; 102 } 103 104 //===- Floating-Point Instructions - 3 Operand Form -----------------------===// 105 multiclass PTX_FLOAT_3OP<string opcstr> { 106 def rr32 : InstPTX<(outs RegF32:$d), 107 (ins RndMode:$r, RegF32:$a, RegF32:$b), 108 !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>; 109 def ri32 : InstPTX<(outs RegF32:$d), 110 (ins RndMode:$r, RegF32:$a, f32imm:$b), 111 !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>; 112 def rr64 : InstPTX<(outs RegF64:$d), 113 (ins RndMode:$r, RegF64:$a, RegF64:$b), 114 !strconcat(opcstr, "$r.f64\t$d, $a, $b"), []>; 115 def ri64 : InstPTX<(outs RegF64:$d), 116 (ins RndMode:$r, RegF64:$a, f64imm:$b), 117 !strconcat(opcstr, "$r.f64\t$d, $a, $b"), []>; 118 } 119 120 //===- Floating-Point Instructions - 4 Operand Form -----------------------===// 121 multiclass PTX_FLOAT_4OP<string opcstr> { 122 def rrr32 : InstPTX<(outs RegF32:$d), 123 (ins RndMode:$r, RegF32:$a, RegF32:$b, RegF32:$c), 124 !strconcat(opcstr, "$r.f32\t$d, $a, $b, $c"), []>; 125 def rri32 : InstPTX<(outs RegF32:$d), 126 (ins RndMode:$r, RegF32:$a, RegF32:$b, f32imm:$c), 127 !strconcat(opcstr, "$r.f32\t$d, $a, $b, $c"), []>; 128 def rii32 : InstPTX<(outs RegF32:$d), 129 (ins RndMode:$r, RegF32:$a, f32imm:$b, f32imm:$c), 130 !strconcat(opcstr, "$r.f32\t$d, $a, $b, $c"), []>; 131 def rrr64 : InstPTX<(outs RegF64:$d), 132 (ins RndMode:$r, RegF64:$a, RegF64:$b, RegF64:$c), 133 !strconcat(opcstr, "$r.f64\t$d, $a, $b, $c"), []>; 134 def rri64 : InstPTX<(outs RegF64:$d), 135 (ins RndMode:$r, RegF64:$a, RegF64:$b, f64imm:$c), 136 !strconcat(opcstr, "$r.f64\t$d, $a, $b, $c"), []>; 137 def rii64 : InstPTX<(outs RegF64:$d), 138 (ins RndMode:$r, RegF64:$a, f64imm:$b, f64imm:$c), 139 !strconcat(opcstr, "$r.f64\t$d, $a, $b, $c"), []>; 140 } 141 142 //===- Integer Instructions - 3 Operand Form ------------------------------===// 143 multiclass PTX_INT3<string opcstr, SDNode opnode> { 144 def rr16 : InstPTX<(outs RegI16:$d), 145 (ins RegI16:$a, RegI16:$b), 146 !strconcat(opcstr, ".u16\t$d, $a, $b"), 147 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>; 148 def ri16 : InstPTX<(outs RegI16:$d), 149 (ins RegI16:$a, i16imm:$b), 150 !strconcat(opcstr, ".u16\t$d, $a, $b"), 151 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>; 152 def rr32 : InstPTX<(outs RegI32:$d), 153 (ins RegI32:$a, RegI32:$b), 154 !strconcat(opcstr, ".u32\t$d, $a, $b"), 155 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>; 156 def ri32 : InstPTX<(outs RegI32:$d), 157 (ins RegI32:$a, i32imm:$b), 158 !strconcat(opcstr, ".u32\t$d, $a, $b"), 159 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>; 160 def rr64 : InstPTX<(outs RegI64:$d), 161 (ins RegI64:$a, RegI64:$b), 162 !strconcat(opcstr, ".u64\t$d, $a, $b"), 163 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>; 164 def ri64 : InstPTX<(outs RegI64:$d), 165 (ins RegI64:$a, i64imm:$b), 166 !strconcat(opcstr, ".u64\t$d, $a, $b"), 167 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>; 168 } 169 170 //===- Integer Instructions - 3 Operand Form (Signed) ---------------------===// 171 multiclass PTX_INT3_SIGNED<string opcstr, SDNode opnode> { 172 def rr16 : InstPTX<(outs RegI16:$d), 173 (ins RegI16:$a, RegI16:$b), 174 !strconcat(opcstr, ".s16\t$d, $a, $b"), 175 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>; 176 def ri16 : InstPTX<(outs RegI16:$d), 177 (ins RegI16:$a, i16imm:$b), 178 !strconcat(opcstr, ".s16\t$d, $a, $b"), 179 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>; 180 def rr32 : InstPTX<(outs RegI32:$d), 181 (ins RegI32:$a, RegI32:$b), 182 !strconcat(opcstr, ".s32\t$d, $a, $b"), 183 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>; 184 def ri32 : InstPTX<(outs RegI32:$d), 185 (ins RegI32:$a, i32imm:$b), 186 !strconcat(opcstr, ".s32\t$d, $a, $b"), 187 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>; 188 def rr64 : InstPTX<(outs RegI64:$d), 189 (ins RegI64:$a, RegI64:$b), 190 !strconcat(opcstr, ".s64\t$d, $a, $b"), 191 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>; 192 def ri64 : InstPTX<(outs RegI64:$d), 193 (ins RegI64:$a, i64imm:$b), 194 !strconcat(opcstr, ".s64\t$d, $a, $b"), 195 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>; 196 } 197 198 //===- Bitwise Logic Instructions - 3 Operand Form ------------------------===// 199 multiclass PTX_LOGIC<string opcstr, SDNode opnode> { 200 def ripreds : InstPTX<(outs RegPred:$d), 201 (ins RegPred:$a, i1imm:$b), 202 !strconcat(opcstr, ".pred\t$d, $a, $b"), 203 [(set RegPred:$d, (opnode RegPred:$a, imm:$b))]>; 204 def rrpreds : InstPTX<(outs RegPred:$d), 205 (ins RegPred:$a, RegPred:$b), 206 !strconcat(opcstr, ".pred\t$d, $a, $b"), 207 [(set RegPred:$d, (opnode RegPred:$a, RegPred:$b))]>; 208 def rr16 : InstPTX<(outs RegI16:$d), 209 (ins RegI16:$a, RegI16:$b), 210 !strconcat(opcstr, ".b16\t$d, $a, $b"), 211 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>; 212 def ri16 : InstPTX<(outs RegI16:$d), 213 (ins RegI16:$a, i16imm:$b), 214 !strconcat(opcstr, ".b16\t$d, $a, $b"), 215 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>; 216 def rr32 : InstPTX<(outs RegI32:$d), 217 (ins RegI32:$a, RegI32:$b), 218 !strconcat(opcstr, ".b32\t$d, $a, $b"), 219 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>; 220 def ri32 : InstPTX<(outs RegI32:$d), 221 (ins RegI32:$a, i32imm:$b), 222 !strconcat(opcstr, ".b32\t$d, $a, $b"), 223 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>; 224 def rr64 : InstPTX<(outs RegI64:$d), 225 (ins RegI64:$a, RegI64:$b), 226 !strconcat(opcstr, ".b64\t$d, $a, $b"), 227 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>; 228 def ri64 : InstPTX<(outs RegI64:$d), 229 (ins RegI64:$a, i64imm:$b), 230 !strconcat(opcstr, ".b64\t$d, $a, $b"), 231 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>; 232 } 233 234 //===- Integer Shift Instructions - 3 Operand Form ------------------------===// 235 multiclass PTX_INT3ntnc<string opcstr, SDNode opnode> { 236 def rr16 : InstPTX<(outs RegI16:$d), 237 (ins RegI16:$a, RegI16:$b), 238 !strconcat(opcstr, "16\t$d, $a, $b"), 239 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>; 240 def rr32 : InstPTX<(outs RegI32:$d), 241 (ins RegI32:$a, RegI32:$b), 242 !strconcat(opcstr, "32\t$d, $a, $b"), 243 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>; 244 def rr64 : InstPTX<(outs RegI64:$d), 245 (ins RegI64:$a, RegI64:$b), 246 !strconcat(opcstr, "64\t$d, $a, $b"), 247 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>; 248 def ri16 : InstPTX<(outs RegI16:$d), 249 (ins RegI16:$a, i16imm:$b), 250 !strconcat(opcstr, "16\t$d, $a, $b"), 251 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>; 252 def ri32 : InstPTX<(outs RegI32:$d), 253 (ins RegI32:$a, i32imm:$b), 254 !strconcat(opcstr, "32\t$d, $a, $b"), 255 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>; 256 def ri64 : InstPTX<(outs RegI64:$d), 257 (ins RegI64:$a, i64imm:$b), 258 !strconcat(opcstr, "64\t$d, $a, $b"), 259 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>; 260 def ir16 : InstPTX<(outs RegI16:$d), 261 (ins i16imm:$a, RegI16:$b), 262 !strconcat(opcstr, "16\t$d, $a, $b"), 263 [(set RegI16:$d, (opnode imm:$a, RegI16:$b))]>; 264 def ir32 : InstPTX<(outs RegI32:$d), 265 (ins i32imm:$a, RegI32:$b), 266 !strconcat(opcstr, "32\t$d, $a, $b"), 267 [(set RegI32:$d, (opnode imm:$a, RegI32:$b))]>; 268 def ir64 : InstPTX<(outs RegI64:$d), 269 (ins i64imm:$a, RegI64:$b), 270 !strconcat(opcstr, "64\t$d, $a, $b"), 271 [(set RegI64:$d, (opnode imm:$a, RegI64:$b))]>; 272 } 273 274 //===- Set Predicate Instructions (Int) - 3/4 Operand Forms ---------------===// 275 multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls, 276 CondCode cmp, string cmpstr> { 277 // TODO support 5-operand format: p|q, a, b, c 278 279 def rr 280 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b), 281 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"), 282 [(set RegPred:$p, (setcc RC:$a, RC:$b, cmp))]>; 283 def ri 284 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b), 285 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"), 286 [(set RegPred:$p, (setcc RC:$a, imm:$b, cmp))]>; 287 288 def rr_and_r 289 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 290 !strconcat("setp.", cmpstr, ".and.", regclsname, 291 "\t$p, $a, $b, $c"), 292 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>; 293 def ri_and_r 294 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c), 295 !strconcat("setp.", cmpstr, ".and.", regclsname, 296 "\t$p, $a, $b, $c"), 297 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp), 298 RegPred:$c))]>; 299 def rr_or_r 300 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 301 !strconcat("setp.", cmpstr, ".or.", regclsname, 302 "\t$p, $a, $b, $c"), 303 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>; 304 def ri_or_r 305 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c), 306 !strconcat("setp.", cmpstr, ".or.", regclsname, 307 "\t$p, $a, $b, $c"), 308 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>; 309 def rr_xor_r 310 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 311 !strconcat("setp.", cmpstr, ".xor.", regclsname, 312 "\t$p, $a, $b, $c"), 313 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>; 314 def ri_xor_r 315 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c), 316 !strconcat("setp.", cmpstr, ".xor.", regclsname, 317 "\t$p, $a, $b, $c"), 318 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp), 319 RegPred:$c))]>; 320 321 def rr_and_not_r 322 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 323 !strconcat("setp.", cmpstr, ".and.", regclsname, 324 "\t$p, $a, $b, !$c"), 325 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), 326 (not RegPred:$c)))]>; 327 def ri_and_not_r 328 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c), 329 !strconcat("setp.", cmpstr, ".and.", regclsname, 330 "\t$p, $a, $b, !$c"), 331 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp), 332 (not RegPred:$c)))]>; 333 def rr_or_not_r 334 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 335 !strconcat("setp.", cmpstr, ".or.", regclsname, 336 "\t$p, $a, $b, !$c"), 337 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), 338 (not RegPred:$c)))]>; 339 def ri_or_not_r 340 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c), 341 !strconcat("setp.", cmpstr, ".or.", regclsname, 342 "\t$p, $a, $b, !$c"), 343 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), 344 (not RegPred:$c)))]>; 345 def rr_xor_not_r 346 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 347 !strconcat("setp.", cmpstr, ".xor.", regclsname, 348 "\t$p, $a, $b, !$c"), 349 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), 350 (not RegPred:$c)))]>; 351 def ri_xor_not_r 352 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c), 353 !strconcat("setp.", cmpstr, ".xor.", regclsname, 354 "\t$p, $a, $b, !$c"), 355 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp), 356 (not RegPred:$c)))]>; 357 } 358 359 //===- Set Predicate Instructions (FP) - 3/4 Operand Form -----------------===// 360 multiclass PTX_SETP_FP<RegisterClass RC, string regclsname, Operand immcls, 361 CondCode ucmp, CondCode ocmp, string cmpstr> { 362 // TODO support 5-operand format: p|q, a, b, c 363 364 def rr_u 365 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b), 366 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"), 367 [(set RegPred:$p, (setcc RC:$a, RC:$b, ucmp))]>; 368 def rr_o 369 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b), 370 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"), 371 [(set RegPred:$p, (setcc RC:$a, RC:$b, ocmp))]>; 372 373 def ri_u 374 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b), 375 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"), 376 [(set RegPred:$p, (setcc RC:$a, fpimm:$b, ucmp))]>; 377 def ri_o 378 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b), 379 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"), 380 [(set RegPred:$p, (setcc RC:$a, fpimm:$b, ocmp))]>; 381 382 def rr_and_r_u 383 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 384 !strconcat("setp.", cmpstr, "u.and.", regclsname, 385 "\t$p, $a, $b, $c"), 386 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp), 387 RegPred:$c))]>; 388 def rr_and_r_o 389 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 390 !strconcat("setp.", cmpstr, ".and.", regclsname, 391 "\t$p, $a, $b, $c"), 392 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp), 393 RegPred:$c))]>; 394 395 def rr_or_r_u 396 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 397 !strconcat("setp.", cmpstr, "u.or.", regclsname, 398 "\t$p, $a, $b, $c"), 399 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>; 400 def rr_or_r_o 401 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 402 !strconcat("setp.", cmpstr, ".or.", regclsname, 403 "\t$p, $a, $b, $c"), 404 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>; 405 406 def rr_xor_r_u 407 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 408 !strconcat("setp.", cmpstr, "u.xor.", regclsname, 409 "\t$p, $a, $b, $c"), 410 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp), 411 RegPred:$c))]>; 412 def rr_xor_r_o 413 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 414 !strconcat("setp.", cmpstr, ".xor.", regclsname, 415 "\t$p, $a, $b, $c"), 416 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp), 417 RegPred:$c))]>; 418 419 def rr_and_not_r_u 420 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 421 !strconcat("setp.", cmpstr, "u.and.", regclsname, 422 "\t$p, $a, $b, !$c"), 423 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp), 424 (not RegPred:$c)))]>; 425 def rr_and_not_r_o 426 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 427 !strconcat("setp.", cmpstr, ".and.", regclsname, 428 "\t$p, $a, $b, !$c"), 429 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp), 430 (not RegPred:$c)))]>; 431 432 def rr_or_not_r_u 433 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 434 !strconcat("setp.", cmpstr, "u.or.", regclsname, 435 "\t$p, $a, $b, !$c"), 436 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), 437 (not RegPred:$c)))]>; 438 def rr_or_not_r_o 439 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 440 !strconcat("setp.", cmpstr, ".or.", regclsname, 441 "\t$p, $a, $b, !$c"), 442 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), 443 (not RegPred:$c)))]>; 444 445 def rr_xor_not_r_u 446 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 447 !strconcat("setp.", cmpstr, "u.xor.", regclsname, 448 "\t$p, $a, $b, !$c"), 449 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp), 450 (not RegPred:$c)))]>; 451 def rr_xor_not_r_o 452 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c), 453 !strconcat("setp.", cmpstr, ".xor.", regclsname, 454 "\t$p, $a, $b, !$c"), 455 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp), 456 (not RegPred:$c)))]>; 457 } 458 459 //===- Select Predicate Instructions - 4 Operand Form ---------------------===// 460 multiclass PTX_SELP<RegisterClass RC, string regclsname, Operand immcls, 461 SDNode immnode> { 462 def rr 463 : InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, RC:$c), 464 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"), 465 [(set RC:$r, (select RegPred:$a, RC:$b, RC:$c))]>; 466 def ri 467 : InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, immcls:$c), 468 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"), 469 [(set RC:$r, (select RegPred:$a, RC:$b, immnode:$c))]>; 470 def ii 471 : InstPTX<(outs RC:$r), (ins RegPred:$a, immcls:$b, immcls:$c), 472 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"), 473 [(set RC:$r, (select RegPred:$a, immnode:$b, immnode:$c))]>; 474 } 475 476 477 478 //===----------------------------------------------------------------------===// 479 // Instructions 480 //===----------------------------------------------------------------------===// 481 482 ///===- Integer Arithmetic Instructions -----------------------------------===// 483 484 defm ADD : PTX_INT3<"add", add>; 485 defm SUB : PTX_INT3<"sub", sub>; 486 defm MUL : PTX_INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies 487 defm DIV : PTX_INT3<"div", udiv>; 488 defm SDIV : PTX_INT3_SIGNED<"div", sdiv>; 489 defm REM : PTX_INT3<"rem", urem>; 490 491 ///===- Floating-Point Arithmetic Instructions ----------------------------===// 492 493 // FNEG 494 defm FNEG : PTX_FLOAT_2OP<"neg">; 495 496 // Standard Binary Operations 497 defm FADD : PTX_FLOAT_3OP<"add">; 498 defm FSUB : PTX_FLOAT_3OP<"sub">; 499 defm FMUL : PTX_FLOAT_3OP<"mul">; 500 defm FDIV : PTX_FLOAT_3OP<"div">; 501 502 // Multi-operation hybrid instructions 503 defm FMAD : PTX_FLOAT_4OP<"mad">, Requires<[SupportsFMA]>; 504 505 506 ///===- Floating-Point Intrinsic Instructions -----------------------------===// 507 508 // SQRT 509 def FSQRTrr32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF32:$a), 510 "sqrt$r.f32\t$d, $a", []>; 511 def FSQRTri32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, f32imm:$a), 512 "sqrt$r.f32\t$d, $a", []>; 513 def FSQRTrr64 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegF64:$a), 514 "sqrt$r.f64\t$d, $a", []>; 515 def FSQRTri64 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, f64imm:$a), 516 "sqrt$r.f64\t$d, $a", []>; 517 518 // SIN 519 def FSINrr32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF32:$a), 520 "sin$r.f32\t$d, $a", []>; 521 def FSINri32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, f32imm:$a), 522 "sin$r.f32\t$d, $a", []>; 523 def FSINrr64 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegF64:$a), 524 "sin$r.f64\t$d, $a", []>; 525 def FSINri64 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, f64imm:$a), 526 "sin$r.f64\t$d, $a", []>; 527 528 // COS 529 def FCOSrr32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF32:$a), 530 "cos$r.f32\t$d, $a", []>; 531 def FCOSri32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, f32imm:$a), 532 "cos$r.f32\t$d, $a", []>; 533 def FCOSrr64 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegF64:$a), 534 "cos$r.f64\t$d, $a", []>; 535 def FCOSri64 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, f64imm:$a), 536 "cos$r.f64\t$d, $a", []>; 537 538 539 540 541 ///===- Comparison and Selection Instructions -----------------------------===// 542 543 // .setp 544 545 // Compare u16 546 547 defm SETPEQu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETEQ, "eq">; 548 defm SETPNEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETNE, "ne">; 549 defm SETPLTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULT, "lt">; 550 defm SETPLEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULE, "le">; 551 defm SETPGTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGT, "gt">; 552 defm SETPGEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGE, "ge">; 553 defm SETPLTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLT, "lt">; 554 defm SETPLEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLE, "le">; 555 defm SETPGTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGT, "gt">; 556 defm SETPGEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGE, "ge">; 557 558 // Compare u32 559 560 defm SETPEQu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETEQ, "eq">; 561 defm SETPNEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETNE, "ne">; 562 defm SETPLTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULT, "lt">; 563 defm SETPLEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULE, "le">; 564 defm SETPGTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGT, "gt">; 565 defm SETPGEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGE, "ge">; 566 defm SETPLTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLT, "lt">; 567 defm SETPLEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLE, "le">; 568 defm SETPGTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGT, "gt">; 569 defm SETPGEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGE, "ge">; 570 571 // Compare u64 572 573 defm SETPEQu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETEQ, "eq">; 574 defm SETPNEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETNE, "ne">; 575 defm SETPLTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULT, "lt">; 576 defm SETPLEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULE, "le">; 577 defm SETPGTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGT, "gt">; 578 defm SETPGEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGE, "ge">; 579 defm SETPLTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLT, "lt">; 580 defm SETPLEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLE, "le">; 581 defm SETPGTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGT, "gt">; 582 defm SETPGEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGE, "ge">; 583 584 // Compare f32 585 586 defm SETPEQf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUEQ, SETOEQ, "eq">; 587 defm SETPNEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUNE, SETONE, "ne">; 588 defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETULT, SETOLT, "lt">; 589 defm SETPLEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETULE, SETOLE, "le">; 590 defm SETPGTf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUGT, SETOGT, "gt">; 591 defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUGE, SETOGE, "ge">; 592 593 // Compare f64 594 595 defm SETPEQf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUEQ, SETOEQ, "eq">; 596 defm SETPNEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUNE, SETONE, "ne">; 597 defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETULT, SETOLT, "lt">; 598 defm SETPLEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETULE, SETOLE, "le">; 599 defm SETPGTf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUGT, SETOGT, "gt">; 600 defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUGE, SETOGE, "ge">; 601 602 // .selp 603 604 defm SELPi16 : PTX_SELP<RegI16, "u16", i16imm, imm>; 605 defm SELPi32 : PTX_SELP<RegI32, "u32", i32imm, imm>; 606 defm SELPi64 : PTX_SELP<RegI64, "u64", i64imm, imm>; 607 defm SELPf32 : PTX_SELP<RegF32, "f32", f32imm, fpimm>; 608 defm SELPf64 : PTX_SELP<RegF64, "f64", f64imm, fpimm>; 609 610 ///===- Logic and Shift Instructions --------------------------------------===// 611 612 defm SHL : PTX_INT3ntnc<"shl.b", PTXshl>; 613 defm SRL : PTX_INT3ntnc<"shr.u", PTXsrl>; 614 defm SRA : PTX_INT3ntnc<"shr.s", PTXsra>; 615 616 defm AND : PTX_LOGIC<"and", and>; 617 defm OR : PTX_LOGIC<"or", or>; 618 defm XOR : PTX_LOGIC<"xor", xor>; 619 620 ///===- Data Movement and Conversion Instructions -------------------------===// 621 622 // any_extend 623 // Implement the anyext instruction in terms of the PTX cvt instructions. 624 //def : Pat<(i32 (anyext RegI16:$a)), (CVT_u32_u16 RegI16:$a)>; 625 //def : Pat<(i64 (anyext RegI16:$a)), (CVT_u64_u16 RegI16:$a)>; 626 //def : Pat<(i64 (anyext RegI32:$a)), (CVT_u64_u32 RegI32:$a)>; 627 628 // bitconvert 629 // These instructions implement the bit-wise conversion between integer and 630 // floating-point types. 631 def MOVi32f32 632 : InstPTX<(outs RegI32:$d), (ins RegF32:$a), "mov.b32\t$d, $a", []>; 633 def MOVf32i32 634 : InstPTX<(outs RegF32:$d), (ins RegI32:$a), "mov.b32\t$d, $a", []>; 635 def MOVi64f64 636 : InstPTX<(outs RegI64:$d), (ins RegF64:$a), "mov.b64\t$d, $a", []>; 637 def MOVf64i64 638 : InstPTX<(outs RegF64:$d), (ins RegI64:$a), "mov.b64\t$d, $a", []>; 639 640 let neverHasSideEffects = 1 in { 641 def MOVPREDrr 642 : InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>; 643 def MOVU16rr 644 : InstPTX<(outs RegI16:$d), (ins RegI16:$a), "mov.u16\t$d, $a", []>; 645 def MOVU32rr 646 : InstPTX<(outs RegI32:$d), (ins RegI32:$a), "mov.u32\t$d, $a", []>; 647 def MOVU64rr 648 : InstPTX<(outs RegI64:$d), (ins RegI64:$a), "mov.u64\t$d, $a", []>; 649 def MOVF32rr 650 : InstPTX<(outs RegF32:$d), (ins RegF32:$a), "mov.f32\t$d, $a", []>; 651 def MOVF64rr 652 : InstPTX<(outs RegF64:$d), (ins RegF64:$a), "mov.f64\t$d, $a", []>; 653 } 654 655 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 656 def MOVPREDri 657 : InstPTX<(outs RegPred:$d), (ins i1imm:$a), "mov.pred\t$d, $a", 658 [(set RegPred:$d, imm:$a)]>; 659 def MOVU16ri 660 : InstPTX<(outs RegI16:$d), (ins i16imm:$a), "mov.u16\t$d, $a", 661 [(set RegI16:$d, imm:$a)]>; 662 def MOVU32ri 663 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a", 664 [(set RegI32:$d, imm:$a)]>; 665 def MOVU64ri 666 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a", 667 [(set RegI64:$d, imm:$a)]>; 668 def MOVF32ri 669 : InstPTX<(outs RegF32:$d), (ins f32imm:$a), "mov.f32\t$d, $a", 670 [(set RegF32:$d, fpimm:$a)]>; 671 def MOVF64ri 672 : InstPTX<(outs RegF64:$d), (ins f64imm:$a), "mov.f64\t$d, $a", 673 [(set RegF64:$d, fpimm:$a)]>; 674 } 675 676 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 677 def MOVaddr32 678 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a", 679 [(set RegI32:$d, (PTXcopyaddress tglobaladdr:$a))]>; 680 def MOVaddr64 681 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a", 682 [(set RegI64:$d, (PTXcopyaddress tglobaladdr:$a))]>; 683 def MOVframe32 684 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "cvta.local.u32\t$d, $a", 685 [(set RegI32:$d, (PTXcopyaddress frameindex:$a))]>; 686 def MOVframe64 687 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "cvta.local.u64\t$d, $a", 688 [(set RegI64:$d, (PTXcopyaddress frameindex:$a))]>; 689 } 690 691 // PTX cvt instructions 692 // Note all of these may actually be used, we just define all possible patterns 693 // here (that make sense). 694 // FIXME: Can we collapse this somehow into a multiclass def? 695 696 // To i16 697 def CVTu16u32 698 : InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a", []>; 699 def CVTu16u64 700 : InstPTX<(outs RegI16:$d), (ins RegI64:$a), "cvt.u16.u64\t$d, $a", []>; 701 def CVTu16f32 702 : InstPTX<(outs RegI16:$d), (ins RndMode:$r, RegF32:$a), 703 "cvt$r.u16.f32\t$d, $a", []>; 704 def CVTs16f32 705 : InstPTX<(outs RegI16:$d), (ins RndMode:$r, RegF32:$a), 706 "cvt$r.s16.f32\t$d, $a", []>; 707 def CVTu16f64 708 : InstPTX<(outs RegI16:$d), (ins RndMode:$r, RegF64:$a), 709 "cvt$r.u16.f64\t$d, $a", []>; 710 def CVTs16f64 711 : InstPTX<(outs RegI16:$d), (ins RndMode:$r, RegF64:$a), 712 "cvt$r.s16.f64\t$d, $a", []>; 713 714 // To i32 715 def CVTu32u16 716 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a", []>; 717 def CVTs32s16 718 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.s32.s16\t$d, $a", []>; 719 def CVTu32u64 720 : InstPTX<(outs RegI32:$d), (ins RegI64:$a), "cvt.u32.u64\t$d, $a", []>; 721 def CVTu32f32 722 : InstPTX<(outs RegI32:$d), (ins RndMode:$r, RegF32:$a), 723 "cvt$r.u32.f32\t$d, $a", []>; 724 def CVTs32f32 725 : InstPTX<(outs RegI32:$d), (ins RndMode:$r, RegF32:$a), 726 "cvt$r.s32.f32\t$d, $a", []>; 727 def CVTu32f64 728 : InstPTX<(outs RegI32:$d), (ins RndMode:$r, RegF64:$a), 729 "cvt$r.u32.f64\t$d, $a", []>; 730 def CVTs32f64 731 : InstPTX<(outs RegI32:$d), (ins RndMode:$r, RegF64:$a), 732 "cvt$r.s32.f64\t$d, $a", []>; 733 734 // To i64 735 def CVTu64u16 736 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a", []>; 737 def CVTs64s16 738 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.s64.s16\t$d, $a", []>; 739 def CVTu64u32 740 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a", []>; 741 def CVTs64s32 742 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.s64.s32\t$d, $a", []>; 743 def CVTu64f32 744 : InstPTX<(outs RegI64:$d), (ins RndMode:$r, RegF32:$a), 745 "cvt$r.u64.f32\t$d, $a", []>; 746 def CVTs64f32 747 : InstPTX<(outs RegI64:$d), (ins RndMode:$r, RegF32:$a), 748 "cvt$r.s64.f32\t$d, $a", []>; 749 def CVTu64f64 750 : InstPTX<(outs RegI64:$d), (ins RndMode:$r, RegF64:$a), 751 "cvt$r.u64.f64\t$d, $a", []>; 752 def CVTs64f64 753 : InstPTX<(outs RegI64:$d), (ins RndMode:$r, RegF64:$a), 754 "cvt$r.s64.f64\t$d, $a", []>; 755 756 // To f32 757 def CVTf32u16 758 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI16:$a), 759 "cvt$r.f32.u16\t$d, $a", []>; 760 def CVTf32s16 761 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI16:$a), 762 "cvt$r.f32.s16\t$d, $a", []>; 763 def CVTf32u32 764 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI32:$a), 765 "cvt$r.f32.u32\t$d, $a", []>; 766 def CVTf32s32 767 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI32:$a), 768 "cvt$r.f32.s32\t$d, $a", []>; 769 def CVTf32u64 770 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI64:$a), 771 "cvt$r.f32.u64\t$d, $a", []>; 772 def CVTf32s64 773 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI64:$a), 774 "cvt$r.f32.s64\t$d, $a", []>; 775 def CVTf32f64 776 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF64:$a), 777 "cvt$r.f32.f64\t$d, $a", []>; 778 779 // To f64 780 def CVTf64u16 781 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI16:$a), 782 "cvt$r.f64.u16\t$d, $a", []>; 783 def CVTf64s16 784 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI16:$a), 785 "cvt$r.f64.s16\t$d, $a", []>; 786 def CVTf64u32 787 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI32:$a), 788 "cvt$r.f64.u32\t$d, $a", []>; 789 def CVTf64s32 790 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI32:$a), 791 "cvt$r.f64.s32\t$d, $a", []>; 792 def CVTf64u64 793 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI64:$a), 794 "cvt$r.f64.u64\t$d, $a", []>; 795 def CVTf64s64 796 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI64:$a), 797 "cvt$r.f64.s64\t$d, $a", []>; 798 def CVTf64f32 799 : InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a", []>; 800 801 ///===- Control Flow Instructions -----------------------------------------===// 802 803 let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 804 def BRAd 805 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>; 806 } 807 808 let isBranch = 1, isTerminator = 1 in { 809 // FIXME: The pattern part is blank because I cannot (or do not yet know 810 // how to) use the first operand of PredicateOperand (a RegPred register) here 811 // When this is revisited, make sure to also look at LowerSETCC and try to 812 // fold it into negated predicates, if possible. 813 def BRAdp 814 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d", 815 [/*(brcond pred:$_p, bb:$d)*/]>; 816 } 817 818 let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 819 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>; 820 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>; 821 } 822 823 let hasSideEffects = 1 in { 824 def CALL : InstPTX<(outs), (ins), "call", [(PTXcall)]>; 825 } 826 827 ///===- Parameter Passing Pseudo-Instructions -----------------------------===// 828 829 def READPARAMPRED : InstPTX<(outs RegPred:$a), (ins i32imm:$b), 830 "mov.pred\t$a, %arg$b", []>; 831 def READPARAMI16 : InstPTX<(outs RegI16:$a), (ins i32imm:$b), 832 "mov.b16\t$a, %arg$b", []>; 833 def READPARAMI32 : InstPTX<(outs RegI32:$a), (ins i32imm:$b), 834 "mov.b32\t$a, %arg$b", []>; 835 def READPARAMI64 : InstPTX<(outs RegI64:$a), (ins i32imm:$b), 836 "mov.b64\t$a, %arg$b", []>; 837 def READPARAMF32 : InstPTX<(outs RegF32:$a), (ins i32imm:$b), 838 "mov.f32\t$a, %arg$b", []>; 839 def READPARAMF64 : InstPTX<(outs RegF64:$a), (ins i32imm:$b), 840 "mov.f64\t$a, %arg$b", []>; 841 842 def WRITEPARAMPRED : InstPTX<(outs), (ins RegPred:$a), "//w", []>; 843 def WRITEPARAMI16 : InstPTX<(outs), (ins RegI16:$a), "//w", []>; 844 def WRITEPARAMI32 : InstPTX<(outs), (ins RegI32:$a), "//w", []>; 845 def WRITEPARAMI64 : InstPTX<(outs), (ins RegI64:$a), "//w", []>; 846 def WRITEPARAMF32 : InstPTX<(outs), (ins RegF32:$a), "//w", []>; 847 def WRITEPARAMF64 : InstPTX<(outs), (ins RegF64:$a), "//w", []>; 848 849 850 //===----------------------------------------------------------------------===// 851 // Instruction Selection Patterns 852 //===----------------------------------------------------------------------===// 853 854 // FADD 855 def : Pat<(f32 (fadd RegF32:$a, RegF32:$b)), 856 (FADDrr32 RndDefault, RegF32:$a, RegF32:$b)>; 857 def : Pat<(f32 (fadd RegF32:$a, fpimm:$b)), 858 (FADDri32 RndDefault, RegF32:$a, fpimm:$b)>; 859 def : Pat<(f64 (fadd RegF64:$a, RegF64:$b)), 860 (FADDrr64 RndDefault, RegF64:$a, RegF64:$b)>; 861 def : Pat<(f64 (fadd RegF64:$a, fpimm:$b)), 862 (FADDri64 RndDefault, RegF64:$a, fpimm:$b)>; 863 864 // FSUB 865 def : Pat<(f32 (fsub RegF32:$a, RegF32:$b)), 866 (FSUBrr32 RndDefault, RegF32:$a, RegF32:$b)>; 867 def : Pat<(f32 (fsub RegF32:$a, fpimm:$b)), 868 (FSUBri32 RndDefault, RegF32:$a, fpimm:$b)>; 869 def : Pat<(f64 (fsub RegF64:$a, RegF64:$b)), 870 (FSUBrr64 RndDefault, RegF64:$a, RegF64:$b)>; 871 def : Pat<(f64 (fsub RegF64:$a, fpimm:$b)), 872 (FSUBri64 RndDefault, RegF64:$a, fpimm:$b)>; 873 874 // FMUL 875 def : Pat<(f32 (fmul RegF32:$a, RegF32:$b)), 876 (FMULrr32 RndDefault, RegF32:$a, RegF32:$b)>; 877 def : Pat<(f32 (fmul RegF32:$a, fpimm:$b)), 878 (FMULri32 RndDefault, RegF32:$a, fpimm:$b)>; 879 def : Pat<(f64 (fmul RegF64:$a, RegF64:$b)), 880 (FMULrr64 RndDefault, RegF64:$a, RegF64:$b)>; 881 def : Pat<(f64 (fmul RegF64:$a, fpimm:$b)), 882 (FMULri64 RndDefault, RegF64:$a, fpimm:$b)>; 883 884 // FDIV 885 def : Pat<(f32 (fdiv RegF32:$a, RegF32:$b)), 886 (FDIVrr32 RndDefault, RegF32:$a, RegF32:$b)>; 887 def : Pat<(f32 (fdiv RegF32:$a, fpimm:$b)), 888 (FDIVri32 RndDefault, RegF32:$a, fpimm:$b)>; 889 def : Pat<(f64 (fdiv RegF64:$a, RegF64:$b)), 890 (FDIVrr64 RndDefault, RegF64:$a, RegF64:$b)>; 891 def : Pat<(f64 (fdiv RegF64:$a, fpimm:$b)), 892 (FDIVri64 RndDefault, RegF64:$a, fpimm:$b)>; 893 894 // FMUL+FADD 895 def : Pat<(f32 (fadd (fmul RegF32:$a, RegF32:$b), RegF32:$c)), 896 (FMADrrr32 RndDefault, RegF32:$a, RegF32:$b, RegF32:$c)>, 897 Requires<[SupportsFMA]>; 898 def : Pat<(f32 (fadd (fmul RegF32:$a, RegF32:$b), fpimm:$c)), 899 (FMADrri32 RndDefault, RegF32:$a, RegF32:$b, fpimm:$c)>, 900 Requires<[SupportsFMA]>; 901 def : Pat<(f32 (fadd (fmul RegF32:$a, fpimm:$b), fpimm:$c)), 902 (FMADrrr32 RndDefault, RegF32:$a, fpimm:$b, fpimm:$c)>, 903 Requires<[SupportsFMA]>; 904 def : Pat<(f32 (fadd (fmul RegF32:$a, RegF32:$b), fpimm:$c)), 905 (FMADrri32 RndDefault, RegF32:$a, RegF32:$b, fpimm:$c)>, 906 Requires<[SupportsFMA]>; 907 def : Pat<(f64 (fadd (fmul RegF64:$a, RegF64:$b), RegF64:$c)), 908 (FMADrrr64 RndDefault, RegF64:$a, RegF64:$b, RegF64:$c)>, 909 Requires<[SupportsFMA]>; 910 def : Pat<(f64 (fadd (fmul RegF64:$a, RegF64:$b), fpimm:$c)), 911 (FMADrri64 RndDefault, RegF64:$a, RegF64:$b, fpimm:$c)>, 912 Requires<[SupportsFMA]>; 913 def : Pat<(f64 (fadd (fmul RegF64:$a, fpimm:$b), fpimm:$c)), 914 (FMADrri64 RndDefault, RegF64:$a, fpimm:$b, fpimm:$c)>, 915 Requires<[SupportsFMA]>; 916 917 // FNEG 918 def : Pat<(f32 (fneg RegF32:$a)), (FNEGrr32 RndDefault, RegF32:$a)>; 919 def : Pat<(f32 (fneg fpimm:$a)), (FNEGri32 RndDefault, fpimm:$a)>; 920 def : Pat<(f64 (fneg RegF64:$a)), (FNEGrr64 RndDefault, RegF64:$a)>; 921 def : Pat<(f64 (fneg fpimm:$a)), (FNEGri64 RndDefault, fpimm:$a)>; 922 923 // FSQRT 924 def : Pat<(f32 (fsqrt RegF32:$a)), (FSQRTrr32 RndDefault, RegF32:$a)>; 925 def : Pat<(f32 (fsqrt fpimm:$a)), (FSQRTri32 RndDefault, fpimm:$a)>; 926 def : Pat<(f64 (fsqrt RegF64:$a)), (FSQRTrr64 RndDefault, RegF64:$a)>; 927 def : Pat<(f64 (fsqrt fpimm:$a)), (FSQRTri64 RndDefault, fpimm:$a)>; 928 929 // FSIN 930 def : Pat<(f32 (fsin RegF32:$a)), (FSINrr32 RndDefault, RegF32:$a)>; 931 def : Pat<(f32 (fsin fpimm:$a)), (FSINri32 RndDefault, fpimm:$a)>; 932 def : Pat<(f64 (fsin RegF64:$a)), (FSINrr64 RndDefault, RegF64:$a)>; 933 def : Pat<(f64 (fsin fpimm:$a)), (FSINri64 RndDefault, fpimm:$a)>; 934 935 // FCOS 936 def : Pat<(f32 (fcos RegF32:$a)), (FCOSrr32 RndDefault, RegF32:$a)>; 937 def : Pat<(f32 (fcos fpimm:$a)), (FCOSri32 RndDefault, fpimm:$a)>; 938 def : Pat<(f64 (fcos RegF64:$a)), (FCOSrr64 RndDefault, RegF64:$a)>; 939 def : Pat<(f64 (fcos fpimm:$a)), (FCOSri64 RndDefault, fpimm:$a)>; 940 941 // Type conversion notes: 942 // - PTX does not directly support converting a predicate to a value, so we 943 // use a select instruction to select either 0 or 1 (integer or fp) based 944 // on the truth value of the predicate. 945 // - PTX does not directly support converting to a predicate type, so we fake it 946 // by performing a greater-than test between the value and zero. This follows 947 // the C convention that any non-zero value is equivalent to 'true'. 948 949 // Conversion to pred 950 def : Pat<(i1 (trunc RegI16:$a)), (SETPGTu16ri RegI16:$a, 0)>; 951 def : Pat<(i1 (trunc RegI32:$a)), (SETPGTu32ri RegI32:$a, 0)>; 952 def : Pat<(i1 (trunc RegI64:$a)), (SETPGTu64ri RegI64:$a, 0)>; 953 def : Pat<(i1 (fp_to_uint RegF32:$a)), (SETPGTu32ri (MOVi32f32 RegF32:$a), 0)>; 954 def : Pat<(i1 (fp_to_uint RegF64:$a)), (SETPGTu64ri (MOVi64f64 RegF64:$a), 0)>; 955 956 // Conversion to u16 957 def : Pat<(i16 (anyext RegPred:$a)), (SELPi16ii RegPred:$a, 1, 0)>; 958 def : Pat<(i16 (sext RegPred:$a)), (SELPi16ii RegPred:$a, 0xFFFF, 0)>; 959 def : Pat<(i16 (zext RegPred:$a)), (SELPi16ii RegPred:$a, 1, 0)>; 960 def : Pat<(i16 (trunc RegI32:$a)), (CVTu16u32 RegI32:$a)>; 961 def : Pat<(i16 (trunc RegI64:$a)), (CVTu16u64 RegI64:$a)>; 962 def : Pat<(i16 (fp_to_uint RegF32:$a)), (CVTu16f32 RndDefault, RegF32:$a)>; 963 def : Pat<(i16 (fp_to_sint RegF32:$a)), (CVTs16f32 RndDefault, RegF32:$a)>; 964 def : Pat<(i16 (fp_to_uint RegF64:$a)), (CVTu16f64 RndDefault, RegF64:$a)>; 965 def : Pat<(i16 (fp_to_sint RegF64:$a)), (CVTs16f64 RndDefault, RegF64:$a)>; 966 967 // Conversion to u32 968 def : Pat<(i32 (anyext RegPred:$a)), (SELPi32ii RegPred:$a, 1, 0)>; 969 def : Pat<(i32 (sext RegPred:$a)), (SELPi32ii RegPred:$a, 0xFFFFFFFF, 0)>; 970 def : Pat<(i32 (zext RegPred:$a)), (SELPi32ii RegPred:$a, 1, 0)>; 971 def : Pat<(i32 (anyext RegI16:$a)), (CVTu32u16 RegI16:$a)>; 972 def : Pat<(i32 (sext RegI16:$a)), (CVTs32s16 RegI16:$a)>; 973 def : Pat<(i32 (zext RegI16:$a)), (CVTu32u16 RegI16:$a)>; 974 def : Pat<(i32 (trunc RegI64:$a)), (CVTu32u64 RegI64:$a)>; 975 def : Pat<(i32 (fp_to_uint RegF32:$a)), (CVTu32f32 RndDefault, RegF32:$a)>; 976 def : Pat<(i32 (fp_to_sint RegF32:$a)), (CVTs32f32 RndDefault, RegF32:$a)>; 977 def : Pat<(i32 (fp_to_uint RegF64:$a)), (CVTu32f64 RndDefault, RegF64:$a)>; 978 def : Pat<(i32 (fp_to_sint RegF64:$a)), (CVTs32f64 RndDefault, RegF64:$a)>; 979 def : Pat<(i32 (bitconvert RegF32:$a)), (MOVi32f32 RegF32:$a)>; 980 981 // Conversion to u64 982 def : Pat<(i64 (anyext RegPred:$a)), (SELPi64ii RegPred:$a, 1, 0)>; 983 def : Pat<(i64 (sext RegPred:$a)), (SELPi64ii RegPred:$a, 984 0xFFFFFFFFFFFFFFFF, 0)>; 985 def : Pat<(i64 (zext RegPred:$a)), (SELPi64ii RegPred:$a, 1, 0)>; 986 def : Pat<(i64 (anyext RegI16:$a)), (CVTu64u16 RegI16:$a)>; 987 def : Pat<(i64 (sext RegI16:$a)), (CVTs64s16 RegI16:$a)>; 988 def : Pat<(i64 (zext RegI16:$a)), (CVTu64u16 RegI16:$a)>; 989 def : Pat<(i64 (anyext RegI32:$a)), (CVTu64u32 RegI32:$a)>; 990 def : Pat<(i64 (sext RegI32:$a)), (CVTs64s32 RegI32:$a)>; 991 def : Pat<(i64 (zext RegI32:$a)), (CVTu64u32 RegI32:$a)>; 992 def : Pat<(i64 (fp_to_uint RegF32:$a)), (CVTu64f32 RndDefault, RegF32:$a)>; 993 def : Pat<(i64 (fp_to_sint RegF32:$a)), (CVTs64f32 RndDefault, RegF32:$a)>; 994 def : Pat<(i64 (fp_to_uint RegF64:$a)), (CVTu64f64 RndDefault, RegF64:$a)>; 995 def : Pat<(i64 (fp_to_sint RegF64:$a)), (CVTs64f64 RndDefault, RegF64:$a)>; 996 def : Pat<(i64 (bitconvert RegF64:$a)), (MOVi64f64 RegF64:$a)>; 997 998 // Conversion to f32 999 def : Pat<(f32 (uint_to_fp RegPred:$a)), (SELPf32rr RegPred:$a, 1000 (MOVf32i32 0x3F800000), (MOVf32i32 0))>; 1001 def : Pat<(f32 (uint_to_fp RegI16:$a)), (CVTf32u16 RndDefault, RegI16:$a)>; 1002 def : Pat<(f32 (sint_to_fp RegI16:$a)), (CVTf32s16 RndDefault, RegI16:$a)>; 1003 def : Pat<(f32 (uint_to_fp RegI32:$a)), (CVTf32u32 RndDefault, RegI32:$a)>; 1004 def : Pat<(f32 (sint_to_fp RegI32:$a)), (CVTf32s32 RndDefault, RegI32:$a)>; 1005 def : Pat<(f32 (uint_to_fp RegI64:$a)), (CVTf32u64 RndDefault, RegI64:$a)>; 1006 def : Pat<(f32 (sint_to_fp RegI64:$a)), (CVTf32s64 RndDefault, RegI64:$a)>; 1007 def : Pat<(f32 (fround RegF64:$a)), (CVTf32f64 RndDefault, RegF64:$a)>; 1008 def : Pat<(f32 (bitconvert RegI32:$a)), (MOVf32i32 RegI32:$a)>; 1009 1010 // Conversion to f64 1011 def : Pat<(f64 (uint_to_fp RegPred:$a)), (SELPf64rr RegPred:$a, 1012 (MOVf64i64 0x3F80000000000000), (MOVf64i64 0))>; 1013 def : Pat<(f64 (uint_to_fp RegI16:$a)), (CVTf64u16 RndDefault, RegI16:$a)>; 1014 def : Pat<(f64 (sint_to_fp RegI16:$a)), (CVTf64s16 RndDefault, RegI16:$a)>; 1015 def : Pat<(f64 (uint_to_fp RegI32:$a)), (CVTf64u32 RndDefault, RegI32:$a)>; 1016 def : Pat<(f64 (sint_to_fp RegI32:$a)), (CVTf64s32 RndDefault, RegI32:$a)>; 1017 def : Pat<(f64 (uint_to_fp RegI64:$a)), (CVTf64u64 RndDefault, RegI64:$a)>; 1018 def : Pat<(f64 (sint_to_fp RegI64:$a)), (CVTf64s64 RndDefault, RegI64:$a)>; 1019 def : Pat<(f64 (fextend RegF32:$a)), (CVTf64f32 RegF32:$a)>; 1020 def : Pat<(f64 (bitconvert RegI64:$a)), (MOVf64i64 RegI64:$a)>; 1021 1022 // setcc - predicate inversion for branch conditions 1023 def : Pat<(i1 (setcc RegPred:$a, imm:$b, SETNE)), 1024 (XORripreds RegPred:$a, imm:$b)>; 1025 1026 ///===- Intrinsic Instructions --------------------------------------------===// 1027 include "PTXIntrinsicInstrInfo.td" 1028 1029 ///===- Load/Store Instructions -------------------------------------------===// 1030 include "PTXInstrLoadStore.td" 1031 1032
