1 //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 // Primary reference: 11 // A2 Processor User's Manual. 12 // IBM (as updated in) 2010. 13 14 //===----------------------------------------------------------------------===// 15 // Functional units on the PowerPC A2 chip sets 16 // 17 def IU0to3_0 : FuncUnit; // Fetch unit 1 to 4 slot 1 18 def IU0to3_1 : FuncUnit; // Fetch unit 1 to 4 slot 2 19 def IU0to3_2 : FuncUnit; // Fetch unit 1 to 4 slot 3 20 def IU0to3_3 : FuncUnit; // Fetch unit 1 to 4 slot 4 21 def IU4_0 : FuncUnit; // Instruction buffer slot 1 22 def IU4_1 : FuncUnit; // Instruction buffer slot 2 23 def IU4_2 : FuncUnit; // Instruction buffer slot 3 24 def IU4_3 : FuncUnit; // Instruction buffer slot 4 25 def IU4_4 : FuncUnit; // Instruction buffer slot 5 26 def IU4_5 : FuncUnit; // Instruction buffer slot 6 27 def IU4_6 : FuncUnit; // Instruction buffer slot 7 28 def IU4_7 : FuncUnit; // Instruction buffer slot 8 29 def IU5 : FuncUnit; // Dependency resolution 30 def IU6 : FuncUnit; // Instruction issue 31 def RF0 : FuncUnit; 32 def XRF1 : FuncUnit; 33 def XEX1 : FuncUnit; // Execution stage 1 for the XU pipeline 34 def XEX2 : FuncUnit; // Execution stage 2 for the XU pipeline 35 def XEX3 : FuncUnit; // Execution stage 3 for the XU pipeline 36 def XEX4 : FuncUnit; // Execution stage 4 for the XU pipeline 37 def XEX5 : FuncUnit; // Execution stage 5 for the XU pipeline 38 def XEX6 : FuncUnit; // Execution stage 6 for the XU pipeline 39 def FRF1 : FuncUnit; 40 def FEX1 : FuncUnit; // Execution stage 1 for the FU pipeline 41 def FEX2 : FuncUnit; // Execution stage 2 for the FU pipeline 42 def FEX3 : FuncUnit; // Execution stage 3 for the FU pipeline 43 def FEX4 : FuncUnit; // Execution stage 4 for the FU pipeline 44 def FEX5 : FuncUnit; // Execution stage 5 for the FU pipeline 45 def FEX6 : FuncUnit; // Execution stage 6 for the FU pipeline 46 47 def CR_Bypass : Bypass; // The bypass for condition regs. 48 //def GPR_Bypass : Bypass; // The bypass for general-purpose regs. 49 //def FPR_Bypass : Bypass; // The bypass for floating-point regs. 50 51 // 52 // This file defines the itinerary class data for the PPC A2 processor. 53 // 54 //===----------------------------------------------------------------------===// 55 56 57 def PPCA2Itineraries : ProcessorItineraries< 58 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3, 59 IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7, 60 IU5, IU6, RF0, XRF1, XEX1, XEX2, XEX3, XEX4, XEX5, XEX6, 61 FRF1, FEX1, FEX2, FEX3, FEX4, FEX5, FEX6], 62 [CR_Bypass, GPR_Bypass, FPR_Bypass], [ 63 InstrItinData<IntGeneral , [InstrStage<4, 64 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 65 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 66 IU4_4, IU4_5, IU4_6, IU4_7]>, 67 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 68 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 69 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 70 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 71 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 72 [10, 7, 7], 73 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 74 InstrItinData<IntCompare , [InstrStage<4, 75 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 76 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 77 IU4_4, IU4_5, IU4_6, IU4_7]>, 78 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 79 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 80 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 81 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 82 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 83 [10, 7, 7], 84 [CR_Bypass, GPR_Bypass, GPR_Bypass]>, 85 InstrItinData<IntDivW , [InstrStage<4, 86 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 87 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 88 IU4_4, IU4_5, IU4_6, IU4_7]>, 89 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 90 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 91 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 92 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 93 InstrStage<1, [XEX5]>, InstrStage<38, [XEX6]>], 94 [53, 7, 7], 95 [NoBypass, GPR_Bypass, GPR_Bypass]>, 96 InstrItinData<IntMFFS , [InstrStage<4, 97 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 98 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 99 IU4_4, IU4_5, IU4_6, IU4_7]>, 100 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 101 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 102 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 103 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 104 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 105 [10, 7, 7], 106 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 107 InstrItinData<IntMTFSB0 , [InstrStage<4, 108 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 109 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 110 IU4_4, IU4_5, IU4_6, IU4_7]>, 111 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 112 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 113 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 114 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 115 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 116 [10, 7, 7], 117 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 118 InstrItinData<IntMulHW , [InstrStage<4, 119 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 120 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 121 IU4_4, IU4_5, IU4_6, IU4_7]>, 122 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 123 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 124 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 125 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 126 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 127 [14, 7, 7], 128 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 129 InstrItinData<IntMulHWU , [InstrStage<4, 130 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 131 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 132 IU4_4, IU4_5, IU4_6, IU4_7]>, 133 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 134 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 135 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 136 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 137 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 138 [14, 7, 7], 139 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 140 InstrItinData<IntMulLI , [InstrStage<4, 141 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 142 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 143 IU4_4, IU4_5, IU4_6, IU4_7]>, 144 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 145 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 146 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 147 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 148 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 149 [15, 7, 7], 150 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 151 InstrItinData<IntRotate , [InstrStage<4, 152 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 153 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 154 IU4_4, IU4_5, IU4_6, IU4_7]>, 155 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 156 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 157 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 158 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 159 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 160 [10, 7, 7], 161 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 162 InstrItinData<IntShift , [InstrStage<4, 163 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 164 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 165 IU4_4, IU4_5, IU4_6, IU4_7]>, 166 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 167 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 168 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 169 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 170 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 171 [10, 7, 7], 172 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 173 InstrItinData<IntTrapW , [InstrStage<4, 174 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 175 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 176 IU4_4, IU4_5, IU4_6, IU4_7]>, 177 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 178 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 179 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 180 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 181 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 182 [10, 7, 7], 183 [GPR_Bypass, GPR_Bypass]>, 184 InstrItinData<BrB , [InstrStage<4, 185 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 186 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 187 IU4_4, IU4_5, IU4_6, IU4_7]>, 188 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 189 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 190 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 191 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 192 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 193 [15, 7, 7], 194 [NoBypass, GPR_Bypass]>, 195 InstrItinData<BrCR , [InstrStage<4, 196 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 197 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 198 IU4_4, IU4_5, IU4_6, IU4_7]>, 199 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 200 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 201 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 202 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 203 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 204 [10, 7, 7], 205 [CR_Bypass, CR_Bypass, CR_Bypass]>, 206 InstrItinData<BrMCR , [InstrStage<4, 207 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 208 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 209 IU4_4, IU4_5, IU4_6, IU4_7]>, 210 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 211 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 212 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 213 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 214 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 215 [10, 7, 7], 216 [CR_Bypass, CR_Bypass, CR_Bypass]>, 217 InstrItinData<BrMCRX , [InstrStage<4, 218 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 219 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 220 IU4_4, IU4_5, IU4_6, IU4_7]>, 221 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 222 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 223 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 224 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 225 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 226 [10, 7, 7], 227 [CR_Bypass, GPR_Bypass, GPR_Bypass]>, 228 InstrItinData<LdStDCBA , [InstrStage<4, 229 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 230 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 231 IU4_4, IU4_5, IU4_6, IU4_7]>, 232 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 233 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 234 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 235 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 236 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 237 [13, 11], 238 [NoBypass, GPR_Bypass]>, 239 InstrItinData<LdStDCBF , [InstrStage<4, 240 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 241 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 242 IU4_4, IU4_5, IU4_6, IU4_7]>, 243 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 244 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 245 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 246 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 247 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 248 [13, 11], 249 [NoBypass, GPR_Bypass]>, 250 InstrItinData<LdStDCBI , [InstrStage<4, 251 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 252 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 253 IU4_4, IU4_5, IU4_6, IU4_7]>, 254 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 255 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 256 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 257 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 258 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 259 [13, 11], 260 [NoBypass, GPR_Bypass]>, 261 InstrItinData<LdStLoad , [InstrStage<4, 262 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 263 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 264 IU4_4, IU4_5, IU4_6, IU4_7]>, 265 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 266 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 267 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 268 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 269 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 270 [14, 7], 271 [GPR_Bypass, GPR_Bypass]>, 272 InstrItinData<LdStStore , [InstrStage<4, 273 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 274 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 275 IU4_4, IU4_5, IU4_6, IU4_7]>, 276 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 277 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 278 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 279 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 280 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 281 [13, 7], 282 [GPR_Bypass, GPR_Bypass]>, 283 InstrItinData<LdStICBI , [InstrStage<4, 284 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 285 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 286 IU4_4, IU4_5, IU4_6, IU4_7]>, 287 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 288 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 289 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 290 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 291 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 292 [14, 7], 293 [NoBypass, GPR_Bypass]>, 294 InstrItinData<LdStUX , [InstrStage<4, 295 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 296 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 297 IU4_4, IU4_5, IU4_6, IU4_7]>, 298 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 299 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 300 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 301 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 302 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 303 [14, 7, 7], 304 [NoBypass, FPR_Bypass, FPR_Bypass]>, 305 InstrItinData<LdStLFD , [InstrStage<4, 306 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 307 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 308 IU4_4, IU4_5, IU4_6, IU4_7]>, 309 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 310 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 311 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 312 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 313 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 314 [14, 7, 7], 315 [FPR_Bypass, GPR_Bypass, GPR_Bypass]>, 316 InstrItinData<LdStLFDU , [InstrStage<4, 317 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 318 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 319 IU4_4, IU4_5, IU4_6, IU4_7]>, 320 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 321 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 322 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 323 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 324 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 325 [14, 7, 7], 326 [FPR_Bypass, GPR_Bypass, GPR_Bypass]>, 327 InstrItinData<LdStLHA , [InstrStage<4, 328 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 329 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 330 IU4_4, IU4_5, IU4_6, IU4_7]>, 331 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 332 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 333 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 334 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 335 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 336 [14, 7], 337 [NoBypass, GPR_Bypass]>, 338 InstrItinData<LdStLMW , [InstrStage<4, 339 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 340 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 341 IU4_4, IU4_5, IU4_6, IU4_7]>, 342 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 343 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 344 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 345 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 346 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 347 [14, 7], 348 [NoBypass, GPR_Bypass]>, 349 InstrItinData<LdStLWARX , [InstrStage<4, 350 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 351 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 352 IU4_4, IU4_5, IU4_6, IU4_7]>, 353 InstrStage<1, [IU5]>, InstrStage<13, [IU6]>, 354 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 355 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 356 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 357 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 358 [26, 7], 359 [NoBypass, GPR_Bypass]>, 360 InstrItinData<LdStSTD , [InstrStage<4, 361 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 362 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 363 IU4_4, IU4_5, IU4_6, IU4_7]>, 364 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 365 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 366 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 367 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 368 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 369 [13, 7], 370 [GPR_Bypass, GPR_Bypass]>, 371 InstrItinData<LdStSTDCX , [InstrStage<4, 372 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 373 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 374 IU4_4, IU4_5, IU4_6, IU4_7]>, 375 InstrStage<1, [IU5]>, InstrStage<13, [IU6]>, 376 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 377 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 378 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 379 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 380 [26, 7], 381 [NoBypass, GPR_Bypass]>, 382 InstrItinData<LdStSTD , [InstrStage<4, 383 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 384 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 385 IU4_4, IU4_5, IU4_6, IU4_7]>, 386 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 387 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 388 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 389 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 390 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 391 [13, 7], 392 [GPR_Bypass, GPR_Bypass]>, 393 InstrItinData<LdStSTDCX , [InstrStage<4, 394 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 395 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 396 IU4_4, IU4_5, IU4_6, IU4_7]>, 397 InstrStage<1, [IU5]>, InstrStage<13, [IU6]>, 398 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 399 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 400 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 401 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 402 [26, 7], 403 [NoBypass, GPR_Bypass]>, 404 InstrItinData<LdStSTWCX , [InstrStage<4, 405 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 406 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 407 IU4_4, IU4_5, IU4_6, IU4_7]>, 408 InstrStage<1, [IU5]>, InstrStage<13, [IU6]>, 409 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 410 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 411 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 412 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 413 [26, 7], 414 [NoBypass, GPR_Bypass]>, 415 InstrItinData<LdStSync , [InstrStage<4, 416 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 417 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 418 IU4_4, IU4_5, IU4_6, IU4_7]>, 419 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 420 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 421 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 422 InstrStage<1, [XEX3]>, InstrStage<12, [XEX4]>, 423 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>]>, 424 InstrItinData<SprISYNC , [InstrStage<4, 425 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 426 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 427 IU4_4, IU4_5, IU4_6, IU4_7]>, 428 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 429 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 430 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 431 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 432 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>, 433 InstrItinData<SprMFSR , [InstrStage<4, 434 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 435 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 436 IU4_4, IU4_5, IU4_6, IU4_7]>, 437 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 438 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 439 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 440 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 441 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 442 [15, 7], 443 [GPR_Bypass, NoBypass]>, 444 InstrItinData<SprMTMSR , [InstrStage<4, 445 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 446 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 447 IU4_4, IU4_5, IU4_6, IU4_7]>, 448 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 449 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 450 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 451 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 452 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 453 [15, 7], 454 [NoBypass, GPR_Bypass]>, 455 InstrItinData<SprMTSR , [InstrStage<4, 456 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 457 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 458 IU4_4, IU4_5, IU4_6, IU4_7]>, 459 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 460 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 461 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 462 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 463 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 464 [15, 7], 465 [NoBypass, GPR_Bypass]>, 466 InstrItinData<SprTLBSYNC , [InstrStage<4, 467 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 468 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 469 IU4_4, IU4_5, IU4_6, IU4_7]>, 470 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 471 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 472 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 473 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 474 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>, 475 InstrItinData<SprMFCR , [InstrStage<4, 476 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 477 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 478 IU4_4, IU4_5, IU4_6, IU4_7]>, 479 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 480 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 481 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 482 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 483 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 484 [10, 7], 485 [GPR_Bypass, CR_Bypass]>, 486 InstrItinData<SprMFMSR , [InstrStage<4, 487 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 488 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 489 IU4_4, IU4_5, IU4_6, IU4_7]>, 490 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 491 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 492 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 493 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 494 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 495 [15, 7], 496 [GPR_Bypass, NoBypass]>, 497 InstrItinData<SprMFSPR , [InstrStage<4, 498 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 499 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 500 IU4_4, IU4_5, IU4_6, IU4_7]>, 501 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 502 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 503 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 504 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 505 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 506 [15, 7], 507 [NoBypass, GPR_Bypass]>, 508 InstrItinData<SprMFTB , [InstrStage<4, 509 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 510 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 511 IU4_4, IU4_5, IU4_6, IU4_7]>, 512 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 513 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 514 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 515 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 516 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>], 517 [29, 7], 518 [NoBypass, GPR_Bypass]>, 519 InstrItinData<SprMTSPR , [InstrStage<4, 520 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 521 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 522 IU4_4, IU4_5, IU4_6, IU4_7]>, 523 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 524 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 525 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 526 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 527 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], 528 [15, 7], 529 [NoBypass, GPR_Bypass]>, 530 InstrItinData<SprMTSRIN , [InstrStage<4, 531 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 532 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 533 IU4_4, IU4_5, IU4_6, IU4_7]>, 534 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 535 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 536 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 537 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 538 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>], 539 [29, 7], 540 [NoBypass, GPR_Bypass]>, 541 InstrItinData<SprRFI , [InstrStage<4, 542 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 543 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 544 IU4_4, IU4_5, IU4_6, IU4_7]>, 545 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 546 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 547 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 548 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 549 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>], 550 [29, 7], 551 [NoBypass, GPR_Bypass]>, 552 InstrItinData<SprSC , [InstrStage<4, 553 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 554 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 555 IU4_4, IU4_5, IU4_6, IU4_7]>, 556 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 557 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, 558 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, 559 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, 560 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>], 561 [29, 7], 562 [NoBypass, GPR_Bypass]>, 563 InstrItinData<FPGeneral , [InstrStage<4, 564 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 565 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 566 IU4_4, IU4_5, IU4_6, IU4_7]>, 567 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 568 InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>, 569 InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>, 570 InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>, 571 InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>], 572 [15, 7, 7], 573 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, 574 InstrItinData<FPCompare , [InstrStage<4, 575 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 576 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 577 IU4_4, IU4_5, IU4_6, IU4_7]>, 578 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 579 InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>, 580 InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>, 581 InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>, 582 InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>], 583 [13, 7, 7], 584 [CR_Bypass, FPR_Bypass, FPR_Bypass]>, 585 InstrItinData<FPDivD , [InstrStage<4, 586 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 587 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 588 IU4_4, IU4_5, IU4_6, IU4_7]>, 589 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 590 InstrStage<1, [RF0]>, InstrStage<71, [FRF1], 0>, 591 InstrStage<71, [FEX1], 0>, 592 InstrStage<71, [FEX2], 0>, 593 InstrStage<71, [FEX3], 0>, 594 InstrStage<71, [FEX4], 0>, 595 InstrStage<71, [FEX5], 0>, 596 InstrStage<71, [FEX6]>], 597 [86, 7, 7], 598 [NoBypass, FPR_Bypass, FPR_Bypass]>, 599 InstrItinData<FPDivS , [InstrStage<4, 600 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 601 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 602 IU4_4, IU4_5, IU4_6, IU4_7]>, 603 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 604 InstrStage<1, [RF0]>, InstrStage<58, [FRF1], 0>, 605 InstrStage<58, [FEX1], 0>, 606 InstrStage<58, [FEX2], 0>, 607 InstrStage<58, [FEX3], 0>, 608 InstrStage<58, [FEX4], 0>, 609 InstrStage<58, [FEX5], 0>, 610 InstrStage<58, [FEX6]>], 611 [73, 7, 7], 612 [NoBypass, FPR_Bypass, FPR_Bypass]>, 613 InstrItinData<FPSqrt , [InstrStage<4, 614 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 615 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 616 IU4_4, IU4_5, IU4_6, IU4_7]>, 617 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 618 InstrStage<1, [RF0]>, InstrStage<68, [FRF1], 0>, 619 InstrStage<68, [FEX1], 0>, 620 InstrStage<68, [FEX2], 0>, 621 InstrStage<68, [FEX3], 0>, 622 InstrStage<68, [FEX4], 0>, 623 InstrStage<68, [FEX5], 0>, 624 InstrStage<68, [FEX6]>], 625 [86, 7], // FIXME: should be [86, 7] for double 626 // and [82, 7] for single. Likewise, 627 // the FEX? cycle count should be 68 628 // for double and 64 for single. 629 [NoBypass, FPR_Bypass]>, 630 InstrItinData<FPFused , [InstrStage<4, 631 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 632 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 633 IU4_4, IU4_5, IU4_6, IU4_7]>, 634 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 635 InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>, 636 InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>, 637 InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>, 638 InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>], 639 [15, 7, 7, 7], 640 [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>, 641 InstrItinData<FPRes , [InstrStage<4, 642 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, 643 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, 644 IU4_4, IU4_5, IU4_6, IU4_7]>, 645 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, 646 InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>, 647 InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>, 648 InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>, 649 InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>], 650 [15, 7], 651 [FPR_Bypass, FPR_Bypass]> 652 ]>; 653
