1 //===-- SparcRegisterInfo.td - Sparc Register defs ---------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Declarations that describe the Sparc register file 12 //===----------------------------------------------------------------------===// 13 14 class SparcReg<string n> : Register<n> { 15 field bits<5> Num; 16 let Namespace = "SP"; 17 } 18 19 class SparcCtrlReg<string n>: Register<n> { 20 let Namespace = "SP"; 21 } 22 23 let Namespace = "SP" in { 24 def sub_even : SubRegIndex; 25 def sub_odd : SubRegIndex; 26 } 27 28 // Registers are identified with 5-bit ID numbers. 29 // Ri - 32-bit integer registers 30 class Ri<bits<5> num, string n> : SparcReg<n> { 31 let Num = num; 32 } 33 // Rf - 32-bit floating-point registers 34 class Rf<bits<5> num, string n> : SparcReg<n> { 35 let Num = num; 36 } 37 // Rd - Slots in the FP register file for 64-bit floating-point values. 38 class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> { 39 let Num = num; 40 let SubRegs = subregs; 41 let SubRegIndices = [sub_even, sub_odd]; 42 let CoveredBySubRegs = 1; 43 } 44 45 // Control Registers 46 def ICC : SparcCtrlReg<"ICC">; 47 def FCC : SparcCtrlReg<"FCC">; 48 49 // Y register 50 def Y : SparcCtrlReg<"Y">; 51 52 // Integer registers 53 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>; 54 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>; 55 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>; 56 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>; 57 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>; 58 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>; 59 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>; 60 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>; 61 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>; 62 def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>; 63 def O2 : Ri<10, "O2">, DwarfRegNum<[10]>; 64 def O3 : Ri<11, "O3">, DwarfRegNum<[11]>; 65 def O4 : Ri<12, "O4">, DwarfRegNum<[12]>; 66 def O5 : Ri<13, "O5">, DwarfRegNum<[13]>; 67 def O6 : Ri<14, "SP">, DwarfRegNum<[14]>; 68 def O7 : Ri<15, "O7">, DwarfRegNum<[15]>; 69 def L0 : Ri<16, "L0">, DwarfRegNum<[16]>; 70 def L1 : Ri<17, "L1">, DwarfRegNum<[17]>; 71 def L2 : Ri<18, "L2">, DwarfRegNum<[18]>; 72 def L3 : Ri<19, "L3">, DwarfRegNum<[19]>; 73 def L4 : Ri<20, "L4">, DwarfRegNum<[20]>; 74 def L5 : Ri<21, "L5">, DwarfRegNum<[21]>; 75 def L6 : Ri<22, "L6">, DwarfRegNum<[22]>; 76 def L7 : Ri<23, "L7">, DwarfRegNum<[23]>; 77 def I0 : Ri<24, "I0">, DwarfRegNum<[24]>; 78 def I1 : Ri<25, "I1">, DwarfRegNum<[25]>; 79 def I2 : Ri<26, "I2">, DwarfRegNum<[26]>; 80 def I3 : Ri<27, "I3">, DwarfRegNum<[27]>; 81 def I4 : Ri<28, "I4">, DwarfRegNum<[28]>; 82 def I5 : Ri<29, "I5">, DwarfRegNum<[29]>; 83 def I6 : Ri<30, "FP">, DwarfRegNum<[30]>; 84 def I7 : Ri<31, "I7">, DwarfRegNum<[31]>; 85 86 // Floating-point registers 87 def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>; 88 def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>; 89 def F2 : Rf< 2, "F2">, DwarfRegNum<[34]>; 90 def F3 : Rf< 3, "F3">, DwarfRegNum<[35]>; 91 def F4 : Rf< 4, "F4">, DwarfRegNum<[36]>; 92 def F5 : Rf< 5, "F5">, DwarfRegNum<[37]>; 93 def F6 : Rf< 6, "F6">, DwarfRegNum<[38]>; 94 def F7 : Rf< 7, "F7">, DwarfRegNum<[39]>; 95 def F8 : Rf< 8, "F8">, DwarfRegNum<[40]>; 96 def F9 : Rf< 9, "F9">, DwarfRegNum<[41]>; 97 def F10 : Rf<10, "F10">, DwarfRegNum<[42]>; 98 def F11 : Rf<11, "F11">, DwarfRegNum<[43]>; 99 def F12 : Rf<12, "F12">, DwarfRegNum<[44]>; 100 def F13 : Rf<13, "F13">, DwarfRegNum<[45]>; 101 def F14 : Rf<14, "F14">, DwarfRegNum<[46]>; 102 def F15 : Rf<15, "F15">, DwarfRegNum<[47]>; 103 def F16 : Rf<16, "F16">, DwarfRegNum<[48]>; 104 def F17 : Rf<17, "F17">, DwarfRegNum<[49]>; 105 def F18 : Rf<18, "F18">, DwarfRegNum<[50]>; 106 def F19 : Rf<19, "F19">, DwarfRegNum<[51]>; 107 def F20 : Rf<20, "F20">, DwarfRegNum<[52]>; 108 def F21 : Rf<21, "F21">, DwarfRegNum<[53]>; 109 def F22 : Rf<22, "F22">, DwarfRegNum<[54]>; 110 def F23 : Rf<23, "F23">, DwarfRegNum<[55]>; 111 def F24 : Rf<24, "F24">, DwarfRegNum<[56]>; 112 def F25 : Rf<25, "F25">, DwarfRegNum<[57]>; 113 def F26 : Rf<26, "F26">, DwarfRegNum<[58]>; 114 def F27 : Rf<27, "F27">, DwarfRegNum<[59]>; 115 def F28 : Rf<28, "F28">, DwarfRegNum<[60]>; 116 def F29 : Rf<29, "F29">, DwarfRegNum<[61]>; 117 def F30 : Rf<30, "F30">, DwarfRegNum<[62]>; 118 def F31 : Rf<31, "F31">, DwarfRegNum<[63]>; 119 120 // Aliases of the F* registers used to hold 64-bit fp values (doubles) 121 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>; 122 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>; 123 def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>; 124 def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>; 125 def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>; 126 def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>; 127 def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>; 128 def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>; 129 def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>; 130 def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>; 131 def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>; 132 def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[83]>; 133 def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[84]>; 134 def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[85]>; 135 def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[86]>; 136 def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>; 137 138 // Register classes. 139 // 140 // FIXME: the register order should be defined in terms of the preferred 141 // allocation order... 142 // 143 def IntRegs : RegisterClass<"SP", [i32], 32, 144 (add L0, L1, L2, L3, L4, L5, L6, 145 L7, I0, I1, I2, I3, I4, I5, 146 O0, O1, O2, O3, O4, O5, O7, 147 G1, 148 // Non-allocatable regs: 149 G2, G3, G4, // FIXME: OK for use only in 150 // applications, not libraries. 151 O6, // stack ptr 152 I6, // frame ptr 153 I7, // return address 154 G0, // constant zero 155 G5, G6, G7 // reserved for kernel 156 )>; 157 158 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>; 159 160 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 15)>; 161
