1 //===-- X86InstrShiftRotate.td - Shift and Rotate Instrs ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the shift and rotate instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // FIXME: Someone needs to smear multipattern goodness all over this file. 15 16 let Defs = [EFLAGS] in { 17 18 let Constraints = "$src1 = $dst" in { 19 let Uses = [CL] in { 20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1), 21 "shl{b}\t{%cl, $dst|$dst, CL}", 22 [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>; 23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1), 24 "shl{w}\t{%cl, $dst|$dst, CL}", 25 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize; 26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1), 27 "shl{l}\t{%cl, $dst|$dst, CL}", 28 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>; 29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1), 30 "shl{q}\t{%cl, $dst|$dst, CL}", 31 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>; 32 } // Uses = [CL] 33 34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), 35 "shl{b}\t{$src2, $dst|$dst, $src2}", 36 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>; 37 38 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. 39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), 40 "shl{w}\t{$src2, $dst|$dst, $src2}", 41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>, 42 OpSize; 43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), 44 "shl{l}\t{$src2, $dst|$dst, $src2}", 45 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>; 46 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), 47 (ins GR64:$src1, i8imm:$src2), 48 "shl{q}\t{$src2, $dst|$dst, $src2}", 49 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))], 50 IIC_SR>; 51 52 // NOTE: We don't include patterns for shifts of a register by one, because 53 // 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one). 54 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1), 55 "shl{b}\t$dst", [], IIC_SR>; 56 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1), 57 "shl{w}\t$dst", [], IIC_SR>, OpSize; 58 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1), 59 "shl{l}\t$dst", [], IIC_SR>; 60 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1), 61 "shl{q}\t$dst", [], IIC_SR>; 62 } // isConvertibleToThreeAddress = 1 63 } // Constraints = "$src = $dst" 64 65 66 // FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern 67 // using CL? 68 let Uses = [CL] in { 69 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), 70 "shl{b}\t{%cl, $dst|$dst, CL}", 71 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>; 72 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst), 73 "shl{w}\t{%cl, $dst|$dst, CL}", 74 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>, 75 OpSize; 76 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst), 77 "shl{l}\t{%cl, $dst|$dst, CL}", 78 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>; 79 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst), 80 "shl{q}\t{%cl, $dst|$dst, CL}", 81 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>; 82 } 83 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src), 84 "shl{b}\t{$src, $dst|$dst, $src}", 85 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)], 86 IIC_SR>; 87 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src), 88 "shl{w}\t{$src, $dst|$dst, $src}", 89 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)], 90 IIC_SR>, 91 OpSize; 92 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src), 93 "shl{l}\t{$src, $dst|$dst, $src}", 94 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)], 95 IIC_SR>; 96 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src), 97 "shl{q}\t{$src, $dst|$dst, $src}", 98 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)], 99 IIC_SR>; 100 101 // Shift by 1 102 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst), 103 "shl{b}\t$dst", 104 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)], 105 IIC_SR>; 106 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst), 107 "shl{w}\t$dst", 108 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)], 109 IIC_SR>, 110 OpSize; 111 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst), 112 "shl{l}\t$dst", 113 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)], 114 IIC_SR>; 115 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst), 116 "shl{q}\t$dst", 117 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)], 118 IIC_SR>; 119 120 let Constraints = "$src1 = $dst" in { 121 let Uses = [CL] in { 122 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1), 123 "shr{b}\t{%cl, $dst|$dst, CL}", 124 [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>; 125 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1), 126 "shr{w}\t{%cl, $dst|$dst, CL}", 127 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize; 128 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1), 129 "shr{l}\t{%cl, $dst|$dst, CL}", 130 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>; 131 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1), 132 "shr{q}\t{%cl, $dst|$dst, CL}", 133 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>; 134 } 135 136 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), 137 "shr{b}\t{$src2, $dst|$dst, $src2}", 138 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>; 139 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), 140 "shr{w}\t{$src2, $dst|$dst, $src2}", 141 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))], 142 IIC_SR>, OpSize; 143 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), 144 "shr{l}\t{$src2, $dst|$dst, $src2}", 145 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))], 146 IIC_SR>; 147 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), 148 "shr{q}\t{$src2, $dst|$dst, $src2}", 149 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>; 150 151 // Shift right by 1 152 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1), 153 "shr{b}\t$dst", 154 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>; 155 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1), 156 "shr{w}\t$dst", 157 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize; 158 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1), 159 "shr{l}\t$dst", 160 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>; 161 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1), 162 "shr{q}\t$dst", 163 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>; 164 } // Constraints = "$src = $dst" 165 166 167 let Uses = [CL] in { 168 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), 169 "shr{b}\t{%cl, $dst|$dst, CL}", 170 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>; 171 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst), 172 "shr{w}\t{%cl, $dst|$dst, CL}", 173 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>, 174 OpSize; 175 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst), 176 "shr{l}\t{%cl, $dst|$dst, CL}", 177 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>; 178 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst), 179 "shr{q}\t{%cl, $dst|$dst, CL}", 180 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>; 181 } 182 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src), 183 "shr{b}\t{$src, $dst|$dst, $src}", 184 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)], 185 IIC_SR>; 186 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src), 187 "shr{w}\t{$src, $dst|$dst, $src}", 188 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)], 189 IIC_SR>, 190 OpSize; 191 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src), 192 "shr{l}\t{$src, $dst|$dst, $src}", 193 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)], 194 IIC_SR>; 195 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src), 196 "shr{q}\t{$src, $dst|$dst, $src}", 197 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)], 198 IIC_SR>; 199 200 // Shift by 1 201 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst), 202 "shr{b}\t$dst", 203 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)], 204 IIC_SR>; 205 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst), 206 "shr{w}\t$dst", 207 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)], 208 IIC_SR>,OpSize; 209 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst), 210 "shr{l}\t$dst", 211 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)], 212 IIC_SR>; 213 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst), 214 "shr{q}\t$dst", 215 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)], 216 IIC_SR>; 217 218 let Constraints = "$src1 = $dst" in { 219 let Uses = [CL] in { 220 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), 221 "sar{b}\t{%cl, $dst|$dst, CL}", 222 [(set GR8:$dst, (sra GR8:$src1, CL))], 223 IIC_SR>; 224 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1), 225 "sar{w}\t{%cl, $dst|$dst, CL}", 226 [(set GR16:$dst, (sra GR16:$src1, CL))], 227 IIC_SR>, OpSize; 228 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1), 229 "sar{l}\t{%cl, $dst|$dst, CL}", 230 [(set GR32:$dst, (sra GR32:$src1, CL))], 231 IIC_SR>; 232 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1), 233 "sar{q}\t{%cl, $dst|$dst, CL}", 234 [(set GR64:$dst, (sra GR64:$src1, CL))], 235 IIC_SR>; 236 } 237 238 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), 239 "sar{b}\t{$src2, $dst|$dst, $src2}", 240 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))], 241 IIC_SR>; 242 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), 243 "sar{w}\t{$src2, $dst|$dst, $src2}", 244 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))], 245 IIC_SR>, 246 OpSize; 247 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), 248 "sar{l}\t{$src2, $dst|$dst, $src2}", 249 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))], 250 IIC_SR>; 251 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), 252 (ins GR64:$src1, i8imm:$src2), 253 "sar{q}\t{$src2, $dst|$dst, $src2}", 254 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))], 255 IIC_SR>; 256 257 // Shift by 1 258 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), 259 "sar{b}\t$dst", 260 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))], 261 IIC_SR>; 262 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1), 263 "sar{w}\t$dst", 264 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))], 265 IIC_SR>, OpSize; 266 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1), 267 "sar{l}\t$dst", 268 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))], 269 IIC_SR>; 270 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1), 271 "sar{q}\t$dst", 272 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))], 273 IIC_SR>; 274 } // Constraints = "$src = $dst" 275 276 277 let Uses = [CL] in { 278 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), 279 "sar{b}\t{%cl, $dst|$dst, CL}", 280 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)], 281 IIC_SR>; 282 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst), 283 "sar{w}\t{%cl, $dst|$dst, CL}", 284 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)], 285 IIC_SR>, OpSize; 286 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst), 287 "sar{l}\t{%cl, $dst|$dst, CL}", 288 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)], 289 IIC_SR>; 290 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst), 291 "sar{q}\t{%cl, $dst|$dst, CL}", 292 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)], 293 IIC_SR>; 294 } 295 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src), 296 "sar{b}\t{$src, $dst|$dst, $src}", 297 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)], 298 IIC_SR>; 299 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src), 300 "sar{w}\t{$src, $dst|$dst, $src}", 301 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)], 302 IIC_SR>, 303 OpSize; 304 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src), 305 "sar{l}\t{$src, $dst|$dst, $src}", 306 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)], 307 IIC_SR>; 308 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src), 309 "sar{q}\t{$src, $dst|$dst, $src}", 310 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)], 311 IIC_SR>; 312 313 // Shift by 1 314 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst), 315 "sar{b}\t$dst", 316 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)], 317 IIC_SR>; 318 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst), 319 "sar{w}\t$dst", 320 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)], 321 IIC_SR>, 322 OpSize; 323 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst), 324 "sar{l}\t$dst", 325 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)], 326 IIC_SR>; 327 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst), 328 "sar{q}\t$dst", 329 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)], 330 IIC_SR>; 331 332 //===----------------------------------------------------------------------===// 333 // Rotate instructions 334 //===----------------------------------------------------------------------===// 335 336 let Constraints = "$src1 = $dst" in { 337 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1), 338 "rcl{b}\t$dst", [], IIC_SR>; 339 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt), 340 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 341 let Uses = [CL] in 342 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1), 343 "rcl{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>; 344 345 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1), 346 "rcl{w}\t$dst", [], IIC_SR>, OpSize; 347 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt), 348 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize; 349 let Uses = [CL] in 350 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1), 351 "rcl{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize; 352 353 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1), 354 "rcl{l}\t$dst", [], IIC_SR>; 355 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt), 356 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 357 let Uses = [CL] in 358 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1), 359 "rcl{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>; 360 361 362 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1), 363 "rcl{q}\t$dst", [], IIC_SR>; 364 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt), 365 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 366 let Uses = [CL] in 367 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1), 368 "rcl{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>; 369 370 371 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1), 372 "rcr{b}\t$dst", [], IIC_SR>; 373 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt), 374 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 375 let Uses = [CL] in 376 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1), 377 "rcr{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>; 378 379 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1), 380 "rcr{w}\t$dst", [], IIC_SR>, OpSize; 381 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt), 382 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize; 383 let Uses = [CL] in 384 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1), 385 "rcr{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize; 386 387 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1), 388 "rcr{l}\t$dst", [], IIC_SR>; 389 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt), 390 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 391 let Uses = [CL] in 392 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1), 393 "rcr{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>; 394 395 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1), 396 "rcr{q}\t$dst", [], IIC_SR>; 397 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt), 398 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 399 let Uses = [CL] in 400 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1), 401 "rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>; 402 403 } // Constraints = "$src = $dst" 404 405 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst), 406 "rcl{b}\t$dst", [], IIC_SR>; 407 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt), 408 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 409 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst), 410 "rcl{w}\t$dst", [], IIC_SR>, OpSize; 411 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt), 412 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize; 413 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst), 414 "rcl{l}\t$dst", [], IIC_SR>; 415 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt), 416 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 417 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst), 418 "rcl{q}\t$dst", [], IIC_SR>; 419 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt), 420 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 421 422 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst), 423 "rcr{b}\t$dst", [], IIC_SR>; 424 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt), 425 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 426 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst), 427 "rcr{w}\t$dst", [], IIC_SR>, OpSize; 428 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt), 429 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize; 430 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst), 431 "rcr{l}\t$dst", [], IIC_SR>; 432 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt), 433 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 434 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst), 435 "rcr{q}\t$dst", [], IIC_SR>; 436 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt), 437 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 438 439 let Uses = [CL] in { 440 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst), 441 "rcl{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>; 442 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst), 443 "rcl{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize; 444 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst), 445 "rcl{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>; 446 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst), 447 "rcl{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>; 448 449 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst), 450 "rcr{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>; 451 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst), 452 "rcr{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize; 453 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst), 454 "rcr{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>; 455 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst), 456 "rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>; 457 } 458 459 let Constraints = "$src1 = $dst" in { 460 // FIXME: provide shorter instructions when imm8 == 1 461 let Uses = [CL] in { 462 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), 463 "rol{b}\t{%cl, $dst|$dst, CL}", 464 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>; 465 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1), 466 "rol{w}\t{%cl, $dst|$dst, CL}", 467 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize; 468 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1), 469 "rol{l}\t{%cl, $dst|$dst, CL}", 470 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>; 471 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1), 472 "rol{q}\t{%cl, $dst|$dst, CL}", 473 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>; 474 } 475 476 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), 477 "rol{b}\t{$src2, $dst|$dst, $src2}", 478 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>; 479 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), 480 "rol{w}\t{$src2, $dst|$dst, $src2}", 481 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))], 482 IIC_SR>, 483 OpSize; 484 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), 485 "rol{l}\t{$src2, $dst|$dst, $src2}", 486 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))], 487 IIC_SR>; 488 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), 489 (ins GR64:$src1, i8imm:$src2), 490 "rol{q}\t{$src2, $dst|$dst, $src2}", 491 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))], 492 IIC_SR>; 493 494 // Rotate by 1 495 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), 496 "rol{b}\t$dst", 497 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))], 498 IIC_SR>; 499 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1), 500 "rol{w}\t$dst", 501 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))], 502 IIC_SR>, OpSize; 503 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1), 504 "rol{l}\t$dst", 505 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))], 506 IIC_SR>; 507 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1), 508 "rol{q}\t$dst", 509 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))], 510 IIC_SR>; 511 } // Constraints = "$src = $dst" 512 513 let Uses = [CL] in { 514 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), 515 "rol{b}\t{%cl, $dst|$dst, CL}", 516 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)], 517 IIC_SR>; 518 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst), 519 "rol{w}\t{%cl, $dst|$dst, CL}", 520 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)], 521 IIC_SR>, OpSize; 522 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst), 523 "rol{l}\t{%cl, $dst|$dst, CL}", 524 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)], 525 IIC_SR>; 526 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst), 527 "rol{q}\t{%cl, $dst|$dst, %cl}", 528 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)], 529 IIC_SR>; 530 } 531 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src1), 532 "rol{b}\t{$src1, $dst|$dst, $src1}", 533 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)], 534 IIC_SR>; 535 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1), 536 "rol{w}\t{$src1, $dst|$dst, $src1}", 537 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)], 538 IIC_SR>, 539 OpSize; 540 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1), 541 "rol{l}\t{$src1, $dst|$dst, $src1}", 542 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)], 543 IIC_SR>; 544 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1), 545 "rol{q}\t{$src1, $dst|$dst, $src1}", 546 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)], 547 IIC_SR>; 548 549 // Rotate by 1 550 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst), 551 "rol{b}\t$dst", 552 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)], 553 IIC_SR>; 554 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst), 555 "rol{w}\t$dst", 556 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)], 557 IIC_SR>, 558 OpSize; 559 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst), 560 "rol{l}\t$dst", 561 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)], 562 IIC_SR>; 563 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst), 564 "rol{q}\t$dst", 565 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)], 566 IIC_SR>; 567 568 let Constraints = "$src1 = $dst" in { 569 let Uses = [CL] in { 570 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 571 "ror{b}\t{%cl, $dst|$dst, CL}", 572 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>; 573 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 574 "ror{w}\t{%cl, $dst|$dst, CL}", 575 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize; 576 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1), 577 "ror{l}\t{%cl, $dst|$dst, CL}", 578 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>; 579 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1), 580 "ror{q}\t{%cl, $dst|$dst, CL}", 581 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>; 582 } 583 584 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), 585 "ror{b}\t{$src2, $dst|$dst, $src2}", 586 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))], IIC_SR>; 587 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), 588 "ror{w}\t{$src2, $dst|$dst, $src2}", 589 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))], 590 IIC_SR>, 591 OpSize; 592 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), 593 "ror{l}\t{$src2, $dst|$dst, $src2}", 594 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))], 595 IIC_SR>; 596 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), 597 (ins GR64:$src1, i8imm:$src2), 598 "ror{q}\t{$src2, $dst|$dst, $src2}", 599 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))], 600 IIC_SR>; 601 602 // Rotate by 1 603 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 604 "ror{b}\t$dst", 605 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))], 606 IIC_SR>; 607 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 608 "ror{w}\t$dst", 609 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))], 610 IIC_SR>, OpSize; 611 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), 612 "ror{l}\t$dst", 613 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))], 614 IIC_SR>; 615 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1), 616 "ror{q}\t$dst", 617 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))], 618 IIC_SR>; 619 } // Constraints = "$src = $dst" 620 621 let Uses = [CL] in { 622 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), 623 "ror{b}\t{%cl, $dst|$dst, CL}", 624 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)], 625 IIC_SR>; 626 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst), 627 "ror{w}\t{%cl, $dst|$dst, CL}", 628 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)], 629 IIC_SR>, OpSize; 630 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst), 631 "ror{l}\t{%cl, $dst|$dst, CL}", 632 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)], 633 IIC_SR>; 634 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst), 635 "ror{q}\t{%cl, $dst|$dst, CL}", 636 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)], 637 IIC_SR>; 638 } 639 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), 640 "ror{b}\t{$src, $dst|$dst, $src}", 641 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)], 642 IIC_SR>; 643 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src), 644 "ror{w}\t{$src, $dst|$dst, $src}", 645 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)], 646 IIC_SR>, 647 OpSize; 648 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src), 649 "ror{l}\t{$src, $dst|$dst, $src}", 650 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)], 651 IIC_SR>; 652 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src), 653 "ror{q}\t{$src, $dst|$dst, $src}", 654 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)], 655 IIC_SR>; 656 657 // Rotate by 1 658 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst), 659 "ror{b}\t$dst", 660 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)], 661 IIC_SR>; 662 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), 663 "ror{w}\t$dst", 664 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)], 665 IIC_SR>, 666 OpSize; 667 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), 668 "ror{l}\t$dst", 669 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)], 670 IIC_SR>; 671 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst), 672 "ror{q}\t$dst", 673 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)], 674 IIC_SR>; 675 676 677 //===----------------------------------------------------------------------===// 678 // Double shift instructions (generalizations of rotate) 679 //===----------------------------------------------------------------------===// 680 681 let Constraints = "$src1 = $dst" in { 682 683 let Uses = [CL] in { 684 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), 685 (ins GR16:$src1, GR16:$src2), 686 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", 687 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))], 688 IIC_SHD16_REG_CL>, 689 TB, OpSize; 690 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), 691 (ins GR16:$src1, GR16:$src2), 692 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", 693 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))], 694 IIC_SHD16_REG_CL>, 695 TB, OpSize; 696 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), 697 (ins GR32:$src1, GR32:$src2), 698 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", 699 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))], 700 IIC_SHD32_REG_CL>, TB; 701 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), 702 (ins GR32:$src1, GR32:$src2), 703 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", 704 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))], 705 IIC_SHD32_REG_CL>, TB; 706 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), 707 (ins GR64:$src1, GR64:$src2), 708 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}", 709 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))], 710 IIC_SHD64_REG_CL>, 711 TB; 712 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), 713 (ins GR64:$src1, GR64:$src2), 714 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}", 715 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))], 716 IIC_SHD64_REG_CL>, 717 TB; 718 } 719 720 let isCommutable = 1 in { // These instructions commute to each other. 721 def SHLD16rri8 : Ii8<0xA4, MRMDestReg, 722 (outs GR16:$dst), 723 (ins GR16:$src1, GR16:$src2, i8imm:$src3), 724 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 725 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, 726 (i8 imm:$src3)))], IIC_SHD16_REG_IM>, 727 TB, OpSize; 728 def SHRD16rri8 : Ii8<0xAC, MRMDestReg, 729 (outs GR16:$dst), 730 (ins GR16:$src1, GR16:$src2, i8imm:$src3), 731 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 732 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, 733 (i8 imm:$src3)))], IIC_SHD16_REG_IM>, 734 TB, OpSize; 735 def SHLD32rri8 : Ii8<0xA4, MRMDestReg, 736 (outs GR32:$dst), 737 (ins GR32:$src1, GR32:$src2, i8imm:$src3), 738 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 739 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, 740 (i8 imm:$src3)))], IIC_SHD32_REG_IM>, 741 TB; 742 def SHRD32rri8 : Ii8<0xAC, MRMDestReg, 743 (outs GR32:$dst), 744 (ins GR32:$src1, GR32:$src2, i8imm:$src3), 745 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 746 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, 747 (i8 imm:$src3)))], IIC_SHD32_REG_IM>, 748 TB; 749 def SHLD64rri8 : RIi8<0xA4, MRMDestReg, 750 (outs GR64:$dst), 751 (ins GR64:$src1, GR64:$src2, i8imm:$src3), 752 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 753 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, 754 (i8 imm:$src3)))], IIC_SHD64_REG_IM>, 755 TB; 756 def SHRD64rri8 : RIi8<0xAC, MRMDestReg, 757 (outs GR64:$dst), 758 (ins GR64:$src1, GR64:$src2, i8imm:$src3), 759 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 760 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, 761 (i8 imm:$src3)))], IIC_SHD64_REG_IM>, 762 TB; 763 } 764 } // Constraints = "$src = $dst" 765 766 let Uses = [CL] in { 767 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 768 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", 769 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), 770 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize; 771 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 772 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", 773 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), 774 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize; 775 776 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 777 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", 778 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), 779 addr:$dst)], IIC_SHD32_MEM_CL>, TB; 780 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 781 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", 782 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), 783 addr:$dst)], IIC_SHD32_MEM_CL>, TB; 784 785 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 786 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}", 787 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL), 788 addr:$dst)], IIC_SHD64_MEM_CL>, TB; 789 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 790 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}", 791 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL), 792 addr:$dst)], IIC_SHD64_MEM_CL>, TB; 793 } 794 795 def SHLD16mri8 : Ii8<0xA4, MRMDestMem, 796 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), 797 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 798 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, 799 (i8 imm:$src3)), addr:$dst)], 800 IIC_SHD16_MEM_IM>, 801 TB, OpSize; 802 def SHRD16mri8 : Ii8<0xAC, MRMDestMem, 803 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), 804 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 805 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, 806 (i8 imm:$src3)), addr:$dst)], 807 IIC_SHD16_MEM_IM>, 808 TB, OpSize; 809 810 def SHLD32mri8 : Ii8<0xA4, MRMDestMem, 811 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), 812 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 813 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, 814 (i8 imm:$src3)), addr:$dst)], 815 IIC_SHD32_MEM_IM>, 816 TB; 817 def SHRD32mri8 : Ii8<0xAC, MRMDestMem, 818 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), 819 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 820 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, 821 (i8 imm:$src3)), addr:$dst)], 822 IIC_SHD32_MEM_IM>, 823 TB; 824 825 def SHLD64mri8 : RIi8<0xA4, MRMDestMem, 826 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3), 827 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 828 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, 829 (i8 imm:$src3)), addr:$dst)], 830 IIC_SHD64_MEM_IM>, 831 TB; 832 def SHRD64mri8 : RIi8<0xAC, MRMDestMem, 833 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3), 834 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 835 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, 836 (i8 imm:$src3)), addr:$dst)], 837 IIC_SHD64_MEM_IM>, 838 TB; 839 840 } // Defs = [EFLAGS] 841 842 multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> { 843 let neverHasSideEffects = 1 in { 844 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2), 845 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 846 []>, TAXD, VEX; 847 let mayLoad = 1 in 848 def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst), 849 (ins x86memop:$src1, i8imm:$src2), 850 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 851 []>, TAXD, VEX; 852 } 853 } 854 855 multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> { 856 let neverHasSideEffects = 1 in { 857 def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 858 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, 859 VEX_4VOp3; 860 let mayLoad = 1 in 861 def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 862 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, 863 VEX_4VOp3; 864 } 865 } 866 867 let Predicates = [HasBMI2] in { 868 defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>; 869 defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W; 870 defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS; 871 defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W; 872 defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD; 873 defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W; 874 defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8, OpSize; 875 defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8, OpSize, VEX_W; 876 } 877
