1 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s 2 ; Avoid some 's' 16-bit instruction which partially update CPSR (and add false 3 ; dependency) when it isn't dependent on last CPSR defining instruction. 4 ; rdar://8928208 5 6 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { 7 entry: 8 ; CHECK: t1: 9 ; CHECK: muls [[REG:(r[0-9]+)]], r3, r2 10 ; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0 11 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]] 12 %0 = mul nsw i32 %a, %b 13 %1 = mul nsw i32 %c, %d 14 %2 = mul nsw i32 %0, %1 15 ret i32 %2 16 } 17 18 ; Avoid partial CPSR dependency via loop backedge. 19 ; rdar://10357570 20 define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind { 21 entry: 22 ; CHECK: t2: 23 %tobool7 = icmp eq i32* %ptr2, null 24 br i1 %tobool7, label %while.end, label %while.body 25 26 while.body: 27 ; CHECK: while.body 28 ; CHECK: mul r{{[0-9]+}} 29 ; CHECK-NOT: muls 30 %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ] 31 %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ] 32 %0 = load i32* %ptr1.addr.09, align 4 33 %arrayidx1 = getelementptr inbounds i32* %ptr1.addr.09, i32 1 34 %1 = load i32* %arrayidx1, align 4 35 %arrayidx3 = getelementptr inbounds i32* %ptr1.addr.09, i32 2 36 %2 = load i32* %arrayidx3, align 4 37 %arrayidx4 = getelementptr inbounds i32* %ptr1.addr.09, i32 3 38 %3 = load i32* %arrayidx4, align 4 39 %add.ptr = getelementptr inbounds i32* %ptr1.addr.09, i32 4 40 %mul = mul i32 %1, %0 41 %mul5 = mul i32 %mul, %2 42 %mul6 = mul i32 %mul5, %3 43 store i32 %mul6, i32* %ptr2.addr.08, align 4 44 %incdec.ptr = getelementptr inbounds i32* %ptr2.addr.08, i32 -1 45 %tobool = icmp eq i32* %incdec.ptr, null 46 br i1 %tobool, label %while.end, label %while.body 47 48 while.end: 49 ret void 50 } 51
