1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s 2 3 ; CHECK: t1 4 ; CHECK: vldmia 5 ; CHECK: vldmia 6 ; CHECK: vadd.i64 q 7 ; CHECK: vstmia 8 define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind { 9 entry: 10 %0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1] 11 %1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1] 12 %2 = add <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1] 13 %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1] 14 store <4 x i32> %3, <4 x i32>* %r, align 16 15 ret void 16 } 17 18 ; CHECK: t2 19 ; CHECK: vldmia 20 ; CHECK: vldmia 21 ; CHECK: vsub.i64 q 22 ; CHECK: vmov r0, r1, d 23 ; CHECK: vmov r2, r3, d 24 define <4 x i32> @t2(<2 x i64>* %a, <2 x i64>* %b) nounwind readonly { 25 entry: 26 %0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1] 27 %1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1] 28 %2 = sub <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1] 29 %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1] 30 ret <4 x i32> %3 31 } 32 33
